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This is a 42 pin DIL chip called 'HD61J215P' from Hitachi. Another Description for this chip is '64H156'. It can be found in older hardware, such as the famous Commodore VC1541 floppy. There it is used as a GCR-Controller (Group-code-encoding, Commodore's disk format instead of MFM). Therefore, you can find it also in many other floppy devices from Commodore (1551, 1570, 1571). Some floppy-drives contain also a 20 pin DIL FPGA, called '64H157' or '82S157'. Who knows more about these chips? Does anyone have any data-sheets of these FPGA?Article: 21151
Hi, Just happened to view your query. In fact, I am also quite new to this area. Noticed your VHDL source includes the archiecture behavious of ram/rom. Rrecently, I have done a project which also requires to design ram. My VHDL source is similar as yours, but later I encounter problems in synthesis...b'cos later I found out most fpga devices already have memory modules in the device. Such, there is no need to synthesize memory, so remove the architecture statement in your VHDL code for ram/rom design. Comment them out, and see the result. Let me know your result, I am also learning. Rgds, Wilson.Article: 21152
Ray Andraka wrote in message <38C64FE0.13682CCB@ids.net>...
>AFAIK, the xilinx software still doesn't support the tristate register for
4K
>parts.
And it won't be. One of the Xilinx apps guys sent me a private note about
that. He said a Change Request was reported in September of last year, and
it was "closed as Never Fix."
'tis a shame, because (IMHO) it's a damn useful feature.
-- a
-----------------------------------------
Andy Peters
Sr Electrical Engineer
National Optical Astronomy Observatories
950 N Cherry Ave
Tucson, AZ 85719
apeters (at) noao \dot\ edu
"Money is property; it is not speech."
-- Justice John Paul Stevens
Article: 21153Hi friends, Can somebody give me links about design verification. I mean following: Simulation and then comparison with test bench is only one (very slow) of verification methods. One other is if we have RTL HDL and low level HDL and can associate all registers. In this case we need only to compare combinatorial logic. I think you know also some other methods. If so reply on this posting pL. Another example: if you want to do hardware verification of some block (may be some sensitive core) by power-on. You can write test and then compare results with some palette. May be you know other methods. Any information and links (also very theoretical) would be appreciated. (My email: bonio.lopez@gmx.ch_remove_this ) Sent via Deja.com http://www.deja.com/ Before you buy.Article: 21154
Hal Murray wrote: > Could you please say a bit more. Are you talking about clean digital > systems where you just have to meet setup/hold times? > > How does what you are doing compare to the Xilinx party line that > says 0 hold so all you have to do is meet worst case setup? (I > think their "0 hold" really means that the min clk to out covers > the clock skew.) > That "Xilinx party line" ( I formulated it ) means just that, and it assumes that you use a global clock net. In local routing you might create long clock distribution delays that would generate hold time problems. Min delays can be of interest when driving external signals. PCI, for example, requires the data to keep driving the bus for at least 2 ns after the clock. Last time I looked, Actel gave "typical" values that you could then modify for temp and voltage extremes. Xilinx always gives "worst-case" values, i.e. longest delays. But we also give derating factors for hotter temperature. Mixing max and min values in one timing analysis can lead to ridiculous results, that's why we suggest a 70% tracking factor. ( Two parameters with the same worst-case delay will never deviate more than 30% from each other, even when at cold and high vcc, they are both much shorter than the worst-case max. This becomes important for figuring out pin-to-pin inpit set-up and hold times ( which we generally guarantee) Peter Alfke, Xilinx ApplicationsArticle: 21155
This is a multi-part message in MIME format. --------------89F9192E24C7ACC3A2344151 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Doubtful this is an FPGA. Try posting to sci.electronics.components. Jan Stumps wrote: > > This is a 42 pin DIL chip called 'HD61J215P' from Hitachi. Another > Description for this chip is '64H156'. > It can be found in older hardware, such as the famous Commodore VC1541 > floppy. > There it is used as a GCR-Controller (Group-code-encoding, Commodore's > disk format instead of MFM). > Therefore, you can find it also in many other floppy devices from > Commodore (1551, 1570, 1571). > Some floppy-drives contain also a 20 pin DIL FPGA, called '64H157' or > '82S157'. > > Who knows more about these chips? Does anyone have any data-sheets of > these FPGA? --------------89F9192E24C7ACC3A2344151 Content-Type: text/x-vcard; charset=us-ascii; name="jsmith.vcf" Content-Transfer-Encoding: 7bit Content-Description: Card for John L. Smith Content-Disposition: attachment; filename="jsmith.vcf" begin:vcard n:Smith;John L. tel;work:858-320-4102 x-mozilla-html:FALSE url:http://www.visicom.com org:Visicom;Imaging Products adr:;;10052 Mesa Ridge Court;San Diego;CA;92121;USA version:2.1 email;internet:jsmith@visicom.com title:Principal Engineer x-mozilla-cpt:;30864 fn:John L. Smith end:vcard --------------89F9192E24C7ACC3A2344151--Article: 21156
> > I'm figuring this one out. Synplify isn't all that great passing > constraints to Alliance. I've ended up putting some pin locks in > each place because it doesn't like them otherwise. OTOH, > Synplify does use timing for synthesis, so it's a two-edged > sword. > Synplify has a BUG passing constraints to Alliance. (See my posting to the thread "Passing multi-cycle timing constrains from Synplify to M1" ). You should turn off the "write vendor constraint file" option in Synplify OPTION menu, and define your own UCF. ----------------------------------------------- Rotem Gazit mailto:rotemg@mysticom.com MystiCom LTD. http://www.mysticom.com ----------------------------------------------- Sent via Deja.com http://www.deja.com/ Before you buy.Article: 21157
On Tue, 07 Mar 2000 06:57:25 GMT, Tobin Fricke <tobin@cory.eecs.berkeley.edu> was overheard to say: > I've recently become interested in microprocessor architecture and have > adopted as a personal project to implement a simple processor of some > sort in an Altera FPGA. I'd like to learn about the architectures and > implementations of various processors in use today and from the past. > I'm familiar with the general "big ideas" such as load-store > architectures, accumulator-architectures, etc, but I'd like to see some > real world designs. I'd like to find some information on the early > Intel and Motorola processors; where can I find data on the Intel 4004 > and 8080? How about the Motorola 6800? Is there some book or website > that offers a comparison of various designs? I'm also interested in > seeing a comparison of modern designs, such as x86, Alpha, MIPS, ARM, > PA-RISC, PowerPC, etc. A good text on *classic* processor design was written by Mick & Brick ~1980 (sorry, I never remember the title -- though the author's names are indelibly etched on my mind! Just like Honey Sue Elovitz... :>). It dealt primarily with bitslice design technologies (popular at the time). But, it will give you a good feel for how data moves through (what would now be considered "small, simple") processors, etc. I don't imagine it would still be in print -- though a good technical library would probably be able to dig up a copy. There is also a wealth of technical literature available from academia in the 60's in 70's (particularly) when lots of novel processor architectures were explored. Back then, it wasn't uncommon to have detailed descriptions of the actual designs of the CPUs published in the "instruction set manual"... --don -------------- Return address is bogus. Mail received at my "real" address is actively filtered to reduce spam. So, unless your address has been incorporated into that filter previously, don't bother sending mail -- it will be discarded before I see it. Sorry. --donArticle: 21158
Hi,
I'm quite new in FPGA, so all that new term are
a little bit confusing to me. Could anyone explain to me
what "ModelSim 2.1i" software is used for.
I heard of it from a colleague.
Thanks.
Abednego
Article: 21159Is it possible to use Logiblox modules in an ABEL design. If so, how would you instatiate the module? Thanks, ChuckArticle: 21160
Peter Alfke <peter@xilinx.com> writes: > Hal Murray wrote: > > > Could you please say a bit more. Are you talking about clean digital > > systems where you just have to meet setup/hold times? > > > > How does what you are doing compare to the Xilinx party line that > > says 0 hold so all you have to do is meet worst case setup? (I > > think their "0 hold" really means that the min clk to out covers > > the clock skew.) > > > > That "Xilinx party line" ( I formulated it ) means just that, and it assumes > that you use a global clock net. In local routing you might create long clock > distribution delays that would generate hold time problems. Interesting you mentioned that. There's a couple (two dozen) lines aimed for local clock routing in the Vitrex family. I tried to use them, but I couldn't figure out if there are any applicable timing constraint to keep the setup and hold times within bounds. I tried to floorplan (a first), so I put the clock pad on the top and the 10 data pads surrounding it. I still got some negative hold time. So, I want less than 3ns setup and less than 2 ns hold, which should be achievable. However, I want to put some timing constraint on the design, so I don't have to floorplan and I don't have to amnually check everything. Or, give an FPGA with nine(9) usable clock networks. Homann -- Magnus Homann, M.Sc. CS & E d0asta@dtek.chalmers.seArticle: 21161
On Wed, 08 Mar 2000 19:03:52 GMT, blackhole@rtd.com wrote: >A good text on *classic* processor design was written by >Mick & Brick ~1980 (sorry, I never remember the title -- though >the author's names are indelibly etched on my mind! Just like >Honey Sue Elovitz... :>). It dealt primarily with bitslice >design technologies (popular at the time). But, it will >give you a good feel for how data moves through (what would >now be considered "small, simple") processors, etc. > >I don't imagine it would still be in print -- though a good >technical library would probably be able to dig up a copy. 'Bit Slice Microprocessor Design', McGraw-Hill, ISBN 0-07-041781-4. A good book, and still relevant if you're building simple stuff. EvanArticle: 21162
Could anyone tell me how to successfully compile a pal design using Protels package? I use the CUPL wizard within the package and create a schematic however when I go to compile I get a lot of errors. Most seem to be generated by the fact that not all the internal logic outputs are being used (i.e. using only 9 bits of a 16 bit counter). I have tried placing no connects on these pins but to no avail. I want the compiled jedec output file to fit into a GAL22V10. thanks SteveArticle: 21163
Magnus Homann wrote: > I tried to floorplan (a first), so I put the clock pad on the top and > the 10 data pads surrounding it. I still got some negative hold time.... Negative hold time is good. Positive hold time is what you should be afraid of. Peter Alfke >Article: 21164
Abednego wrote in message <8a68jp$ag1$1@bagan.srce.hr>...
>
>Hi,
>
> I'm quite new in FPGA, so all that new term are
>a little bit confusing to me. Could anyone explain to me
>what "ModelSim 2.1i" software is used for.
>I heard of it from a colleague.
you're confusing two different software packages.
1) ModelSim is Model Technology's VHDL/Verilog simulation software package.
It's currently up to version 5.3d. You use it to simulate your (V)HDL code
before synthesizing and implementing in an FPGA. ModelSim is "technology
independent." It can be used to simulate designs that are going to be
implemented in any FPGA family.
2) Xilinx's Foundation and Alliance tools are currently at version 2.1i
service pack 4. These tools are used to create and implement a design in an
FPGA. You cannot use the Xilinx tools to implement an Actel or an Altera
part.
If you are not using VHDL or Verilog, you do not need ModelSim. You *do*
need the 2.1i tools if you are targetting a Xilinx part.
-- a
-----------------------------------------
Andy Peters
Sr Electrical Engineer
National Optical Astronomy Observatories
950 N Cherry Ave
Tucson, AZ 85719
apeters (at) noao \dot\ edu
"Money is property; it is not speech."
-- Justice John Paul Stevens
Article: 21165On Wed, 8 Mar 2000 12:31:10, Utku Ozcan <ozcan@netas.com.tr> wrote: > I don't know if it is the same for PCs. AFAIK PCs can have > more than one processor on the machine, but I think the > processor share is totally dependent upon operating system > and the executable that takes the advantage of multithreading > (sharing the process -program- into more than one processor). I'm quite sure that Xilinx' P&R NT tools aren't SMP friendly either. Windows may do SMP, but it will still can't thread software that isn't threaded to begin with. It may be able to run different jobs on two processors and the OS may be able to swap them around, but this doesn't help P&R performance. I am rather surprised that P&R is so coupled to processor performance. My PII-333 is 66MHz X 3.5 and the PIII-600 is 100MHz X 6, yet the numbers are very close to double for the 600. Oh well, I guess it's time to hit up the boss for new toys ;-) ..actually I was hoping to do this on a laptop, but that doesn't seem possible. --- KeithArticle: 21166
On Wed, 8 Mar 2000 18:50:29, rotemg@mysticom.com wrote: > > > > > I'm figuring this one out. Synplify isn't all that great passing > > constraints to Alliance. I've ended up putting some pin locks in > > each place because it doesn't like them otherwise. OTOH, > > Synplify does use timing for synthesis, so it's a two-edged > > sword. > > > Synplify has a BUG passing constraints to Alliance. > (See my posting to the thread "Passing multi-cycle timing constrains > from Synplify to M1" ). > You should turn off the "write vendor constraint file" option in > Synplify OPTION menu, and define your own UCF. I'm quiclky coming to the same conclusion, though this means specifying everything twice. The tools are verbose enough, this isn't going to be fun. ---- KeithArticle: 21167
If you are using XACT 6.0 annd NOT the Aliance M1 Xilinx tools than from within the XACT design manager you select the top level schematic of your design from your viewlogic project directory. When you implement the design it runs an xilinx utility wir2xnf (in the translate step) to create xilinx xnf files from the viewlogic wir files. If you are using M1 alliance from Xilinx, than you need to select an EDIF netlist in the Design manager as the newer M1 tools do not translate the wir files to xnf files anymore (wir2xnf). Do what Remi suggested you do. This adds custom utilities to the ViewLogic tools menu from within Viewdraw to write Xilinx EDIF netlist. Zhibin Dai <zdai@uoguelph.ca> wrote in message news:8a3tt2$qqc$1@testinfo.cs.uoguelph.ca... > Hi, > > I have some questions for WorkView Office and Alliance XACT: > > 1. Can Workview Office generate a .XNF netlist from ViewDraw? I only got > .WIR files. > > 2. I produced a .EDN file from a Schematic by using EDIF tools in WVO. > But when I use it on Alliance XACT to perform mapping, I got a message: > > ERROR:basnu:93 - logical block "$1I30/$1I1" of type "NOR2" is unexpanded. > > I think I missed something. What's wrong? > > > 3. Is there a way to get information like switch consumption, number of > connections and average length of connection in Xilinx tools? > > > I appreciate any advice you provided! > > > > ZhibinArticle: 21168
Peter Alfke wrote:
> Last time I looked, Actel gave "typical" values that you could then modify for
> temp and voltage extremes. Xilinx always gives "worst-case" values, i.e.
> longest delays. But we also give derating factors for hotter temperature.
Hi Peter,
With the Actel tools, you can set the environmental conditions and it will perform
calculations for either best, typical, or worst-case. Environmental conditions
that you can dial in are speed grade, temperature, voltage, and, where applicable,
radiation level. Process variations, including antifuse resistance, is handled in
the case selection. In the data book, they typically give min or max values along
with derating curves for temperature and voltage. Of course, for accuracy, the
post place and route extracted delay calculations are the most accurate.
Have a good evening,
----------------------------------------------------------------------
rk The Soviets no longer were a threat
stellar engineering, ltd. in space, and in the terms that
stellare@erols.com.NOSPAM became commonplace among the veteran
Hi-Rel Digital Systems Design ground crews, as well as the
astronauts, the dreamers and builders
were replaced by a new wave of NASA teams, bureaucrats who swayed with
the political winds, sadly short of dreams, drive, and determination
to keep forging outward beyond earth. -- Shepard and Slayton.
Article: 21169Yeah, the unofficial rumors I've heard have all been that they are doing nothing more on the 4K/spartan part of the software. That means we're stuck with the relatively broken floorplanner etc (relative to what we had in Xact6). Looks to me like the 4K architecture is slowly being led out to pasture. Andy Peters wrote: > Ray Andraka wrote in message <38C64FE0.13682CCB@ids.net>... > > >AFAIK, the xilinx software still doesn't support the tristate register for > 4K > >parts. > > And it won't be. One of the Xilinx apps guys sent me a private note about > that. He said a Change Request was reported in September of last year, and > it was "closed as Never Fix." > > 'tis a shame, because (IMHO) it's a damn useful feature. > > -- a > ----------------------------------------- > Andy Peters > Sr Electrical Engineer > National Optical Astronomy Observatories > 950 N Cherry Ave > Tucson, AZ 85719 > apeters (at) noao \dot\ edu > > "Money is property; it is not speech." > -- Justice John Paul Stevens -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 21170
Magnus Homann wrote: > > Peter Alfke <peter@xilinx.com> writes: > > That "Xilinx party line" ( I formulated it ) means just that, and it assumes > > that you use a global clock net. In local routing you might create long clock > > distribution delays that would generate hold time problems. > > Interesting you mentioned that. There's a couple (two dozen) lines > aimed for local clock routing in the Vitrex family. I tried to use > them, but I couldn't figure out if there are any applicable timing > constraint to keep the setup and hold times within bounds. > > I tried to floorplan (a first), so I put the clock pad on the top and > the 10 data pads surrounding it. I still got some negative hold time. > So, I want less than 3ns setup and less than 2 ns hold, which should > be achievable. However, I want to put some timing constraint on the > design, so I don't have to floorplan and I don't have to amnually > check everything. > > Or, give an FPGA with nine(9) usable clock networks. > > Homann > -- > Magnus Homann, M.Sc. CS & E > d0asta@dtek.chalmers.se I think the setup and hold times that Peter is talking about are for internal paths from one FF to another or input or output FFs in the IOBs. For the internal FFs, if I understand things correctly, Xilinx simply guarantees that the hold time will be met under all conditions (provided the clock distribution is used). You then specify the clock rate and the timing tools tell if the routing tools met the setup times. The clock pin to IOB pin setup and hold are specified in the databooks. Again, the assumption is that the proper clock distribution is used. But I believe you can get 0 ns (or negative) hold if you allow the input delay to be used. This gives you a larger setup time. If you want a smaller setup time, you take out the delay and you get a positive hold time. The Xilinx datasheet that I have lists only the pin to pin timing for LVTTL signals with delay. If you use the DLL, you can meet your requirements no problem. If you don't use the DLL, then it depends on the speed grade, the part size and I can't tell about turning off the delay option. Does this help? -- Rick Collins rick.collins@XYarius.com remove the XY to email me. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 21171
Andy Peters wrote: > > 2) Xilinx's Foundation and Alliance tools are currently at version 2.1i > service pack 4. These tools are used to create and implement a design in an > FPGA. You cannot use the Xilinx tools to implement an Actel or an Altera > part. Bzzzzt. Nope, it's March, the Service Pack of the month this month is.... You guessed it, Number 5. And they still don't have my show-stopper bugs from SP2 fixed. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 21172
On Wed, 8 Mar 2000 09:40:24 -0700, "Andy Peters" <apeters.Nospam@nospam.noao.edu.nospam> wrote: >Ray Andraka wrote in message <38C64FE0.13682CCB@ids.net>... > >>AFAIK, the xilinx software still doesn't support the tristate register for >4K >>parts. > >And it won't be. One of the Xilinx apps guys sent me a private note about >that. He said a Change Request was reported in September of last year, and >it was "closed as Never Fix." > >'tis a shame, because (IMHO) it's a damn useful feature. Am I missing something here? My '99 databook shows that the 4000/Spartan parts do not have a register on the tristate control in the IOB. Only the Virtex/Spartan2 parts have the register. Ta, Allan.Article: 21173
In comp.arch.fpga Norm Ebsary <norm@dtinetworks.com> wrote: > Hey, why are you not looking at www.open-cores.org? DNS Domain 'www.open-cores.org' is invalid: Host not found (authoritative). +volker-Article: 21174
Rickman <spamgoeshere4@yahoo.com> writes: [Deleted Homann's tired rantings about negative hold time, when he really meant positive hold time] > I think the setup and hold times that Peter is talking about are for > internal paths from one FF to another or input or output FFs in the > IOBs. For the internal FFs, if I understand things correctly, Xilinx > simply guarantees that the hold time will be met under all conditions > (provided the clock distribution is used). You then specify the clock > rate and the timing tools tell if the routing tools met the setup times. > > The clock pin to IOB pin setup and hold are specified in the databooks. > Again, the assumption is that the proper clock distribution is used. But > I believe you can get 0 ns (or negative) hold if you allow the input > delay to be used. This gives you a larger setup time. If you want a > smaller setup time, you take out the delay and you get a positive hold > time. It is used, and I still get positive hold time, about 0.7 ns. I also get negative setup time, so the window isn't very big. I just want to constrain the P&R, and the timing analyzer so that it would check it for me. Note: I'm trying to use the secodnary clock routing resource, as I'm using the global resource for Other Stuff (four truly global clocks). > The Xilinx datasheet that I have lists only the pin to pin timing for > LVTTL signals with delay. If you use the DLL, you can meet your > requirements no problem. If you don't use the DLL, then it depends on > the speed grade, the part size and I can't tell about turning off the > delay option. Not really. I need 8 of these clocks, and there are only four DLLs (and global clock dist.) in the Virtex family. -- Magnus Homann, M.Sc. CS & E d0asta@dtek.chalmers.se
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Compare FPGA features and resources
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