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Messages from 21825

Article: 21825
Subject: Re: Shuttle Backup Computers and "Diverse Design" - Single Point Failures
From: rk <stellare@nospam.erols.com>
Date: Sun, 02 Apr 2000 17:30:35 -0400
Links: << >>  << T >>  << A >>
Crossposting to comp.arch.fpga where this conversation started out, as a
discussiona bout single point failures.  Continue below.

rk

===================================

 Jorge R. Frank wrote:

} rk wrote:
} >
} > Hi,
} >
} > Off in another group we were talking about single point failures and
} > "diverse design" to ensure that common design errors don't make
} > redundancy meaningless.  One example is the Space Shuttle's fifth
} > computer, with one poster claiming that the astronauts would never use
} > it.  Any comments?
}
} Well... I don't know who claimed that.  I certainly *hope* crews never
} have to use it; a lot of simplifications had to be made to make all the
} ascent, abort, entry, and systems management software fit into a single
} memory configuration. There's no reason to believe that it wouldn't
} *work*... it's tested as thoroughly as the primary software, and crews
} regularly train to fly it (and the training simulators use real flight
} computers running the real software, not a simulation of same...)
}
} Perhaps the poster was making the claim on the basis that the failure
} scenarios that would require engaging the backup computer are too
} unlikely. Well, all it would take is *one* bug in the primary software
} getting through testing.  That's unlikely, but it would be arrogant to
} claim it *couldn't* happen.  Another scenario would be two primary
} computers "hearing" something on a flight-critical data bus that the
} other two didn't... and all *that* would take would be a noisy data bus,
} something that could be caused by, say, a screw rubbing through the
} insulation on the bus wiring.  Naw, *that'll* never happen...

Hi Jorge,

Thanks for the response.  I have included a few of the posts from the
previous thread; this is an interesting one and one where these two groups
do have some overlap.  As part of this discussion, I have included a small
section from an ACM article where a software error did get through, but was
caught in the simulator.

Also, if I remember correctly (I had a *rough* weekend so I may not be quite
at my best), weren't two engine controllers affected by the wire damage in
flight?

Have a good weekend,

rk

===============================================================
===============================================================




Subject:       Re: FPGA & single point failure
Date:          30 Mar 2000 03:18:44 GMT
From:          krw@attglobal.net (Keith R. Williams)
Organization:  Global Network Services - Remote Access Mail & News Services
Newsgroups:    comp.arch.fpga


Understood. However, the fact is that the astronauts have told
the OBS people that they would never pull the lever in flight.
By the time time things got so bad that they'd try
un-FLIGHT-tested software they'd be dead, or so hopelessy lost
that it wouldn't matter.  Note that they won't test the backup
software on a nominal flight.

It's one thing to screw up in the simulator because you're "dead"
and another kettle-o-fish to be in space and pull the plug on
something you've always trusted.  With the dynamics there isn't
time to react and any reaction is *going* to go with what you
know - right or wrong.

On Wed, 29 Mar 2000 03:21:33, rk <stellare@nospam.erols.com>
wrote:

} Keith R. Williams wrote:
}
} > > The one example of a system with diversity that I am aware of is the
Space
} > > Shuttle's main computer system.  It consists of 5 computers, with
identical
} > > hardware.  The software, however, is identical on the 4 computers that

} > > actually do the work.  A fifth computer, running but not controlling
the
} > > vehicle unless commanded to, runs software developed by a completely
} > > independent team.
} >
} > This is correct.  Note the astronauts have also said that they
} > would never pull the switch to go to the redundant software (it
} > is a manual override).  They trust the Shuttle OBS and have never
} > tried the other.
} > >
} > > Anyone else know of any other examples?
} >
} > Other than multiple parallel, but identical, TMR circuits in a
} > crypto processor I don't know of any.  It's incredibly expensive
} > to duplicate everything, especially the intellectual part.  Then,
} > when you get an error after years of fault-free operation, do you
} > want to trust a newbie?  When do you make that determination?
} > ..likely when things have gone so wrong it's too late.  I
} > believe it's better to throw that money and tallent at making
} > sure the original problem is solved.  I believe the Shuttle OBS
} > is evidence of this, both ways.
}
} Here's an excerpt from:
}
}    The Space Shuttle Primary Computer System
}    A. Spector and D. Gifford
}    Communications of the ACM, September, 1984, p. 874
}
} which is "interesting" ...
}
}
}      AS. Could you describe a training scenario on the SMS that caused a
problem
}      for you?
}
}      Clemons.  Yes - it was a "bad-news - good-news" situation.  In 1981,
just
}      before STS-2 was scheduled to take off, some fuel spilled on the
vehicle and
}      a number of tiles fell off.  The mission was therefore delayed for a
month
}      or so.  there wasn't much to do at the Cape, so the crew came back to

}      Houston to put in more time on the SMS.
}
}      One of the abort simulations they chose to test is called a
"TransAtlantic
}      abort," which supposes that the crew can neither return to the launch
site
}      nor go into orbit.  The objective is to land in Spain after dumping
some
}      fuel.  The crew was about to go into this dump sequence when all four
of our
}      flight computer machines locked up and went "catatonic."  Had this
been the
}      real thing, the Shuttle would probably have had difficulty landing.
This
}      kind of scenario could only occur under a very specific and unlikely
}      combination of physical and aerodynamic conditions; but there it was:
Our
}      machines stopped.  Our greatest fear had materialized - a generic
software
}      problem.
}        We went off to look at the problem.  The crew was rather upset, and
they
}      went off to lunch.
}
}      AS. And contemplated their future on the next mission?
}
}      Clemons.  We contemplated our future too.  We analyzed the dump and
}      determined what had happened.  Some software in all four machines had

}      simultaneously branched off into a place where there wasn't any code
to
}      branch off into.  This resulted in a short loop in the operating
system that
}      was trying to field and to service repeated interrupts.  No
applications
}      were being run.  All the displays got a big X across them indicating
that
}      there were not being serviced.
}
} rk

Article: 21826
Subject: Re: Shuttle Backup Computers and "Diverse Design"
From: rk <stellare@nospam.erols.com>
Date: Sun, 02 Apr 2000 17:46:04 -0400
Links: << >>  << T >>  << A >>
Hi Lynn,

Lynn Killingbeck wrote:

> rk wrote:
> >
> > Hi,
> >
> > Off in another group we were talking about single point failures and
> > "diverse design" to ensure that common design errors don't make
> > redundancy meaningless.  One example is the Space Shuttle's fifth
> > computer, with one poster claiming that the astronauts would never use
> > it.  Any comments?
> >
> > Additionally, does anyone have any other examples of systems where
> > diverse design was used and why?
> >
> > Have a good evening,
> >
> > rk
>
> Of course there are situations where they will use it! Suppose that the
> hypothetical "generic software error" becomes real, and _all_ of the
> four primary computers throw a fit and quit working - simultaneously. Do
> you seriously think that the crew would say something like "We'd rather
> face a certain death with the broken (they are not running!) primarys,
> than engage the backup and at least hope!"? There's not supposed to be
> such an animal as a generic software error in the verified code. But
> that is a rather complex piece of software, and no one I know (and
> believe!) will absolutely, postiviely, 100% guarantee (e.g., with
> forfeiture of that person's own life if such a failure happens) there is
> no such thing.

I agree.  However, the previous poster seemed to believe they would not use
the backup.


     Understood. However, the fact is that the astronauts have told
     the OBS people that they would never pull the lever in flight.
     By the time time things got so bad that they'd try
     un-FLIGHT-tested software they'd be dead, or so hopelessy lost
     that it wouldn't matter.  Note that they won't test the backup
     software on a nominal flight.

In the ACM article [September '84] they give an example, before the second
flight, if I recall correctly, where the simulator locked up from a software
error during a transatlantic abort.

Having designed quite a bit of circuitry for hi-rel missions [unmanned] that
employ redundancy, it's tough to *guarantee* that everything is correct and
no design faults have gotten through design, analysis, review, and test.

======================================

> It isn't that diverse a system (reading a lot into you undefined term).

I knew the concept but another poster introduced the term.  I had found the
following, which I will repeat here:

     Going through various notes and references laying around, I can only
     quickly find one  more reference to diverse systems in _Reducing Space
     Mission Cost_, Wertz and Larson.   Here's a quick quote (p. 299):

          In diverse design redundancy two or more components of different
     design furnish the same service.  This has two advantages: it offers
     high protection against failures due to design deficiencies, and it can
     offer lower cost if the back-up unit is a "life-boat," with lower
     accuracy and functionality, but still adequate for the minimum mission
     needs.  The installation of diverse units usually adds to logistic cost
     because of additional test specifications, fixtures, and spare parts.
     This form of redundancy is, therefore, economical primarily where the
     back-up unit comes from a previous satellite design, or where there is
     experience     with it from another source.  Where there is concern
     about the design integrity of a primary component, diverse design
     redundancy may have to be employed regardless of cost.  [Unfortunately
     they don't give, in their case studies, specific examples of this, or
     at least none that I could find at this hour].

Like most things, the amount of "diversity" is a trade-off.  I can think of
few systems that have diversity and have not worked on one myself.  Surrey
Satellite uses it.

Thanks,

An interesting topic,

Have a good evening,

rk

Article: 21827
Subject: Re: FPGA openness
From: Zoltan Kocsi <root@127.0.0.1>
Date: 03 Apr 2000 11:02:18 +1000
Links: << >>  << T >>  << A >>
krw@attglobal.net (Keith R. Williams) writes:

> > Can you do that ? I mean copyright an arbitrary sequence of bits,
> > with all the DMCA protection, 70 years after author's death and all ?
> > What is the minimum length ? 
> 
> Sure.  The fact that you've created "art" means it's copyrighted.
>  You can *register* a copyright and in fact you must if you wish 
> to sue.

I think you misunderstood me. I was not talking about the FPGA 
design or a microprocessor program. 

I was talking about the bitstream as such, that is, can I register
an arbitrary sequence of 1s and 0s (of which of course I am the 
author), expressed in any bi-valued way as my intellectual property ? 

It would raise a few issues, I think:

- how long is the shortest copyrightable bitstream ?

- how do you search for violations ? This involves the issue 
  of reverse-engineering and trying to access material that
  is access controlled. Say, you suspect that a DVD movie 
  contains your bitstream, but you can't decode the DVD to
  check it because it would be criminal activity, according 
  to the MPAA. Evidence obtained in illegal means is not 
  admissible in court.

- how long of a sequence of bits that maches a portion of 
  your copyrighted stream is considered fair use ?
  
- how many changed bits are needed to the resulting bitstream
  to be considered as based on the original ?
  
- if there's a bitstream which by applying an algorithm (e.g.
  drop every second bit from it) can be transformed to the original
  stream, is it a violation ? How complex the algorithm can be to 
  claim violation, knowing that a complex enough algorithm can 
  transform any bitstream to any other bitstream ?
  
Zoltan

-- 
+------------------------------------------------------------------+
| ** To reach me write to zoltan in the domain of bendor com au ** |
+--------------------------------+---------------------------------+
| Zoltan Kocsi                   |   I don't believe in miracles   |  
| Bendor Research Pty. Ltd.      |   but I rely on them.           |
+--------------------------------+---------------------------------+

Article: 21828
Subject: Error during synthesis
From: "Tomasz Brychcy" <tbrychcy@sensor.ime.pz.zgora.pl>
Date: Mon, 3 Apr 2000 07:40:25 +0200
Links: << >>  << T >>  << A >>
Hello,

it's a next error :
Clock variable 'CLOCK' is being used as data;

I do not know what mean and why is the error?
 I attach you the file which the error is

With regards

Tomasz Brychcy



begin 666 mode_0_s.v
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M*2!B96=I;@T*#0H):68@*$Y%6%1?0TQ/0TM?4%5,4T4]/3$G8C$I(&)E9VEN
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M\W=N>2!&1F@I#0H)"65N9 T*"0EE;'-E(&EF("A,4T)?35-"/3TQ)V(Q("8F
M(%)/3$Q%1#T],2=B,"D-"@D)"4-/54Y424Y'/3$G8C ["0D)"0DO+WIA=')Z
M>6UA;FEE('IL:6-Z86YI82!L:6-Z;FEK80T*"6EF("A-3T1%/3TS)V(P,# @
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M1%]'051%/3TQ)V(Q("8F($-/54Y424Y'/3TQ)V(Q*2!B96=I;@D)"0D)+R]W
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M($Y53$Q?0T4A/3$G8C$I(&)E9VEN"0DO+VIEG&QI(&QI8WIN:6L@;W-IN6=N
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M,3L-"@D)"65N9 T*"0D)96QS92!I9B H0T4]/3$V)V(P,# P7S P,#!?,# P
M,%\P,# P*2!B96=I;@T*"0D)"4-%/3$V)VAF9F9F.PD)"0D)+R]T;R!#12!M
M=7-I('IO<W1AYB!U<W1A=VEO;GD@;F$@,C4U("AI(&]D('1E:B!W87)T;YQC
M:2!Z;&EC>F$@9&%L96HI#0H)"0D)3E5,3%]#13TQ)V(P.PT*"0D)"5)/3$Q%
M1#TQ)V(Q.PD)"0D)+R]T;R!Z;F%C>GDL(+]E(&QI8WIN:6L@<VEE('!R>F5K
M<NIC:;,-"@D)"65N9 T*"0EE;F0-"@D)"0T*"65N9 T*"65L<V4@:68@*$U/
M1$4]/3,G8C P," F)B!"24Y?0D-$/3TQ)V(Q*0D)"0D)"2\O>FQI8WIA;FEE
M('<@:V]D>FEE($)#1 T*"3L-"@D)#0IE;F0-"@T*96YD;6]D=6QE#0H-"@T*
`
end

Article: 21829
Subject: Re: APS V240 board
From: "Kate Atkins" <kate.atkins@siraeo.nospam.co.uk>
Date: Mon, 3 Apr 2000 12:56:39 +0100
Links: << >>  << T >>  << A >>
Richard

Thankyou for the new info.

Unfortunately the RevB datasheet disagrees with the schematic for FPGA pins
175 (actually SRAMDQ2) and 176 (actually SRAMDQ3).

Regards

Kate Atkins

Richard Schwarz <rick@apsfpga.com> wrote in message
news:38E4EFE3.D175BFB6@apsfpga.com...
> Kate,
>
> Sorry for the confusion. The APS-V240 Rev A data sheet did have an error
on the
> PC-104 pin out. The new sheet can be seen at:
>
> http://www.associatedpro.com/v240.pdf
>
> Also I will email it to you. You should have also gotten some scheamtics
and
> examples on a CD. I will email the schematics, just in case. Let me know
if you
> did not get the CD.
>
> Richard Schwarz,  President  APS
>
> Kate Atkins wrote:
>
> > Hi all
> >
> > We have one of these boards and are having some hassle because the data
> > sheet on the web site gives the wrong FPGA to PC104 bus interface pin
> > mapping. We are also not sure about the FPGA to ZBT RAM pin mapping (or
any
> > of the rest of it). This part of the data sheet appears to have been
copied
> > from the X240 data sheet but doesn't match the PCB.
> >
> > APS have not replied to our emails about this. Before we resort to
> > microscope and continuity tester can anybody help with any more info?
> >
> > Regards
> >
> > Kate
>


Article: 21830
Subject: HIPO - Hierarchy Input Process Output
From: Virginia Horseman <horsemanone@my-deja.com>
Date: Mon, 03 Apr 2000 12:39:26 GMT
Links: << >>  << T >>  << A >>



Does anyone have any links to sites that have HIPO - (Hierarchy Input
Process Output) methodology?

Thanks.

Gregg Jones


Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 21831
Subject: Re: Adrian Thompson's and GA work on Xilinx
From: seamang@westminster.ac.uk (Graham Seaman)
Date: 3 Apr 2000 13:30:32 GMT
Links: << >>  << T >>  << A >>
Craig Slorach (craigs@elec.gla.ac.uk) wrote:
: One option is to host a 6200 like architecture on an existing FPGA by
: creating a 'virtual structure' on an existing FPGA. I have done some work on
: this and can provide an overview and details where necessary. This approach
: is by no means an optimal use of resources on the target FPGA but it can be
: done. 
What FPGA have you done it for? Are the details available anywhere?

Thanks
Graham

Article: 21832
Subject: PCI test bench ??
From: sja@world.std.com (Stuart J Adams)
Date: Mon, 3 Apr 2000 14:11:47 GMT
Links: << >>  << T >>  << A >>
 Can anyone recommend a PCI test bench 
 that I can use to validate PCI compliance 
 of my CPLD/FPGA PCI core ???

 (I was hoping to find something that would 
  test for all of the items in the PCI compliance
  checklist)

Thanks,
  Stuart

Article: 21833
Subject: need FIFOs, urgent!
From: Erik Lins <Erik.Lins@exp2.physik.uni-giessen.de>
Date: Mon, 03 Apr 2000 16:25:52 +0200
Links: << >>  << T >>  << A >>
Hello everyone,

I would need a small amount of Cypress CY7C433-40AC FIFOs very urgent.
The 433 is not so important (429, 460 etc. ok, too) and -40 ist also not
important (might be faster or so). Very important is AC, which is
TQFP-32 package, which I was not able to find at any german ditributor.

Could anyone provide me with 10 or 20 pieces ?

Thank you in advance,
Erik Lins
+49-6403-925353
Email: erik@lins.de
Article: 21834
Subject: Re: Error during synthesis
From: "Xanatos" <deletemeaoe_londonfog@hotmail.com>
Date: Mon, 03 Apr 2000 14:44:14 GMT
Links: << >>  << T >>  << A >>
news:8c9ara$gvt$1@okapi.ict.pwr.wroc.pl...
> Hello,
>
> it's a next error :
> Clock variable 'CLOCK' is being used as data;
>
> I do not know what mean and why is the error?
>  I attach you the file which the error is
>
> With regards
>
> Tomasz Brychcy
>
Tomasz,

I took alook at the code....and here is one of two errors that are causing
you grief:

>>
always @(posedge CLOCK)

 if (CLOCK==1'b1 && OPEN_GATE==1'b1)
  P=1'b1;
 else
  P=1'b0;
>>

Why are you using CLOCK==1'b1 here. The block will only execute on the
rising edge of CLOCK, which is going to infer '1' anyway. Just use
 if (OPEN_GATE==1'b1)
  P=1'b1;
 else
  P=1'b0;

for that always block.
The other one I noticed is a negedge CLOCK, and a if (CLOCK==0) or some
sort. Fix that one two.

Lemmie know if that works....as I am far from a verilog expert.
Xanatos


Article: 21835
Subject: Re: Virtex DLL Spread-spectrum clock sensitivity
From: Austin Lesea <austin.lesea@xilinx.com>
Date: Mon, 03 Apr 2000 09:05:59 -0700
Links: << >>  << T >>  << A >>
Jeffrey,

Are you intending to apply a spread spectrum clock to the input of the DLL?

If this is the case, the absolute, edge to edge change in delay (frequency) can
not be any greater than that stated in the data sheet.  The reason for this is
that the loop will not be able to track and lock if the edge to edge change
prevents the detectors from figuring out when a complete cycle is in the delay
line.

As long as the edge to edge change is not exceeded, the DLL is designed to track
over voltage and temperature variations, so that even though FM'ing or PM'ing
modulation will be of greater deviation and faster than a voltage or temperature
variation, the loop should track it just fine.

We are doing some measurements now, and should have results in a week or so.

I would also expect that if the change (however slow) was too great, the delay
line would eventually lose the edge by stepping off the end.  I am trying to
quantify "too great".

Remember to take the worst case time delta into account in your design, and
remember that the DLL is NOT a PLL and does NO jitter filtering (what you get
out, is what you put in).

The good news:  the DLL is not a PLL, and behaves in a quite predictable,
deterministic fashion (when did you ever see a PLL with a LOCKED signal that
worked?)

Austin

jeffrey j cook wrote:

> Is anyone aware of any hindering issues of using a spread-spectrum clock when
> driving the Virtex, especially when it comes to using the DLL's?
>
> Thanks.
>
> Jeffrey J. Cook
> jjc@ieee.org
> --
> "Sometimes the easiest way to get something done is to be a little na´ve
> about it -- and just ship it."
> Bill Joy, Sun Microsystems  - Jini Engineer

Article: 21836
Subject: Xilinx student edition, version 1.5
From: myself@magma.ca (myself)
Date: Mon, 03 Apr 2000 18:42:59 GMT
Links: << >>  << T >>  << A >>
Hi 
has Anyone used the
Xilinx student edition, version 1.5

I am unclear on the software that comes with this book!
I want to write VHDL code for  FPGA's. 
I am not interested in schematic entry.


Does this book cover VHDL? 
Does this book include the "Foundation" series of software?
What series and version is it? (Does it support VHDL)?

Any other books that come with vhdl software and practical examples? 

Martin Brown

Article: 21837
Subject: Re: Xilinx student edition, version 1.5
From: Luke Roth <roth@spaten.cse.psu.edu>
Date: Mon, 3 Apr 2000 15:10:51 -0400
Links: << >>  << T >>  << A >>
	Yes, I've used it a bit.  The student package comes with a limited
version of the Foundation tools, v1.5.  It is several steps behing the
current version (v2.1i, IIRC) but is perfecty functional.  It is limited
to devices no larger that the XC4010, but it does handle both VHDL
synthesis and schematic entry.
	The book that comes with it is well written for a beginner, and
most of its example designs are shown using VHDL, ABEL, and schematic
entry.  It's not a comprehensive reference, but the examples are well
written (if a bit basic).  I have heard that Xilinx will be upgrading the
package to use the v2.1 foundation tools (which support the newer
SpartanII/Virtex architecture, probably with the same gate count
limitation) for the fall semester.
	Luke

On Mon, 3 Apr 2000, myself wrote:

> Hi 
> has Anyone used the
> Xilinx student edition, version 1.5
> 
> I am unclear on the software that comes with this book!
> I want to write VHDL code for  FPGA's. 
> I am not interested in schematic entry.
> 
> 
> Does this book cover VHDL? 
> Does this book include the "Foundation" series of software?
> What series and version is it? (Does it support VHDL)?
> 
> Any other books that come with vhdl software and practical examples? 
> 
> Martin Brown
> 
> 

Article: 21838
Subject: Re: Xilinx student edition, version 1.5
From: elynum@my-deja.com
Date: Mon, 03 Apr 2000 20:10:36 GMT
Links: << >>  << T >>  << A >>
In article <38e8e6e1.19193205@news.magma.ca>,
myself@magma.ca (myself) wrote:
> Hi
> has Anyone used the
> Xilinx student edition, version 1.5
>
> I am unclear on the software that comes with this book!
> I want to write VHDL code for FPGA's.
> I am not interested in schematic entry.
>
> Does this book cover VHDL?
> Does this book include the "Foundation" series of software?
> What series and version is it? (Does it support VHDL)?
>
> Any other books that come with vhdl software and practical examples?
>
> Martin Brown
>
> I have the version 1.3 of that book.  It is an excellent book.  I
believe that version 1.5 does have a vhdl simulator in conjunction with
schematic entry.  It should be in the back of your book in the CD's that
come with the book.  The book covers mostly verilog but their are vhdl
versions of the verilog code.  You must go online to this web page to
get the vhdl equivalent => www.xess.com just do a search on vhdl and you
should come up with the vhdl version of the labs that you can download.
Also, there is a forum that you can sign up for once you get to that web
page that I have found very helpful.  You should also, consider buying
their fpga hardware board so you can actually see your code at work or
go the cheap route to build your own. I built my own version of their
hardware.  Would I do it again, nope! Save yourself the time unless you
want to learn how to wirewrap, solder and learn debug, and buy it.


Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 21839
Subject: Re: Xilinx student edition, version 1.5
From: Dave Vanden Bout <devb@xess.com>
Date: Mon, 03 Apr 2000 17:29:40 -0400
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.
--------------F7B0B69DD176336B399AFC84
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit



elynum@my-deja.com wrote:

> In article <38e8e6e1.19193205@news.magma.ca>,
> myself@magma.ca (myself) wrote:
> > Hi
> > has Anyone used the
> > Xilinx student edition, version 1.5
> >
> > I am unclear on the software that comes with this book!
> > I want to write VHDL code for FPGA's.
> > I am not interested in schematic entry.
> >
> > Does this book cover VHDL?
> > Does this book include the "Foundation" series of software?
> > What series and version is it? (Does it support VHDL)?
> >
> > Any other books that come with vhdl software and practical examples?
> >
> > Martin Brown
> >
> > I have the version 1.3 of that book.  It is an excellent book.  I
> believe that version 1.5 does have a vhdl simulator in conjunction with
> schematic entry.  It should be in the back of your book in the CD's that
> come with the book.  The book covers mostly verilog but their are vhdl
> versions of the verilog code.  You must go online to this web page to

Just to correct this small point: the current edition of the book comes with Foundation 1.5 and covers design with Xilinx FPGAs using schematics, ABEL, and VHDL.  There is no coverage of Verilog in the book although the software supports Verilog in addition to VHDL, ABEL, and schematics (and mixed-mode designs).  Also, the CDROMs that come in the package include the source code for all the design examples.

>
> get the vhdl equivalent => www.xess.com just do a search on vhdl and you
> should come up with the vhdl version of the labs that you can download.
> Also, there is a forum that you can sign up for once you get to that web
> page that I have found very helpful.  You should also, consider buying
> their fpga hardware board so you can actually see your code at work or
> go the cheap route to build your own. I built my own version of their
> hardware.  Would I do it again, nope! Save yourself the time unless you
> want to learn how to wirewrap, solder and learn debug, and buy it.
>
> Sent via Deja.com http://www.deja.com/
> Before you buy.

--
|| Dr. Dave Van den Bout   XESS Corp.               (919) 387-0076 ||
|| devb@xess.com           2608 Sweetgum Dr.        (800) 549-9377 ||
|| http://www.xess.com     Apex, NC 27502 USA   FAX:(919) 387-1302 ||


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n:Vanden Bout;Dave
tel;fax:(919) 387-1302
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org:XESS Corp.
adr:;;2608 Sweetgum Drive;Apex;NC;27502;USA
version:2.1
email;internet:devb@xess.com
title:FPGA Product Manager
x-mozilla-cpt:;-16464
fn:Dave Vanden Bout
end:vcard

--------------F7B0B69DD176336B399AFC84--

Article: 21840
Subject: Re: Pipelined ALTERA LPMs - where are the registers introduced?
From: nestor@stansync.com (Nestor)
Date: Mon, 03 Apr 2000 21:33:55 GMT
Links: << >>  << T >>  << A >>
Thanks for your response.  It makes sense.

Nestor

On 31 Mar 2000 07:21:31 GMT, psycho333221@aol.com (Psycho333221)
wrote:

>The registers are placed so as to attempt to break the logic into equal sized
>chunks.  So for LPM_PIPELINE = 1, the registers should be right at the center. 
>If you think about it, this is the only way that makes sense if you really
>intend to increase speed.
>The ideal is that if it normally takes x for the signal to propagate, then with
>a pipeline of n the propogation delay should be x/n.  However, in most cases
>this ideal is not reached since it is difficult to break the function up
>perfectly and also the delays of different routing are different.

Article: 21841
Subject: FPGA controlling S-7600A TCP/IP ...
From: Laurent Gauch <laurent.gauch@aps-euro.com>
Date: Mon, 03 Apr 2000 19:06:25 -0400
Links: << >>  << T >>  << A >>
Hi,

I am searching a example of a VHDL State-Machine working like a MPU
implementation controlling the new S-7600A chip (TCP/IP Network Protocol
Stack LSI from Seiko).

Or if somebody know where I can find some flow diagrams about a MPU
implementation controlling the S-7600A chip, that will be a big help for
me.

Also, I need to know the gates number in a FPGA or CPLD of a minimal
State-Machine like this up with only the minimum of controls
possibilities. If somebody has a idea about this gates number ...

Thank you in advance for your help.
Have an happy week on this blue planet!
Laurent

~~~ laurent.gauch@aps-euro.com ~~~
Laurent Gauch
APS-Euro
www.aps-euro.com
info@aps-euro.com
~~~~~~~~~~~~~~~~~~~~~~~~~~~

Article: 21842
Subject: Re: Virtex bitstreams wanted for compression study
From: aeeaee.com.br <>
Date: Mon, 3 Apr 2000 17:23:35 -0700
Links: << >>  << T >>  << A >>
I have already developed a compression algorithm for Spartan and Virtex bit streams. It is very easy to uncompress using simple microcontroller and provides up to 60% of compression rate. Is Fujitsu interested on it? Please, take a look at www.aee.com.br/icomp.html.
Note that the numbers there are old and a new release of the algorithm is under final test phase, and it gets around 60% with an almost full (97% CLBs) FPGA.
Article: 21843
Subject: Re: Virtex Secondary Clock Nets
From: "Paul Gigliotti" <paul.gigliotti@xilinx.com>
Date: Mon, 3 Apr 2000 18:42:57 -0700
Links: << >>  << T >>  << A >>
I am not an expert but it is my understanding that there are 24 backbones in the part for high fanout/local clocking.  Currently you need to put max skew time specs, and possibly floor plan to keep the logic within a small number of columns 4-5, to control skew and force the software to use these resources.

Next software release will have a use low skew resource contraint to help make this easier...

Article: 21844
Subject: Re: FPGA openness
From: krw@attglobal.net (Keith R. Williams)
Date: 4 Apr 2000 02:10:33 GMT
Links: << >>  << T >>  << A >>
On Mon, 3 Apr 2000 01:02:18, Zoltan Kocsi <root@127.0.0.1> wrote:

> krw@attglobal.net (Keith R. Williams) writes:
> 
> > > Can you do that ? I mean copyright an arbitrary sequence of bits,
> > > with all the DMCA protection, 70 years after author's death and all ?
> > > What is the minimum length ? 
> > 
> > Sure.  The fact that you've created "art" means it's copyrighted.
> >  You can *register* a copyright and in fact you must if you wish 
> > to sue.
> 
> I think you misunderstood me. I was not talking about the FPGA 
> design or a microprocessor program. 
> 
> I was talking about the bitstream as such, that is, can I register
> an arbitrary sequence of 1s and 0s (of which of course I am the 
> author), expressed in any bi-valued way as my intellectual property ? 

I'm not an IP lawyer, but I believe you can. Intel has done much 
the same for microcode (as has everyone else under the sun).  
This is the least of your problems though.  Any yahoo that's 
going to steal IP isn't going to have a pocket to go after. The 
problem, at least as I see it, is not theft by other legit 
companies, but total frauds.  The system doesn't deal with this 
side well at all.

> It would raise a few issues, I think:
> 
> - how long is the shortest copyrightable bitstream ?

..enough to prove that it's yours.  I'm not kidding.  There have
been cases where flaws were intentionally put into microcode just
to trace duplicates in other's products.  Consider this tactic.

> - how do you search for violations ? This involves the issue 
>   of reverse-engineering and trying to access material that
>   is access controlled. Say, you suspect that a DVD movie 
>   contains your bitstream, but you can't decode the DVD to
>   check it because it would be criminal activity, according 
>   to the MPAA. Evidence obtained in illegal means is not 
>   admissible in court.

If it's perfectly copied, it's impossible to tell the real from 
the fake.  The Secret Service has many specialists workign on 
this very thing.  The point is to make it difficult for the perp,
but easy on the legitimate customer.  If the customer has a gripe
you've lost them!  I *hate* dongles, but tollerate them because I
understand the value of the software.

Note that perfect copies will also copy flaws.  If they re-label 
parts and market against you this is a usefull strategy.  Sheesh,
even Intel and AMD have problems with crap parts entering the 
market.  You're not going to stop it if the money is too high.  
You're not likely to catch the perps either.

> - how long of a sequence of bits that maches a portion of 
>   your copyrighted stream is considered fair use ?

No such animal.  Fair use never includes evasion of copyright.

> - how many changed bits are needed to the resulting bitstream
>   to be considered as based on the original ?

Your judge will determine this.  Seriously, there is little you 
can do if your perp has nothing to lose.  In this light, the game
market doesn't seem ripe for FPGAs.  An ASIC would likely be a 
better solution.  Yes, I can easily see possibilities for FPGA 
companies to "harden" the designs. It would take a OTP 
programmable widget of some sort, but it's possible.  The 
question is: "do enough customers care enough to make everyone 
pay?"  For some products, maybe.  I don't see it at the high end.
..Maybe with the dirt-cheap stuff, but these tend to be 
yesterday's high-end.

> - if there's a bitstream which by applying an algorithm (e.g.
>   drop every second bit from it) can be transformed to the original
>   stream, is it a violation ? How complex the algorithm can be to 
>   claim violation, knowing that a complex enough algorithm can 
>   transform any bitstream to any other bitstream ?

Given that you're programming a known device which is available 
to all, any munging would be the same.  The bottom line is that 
you would have to prove a common IP.  With an equivalent 
bitstream this shouldn't be hard.  It's not like you can just 
move things around without knowing the bitstream. In fact, you've
just given me another reason to believe X has it right by not 
releasing the bitstream. While it keeps nothing secret, it does 
raise the bar at copying and munging the design to obscure theft.
I hadn't considered X's "security through obscurity" wacky stance
until I thought about this for a while.  

----
  Keith

Article: 21845
Subject: Re: Virtex bitstreams wanted for compression study
From: allan.herriman.hates.spam@fujitsu.com.au (Allan Herriman)
Date: Tue, 04 Apr 2000 02:27:49 GMT
Links: << >>  << T >>  << A >>
On Mon, 3 Apr 2000 17:23:35 -0700, aeeaee.com.br <> wrote:

>I have already developed a compression algorithm for Spartan and Virtex bit streams. It is very easy to uncompress using simple microcontroller and provides up to 60% of compression rate. Is Fujitsu interested on it? Please, take a look at www.aee.com.br/icomp.html.
>Note that the numbers there are old and a new release of the algorithm is under final test phase, and it gets around 60% with an almost full (97% CLBs) FPGA.

I'm only interested in open compression algorithms.

Thanks,
Allan.

Article: 21846
Subject: Library of Parameterized Modules
From: "Liviu" <chiaburu@sympatico.ca>
Date: 3 Apr 2000 19:27:25 -0800
Links: << >>  << T >>  << A >>

I'm trying to run a behavioral VHDL simulation with ModelSim PE 5.3 and I couldn't find any way to use LPM. Has anyone used components in LPM with ModelSim ?  
Article: 21847
Subject: Re: Xilinx student edition, version 1.5
From: elynum@my-deja.com
Date: Tue, 04 Apr 2000 04:34:50 GMT
Links: << >>  << T >>  << A >>
In article <38E90D44.69E9C825@xess.com>,
Dave Vanden Bout <devb@xess.com> wrote:
> This is a multi-part message in MIME format.
> --------------F7B0B69DD176336B399AFC84
> Content-Type: text/plain; charset=us-ascii
> Content-Transfer-Encoding: 7bit
>
> elynum@my-deja.com wrote:
>
> > In article <38e8e6e1.19193205@news.magma.ca>,
> > myself@magma.ca (myself) wrote:
> > > Hi
> > > has Anyone used the
> > > Xilinx student edition, version 1.5
> > >
Sorry, Dave you are correct!
> > > I am unclear on the software that comes with this book!
> > > I want to write VHDL code for FPGA's.
> > > I am not interested in schematic entry.
> > >
> > > Does this book cover VHDL?
> > > Does this book include the "Foundation" series of software?
> > > What series and version is it? (Does it support VHDL)?
> > >
> > > Any other books that come with vhdl software and practical
examples?
> > >
> > > Martin Brown
> > >
> > > I have the version 1.3 of that book. It is an excellent book. I
> > believe that version 1.5 does have a vhdl simulator in conjunction
with
> > schematic entry. It should be in the back of your book in the CD's
that
> > come with the book. The book covers mostly verilog but their are
vhdl
> > versions of the verilog code. You must go online to this web page to
>
> Just to correct this small point: the current edition of the book
comes with Foundation 1.5 and covers design with Xilinx FPGAs using
schematics, ABEL, and VHDL. There is no coverage of Verilog in the book
although the software supports Verilog in addition to VHDL, ABEL, and
schematics (and mixed-mode designs). Also, the CDROMs that come in the
package include the source code for all the design examples.
>
> >
> > get the vhdl equivalent => www.xess.com just do a search on vhdl
and you
> > should come up with the vhdl version of the labs that you can
download.
> > Also, there is a forum that you can sign up for once you get to
that web
> > page that I have found very helpful. You should also, consider
buying
> > their fpga hardware board so you can actually see your code at work
or
> > go the cheap route to build your own. I built my own version of
their
> > hardware. Would I do it again, nope! Save yourself the time unless
you
> > want to learn how to wirewrap, solder and learn debug, and buy it.
> >
> > Sent via Deja.com http://www.deja.com/
> > Before you buy.
>
> --
> || Dr. Dave Van den Bout XESS Corp. (919) 387-0076 ||
> || devb@xess.com 2608 Sweetgum Dr. (800) 549-9377 ||
> || http://www.xess.com Apex, NC 27502 USA FAX:(919) 387-1302 ||
>
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> org:XESS Corp.
> adr:;;2608 Sweetgum Drive;Apex;NC;27502;USA
> version:2.1
> email;internet:devb@xess.com
> title:FPGA Product Manager
> x-mozilla-cpt:;-16464
> fn:Dave Vanden Bout
> end:vcard
>
> --------------F7B0B69DD176336B399AFC84--
>
>


Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 21848
Subject: Re: Adrian Thompson's and GA work on Xilinx
From: "Craig Slorach" <craigs@elec.gla.ac.uk>
Date: Tue, 4 Apr 2000 09:31:27 +0100
Links: << >>  << T >>  << A >>
There 's a paper coming up in ICES2000 (EHW conf) in Edinburgh which gives
basic results and analysis. I give details of targetting the Xilinx 4000 and
the Altera Max series. To avoid long messages, please mail me for further
details (craigs@elec.gla.ac.uk).

"Graham Seaman" <seamang@westminster.ac.uk> wrote
> : One option is to host a 6200 like architecture on an existing FPGA by
> : creating a 'virtual structure' on an existing FPGA.
> What FPGA have you done it for? Are the details available anywhere?



Article: 21849
Subject: Re: FPGA controlling S-7600A TCP/IP ...
From: "Gary Watson" <gary@nexsan.sex>
Date: Tue, 4 Apr 2000 10:30:16 +0100
Links: << >>  << T >>  << A >>
Laurent Gauch <laurent.gauch@aps-euro.com> wrote in message
news:38E923F1.FA4BBC50@aps-euro.com...
> Hi,
>
> I am searching a example of a VHDL State-Machine working like a MPU
> implementation controlling the new S-7600A chip (TCP/IP Network Protocol
> Stack LSI from Seiko).
>
> Or if somebody know where I can find some flow diagrams about a MPU
> implementation controlling the S-7600A chip, that will be a big help for
> me.

Wouldn't it depend upon what you plan to do with the chip?  The chip looks
really cool for IP over RS-232 applications, I must admit.  I just wish they
did an Ethernet version.


--

Gary Watson
gary@nexsan.sex  (Change dot sex to dot com to reply!!!)
Nexsan Technologies Ltd.
Derby DE21 7BF  ENGLAND
http://www.nexsan.com







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