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Messages from 21950

Article: 21950
Subject: CLKDLL stabilty state
From: karenwlead@my-deja.com
Date: Sat, 08 Apr 2000 12:21:58 GMT
Links: << >>  << T >>  << A >>
Hi All,

After how many cycles the virtex clkdll reaches the stability state

:)


Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 21951
Subject: Digital Design/Systems/CAD Engineer looking for position in California
From: Andreas Schmidt <as@asic.cc>
Date: Sat, 08 Apr 2000 16:48:42 +0200
Links: << >>  << T >>  << A >>
<!doctype html public "-//w3c//dtd html 4.0 transitional//en">
<html>
Dear recruiting team,
<p>- you are looking for a highly-motivated digital
<br>&nbsp; design/systems/CAD engineer?
<br>- you need an engineer who is fascinated of computer
<br>&nbsp; technology, especially parallel/vector architectures,
<br>&nbsp; System-On-a-Chip and high-speed datacommunications?
<br>- you ask for an employee who's motivation to study
<br>&nbsp; electrical engineering was generated by Seymour Cray
<br>&nbsp; and his machines?
<br>- you are searching for a creative mind combined with
<br>&nbsp; strong problem solving capabilities?
<br>- you want a new member for your team, who is committed
<br>&nbsp; to excellence and success?
<br>- you desire an open-minded person who is programmed to
<br>&nbsp; reach the goal, increasing your efficiency and
<br>&nbsp; pushing the limits?
<br>Try this.....
<p>=> <A HREF="http://www.asic.cc">http://www.asic.cc</A>
<p>Best regards,
<p>Andreas Schmidt
<p>P.S.: Everything is possible, if you really want it...
<br>&nbsp;
<br>&nbsp;</html>

Article: 21952
Subject: top50 keywords january - february - march...
From: The IRS <aralf@usa.netnospam>
Date: Sat, 08 Apr 2000 19:05:38 +0300
Links: << >>  << T >>  << A >>

-- 

http://top50keywords.tripod.com/

Article: 21953
Subject: JTAG PROBLEM
From: "adams" <leezmina@sina.com>
Date: Sun, 9 Apr 2000 17:29:52 +0800
Links: << >>  << T >>  << A >>
Hi,
I have seen Altera Max7192, downloaded via JTAG by byteblaster cable. But
Xilinx XCS10 have CCLK,MODE,Din,Dout other than TCK,TMS,TDI,TDO, can I
download it via JTAG port, or it can only be configured via Din,etc.

Thanks in advance.

Adams


Article: 21954
Subject: Re: multiprocessor support of IC design tools
From: Utku Ozcan <ozcan@netas.com.tr>
Date: Sun, 09 Apr 2000 15:10:18 +0300
Links: << >>  << T >>  << A >>
My point is, in UNIX, multipass place and route option shares
each PAR process to a processor. If one workstation has only
one processor then it means one PAR process is assigned to
one workstation.

Since the PAR time is the most critical during design,
my question is if one PAR process can be shared among
more than one processor, in the same workstation or
in more then one workstation. I think this is impossible
in current tools. If you have more than one processor
in a workstation, then you have to define one user account
or session for each processor on the workstation, which
is the same as having the number of workstation in which
one processor has been plugged. The number of the workstations
here is the number of the processors in the same workstation.

That means two workstations with one processor each is
exactly the same as one workstation with two processors,
but as Ray stated, one workstation with multiple processors
will be slower because of peripherals (RAM, harddisk access
etc).

Utku

-- 
I feel better than James Brown.
Article: 21955
Subject: Re: multiprocessor support of IC design tools
From: Ray Andraka <randraka@ids.net>
Date: Sun, 09 Apr 2000 15:11:02 GMT
Links: << >>  << T >>  << A >>
That said, I have successfully run two separate PAR sessions on my dual
processor machine concurrently.  Granted, that doesn't accelerate the
PAR for one, but where you might want to run PAR with more than one seed
or have more than one FPGA in a design it can be helpful.  If you run
two copies of PAR on one design, I think you'll need to copy that design
to a second directory to keep them from interfering.


>

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 21956
Subject: Re: Shuttle Backup Computers and "Diverse Design"
From: Greg Neff <gregneff@my-deja.com>
Date: Sun, 09 Apr 2000 15:25:24 GMT
Links: << >>  << T >>  << A >>
In article <8cffgn$bi6$1@sulawesi-fi.lerc.nasa.gov>,
  "Geoffrey A. Landis" <geoffrey.landis@sff.net> wrote:
> In article <38E3CE53.371D@pointecom.net> Lynn Killingbeck,
> killbeck@pointecom.net writes:
> }...
> }It isn't that diverse a system (reading a lot into you undefined
term).

True, the term "diversity" has not been defined in this thread.  I
originally introduced this term into a discussion thread in
comp.arch.fpga, where the posted question was not related to the space
shuttle.

> }.... The
> }backup _software_ uses the same hardware, same specifications, same
I/O
> }system, same displays and controls, same compiler, same language(s),
and
> }same just-about-everything.
>
> Really?  One of the first jobs I was offered out of college was one to
> work on the software for the backup computer.  The team leader who
> interviewed me explained that one of the ground rules was that it was
> completely independently-written code, running on a different platform
> built by a different manufacturer.  Did this original plan get
dropped?

Maybe in some systems, like the space shuttle.  But true diversity uses
both different hardware and different software.  For example, I know of
one system requiring distributed control where both LonWorks and
DeviceNet were used, in order to provide as much diversity as possible.

>
> (that was about five years before the actual first shuttle launch, and
> everything about the computer system could very well have changed.)
>
> --
> Geoffrey A. Landis
> http://www.sff.net/people/geoffrey.landis
>

--
Greg Neff
VP Engineering
*Microsym* Computers Inc.
greg@guesswhichwordgoeshere.com


Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 21957
Subject: Virtex Trivia
From: "Kevin T. Mortimer" <mortik@rpi.edu>
Date: Mon, 10 Apr 2000 02:39:21 -0400
Links: << >>  << T >>  << A >>

I need to know the physical size of a CLB and IOB for the .22um Xilinx
Virtex CMOS process.

Thanks in advance for your help...

-Kevin Mortimer      




         

Article: 21958
Subject: FPL 2000 -- Call for Exhibitors
From: Reiner Hartenstein <hartenst@rhrk.uni-kl.de>
Date: Mon, 10 Apr 2000 09:25:52 +0200
Links: << >>  << T >>  << A >>

--------------C682648B0DE78FBE50859F2B
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Call for Exhibitors   --   Call for Participants

            FPL 2000

     The 10th International Conference on
   Field Programmable Logic and Applications

           28 - 30 August 2000
         Villach, Carinthia, Austria
      (in the cheart of "silicon alps")

High Growth Rate Conference:
    50 % more submissions  (from 1999 to 2000)
    44% more participants (from '98 to '99)
    Also featuring keynotes and survey papers.
    Advance Program ready by end of May

      The eldest international conference
      on reconfigurable logic and systems
      (2 years elder than FPGA and FCCM),
      founded by Oxford University (UK)

we welcome the submission of proposals like:

          exhibit proposals
          product demonstrations
          industrial papers and tutorials
          book exhibits
          others (please, propose!)

Exhibitor Registration Deadline: July 28, 2000

Download Registration Form:
PDF: http://xputers.informatik.uni-kl.de/FPL/fpl2000/
Postscript:
http://xputers.informatik.uni-kl.de/FPL/fpl2000/CfP_FPL2000.ps


for details on FPL 2000 see:
http://xputers.informatik.uni-kl.de/FPL/FPL2000/detailed_fpl.html

Regards,

Reiner W. Hartenstein
Program Chair FPL 2000
http://xputers.informatik.uni-kl.de/FPL/fpl2000/

--------------C682648B0DE78FBE50859F2B
Content-Type: text/html; charset=us-ascii
Content-Transfer-Encoding: 7bit

<!doctype html public "-//w3c//dtd html 4.0 transitional//en">
<html>
<tt></tt>&nbsp;<tt></tt>
<p><tt>Call for Exhibitors&nbsp;&nbsp; --&nbsp;&nbsp; Call for Participants</tt><tt></tt>
<p><tt>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
<b><font size=+4>FPL 2000</font></b></tt><tt></tt>
<p><tt>&nbsp;&nbsp;&nbsp;&nbsp; The 10th International Conference on</tt>
<br><tt>&nbsp;&nbsp; Field Programmable Logic and Applications</tt><tt></tt>
<p><tt>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 28
- 30 August 2000</tt>
<br><tt>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Villach, Carinthia,
Austria</tt>
<br><tt>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (in the cheart of "silicon alps")</tt><tt></tt>
<p><tt>High Growth Rate Conference:</tt>
<br><tt>&nbsp;&nbsp;&nbsp; 50 % more submissions&nbsp; (from 1999 to 2000)</tt>
<br><tt>&nbsp;&nbsp;&nbsp; 44% more participants (from '98 to '99)</tt>
<br><tt>&nbsp;&nbsp;&nbsp; Also featuring <b>keynotes</b> and <b>survey
papers.</b></tt>
<br><tt><b>&nbsp;&nbsp;&nbsp;</b><i> Advance Program ready by end of May</i></tt><i><tt></tt></i>
<p><i><tt>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; The eldest international conference</tt></i>
<br><i><tt>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; on reconfigurable logic and systems</tt></i>
<br><i><tt>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (2 years elder than FPGA and
FCCM),</tt></i>
<br><i><tt>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; founded by Oxford University
(UK)</tt></i><tt></tt>
<p><tt>we welcome the submission of proposals like:</tt><tt></tt>
<p><tt>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; exhibit proposals</tt>
<br><tt>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; product
demonstrations</tt>
<br><tt>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; industrial
papers and tutorials</tt>
<br><tt>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; book exhibits</tt>
<br><tt>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; others (please,
propose!)</tt><tt></tt>
<p><b><tt>Exhibitor Registration Deadline: July 28, 2000</tt></b><tt></tt>
<p><tt>Download Registration Form:</tt>
<br><tt>PDF: <A HREF="http://xputers.informatik.uni-kl.de/FPL/fpl2000/">http://xputers.informatik.uni-kl.de/FPL/fpl2000/</A></tt>
<br><tt>Postscript:</tt>
<br><tt><A HREF="http://xputers.informatik.uni-kl.de/FPL/fpl2000/CfP_FPL2000.ps">http://xputers.informatik.uni-kl.de/FPL/fpl2000/CfP_FPL2000.ps</A></tt>
<br><tt></tt>&nbsp;<tt></tt>
<p><tt>for details on FPL 2000 see:&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
<A HREF="http://xputers.informatik.uni-kl.de/FPL/FPL2000/detailed_fpl.html">http://xputers.informatik.uni-kl.de/FPL/FPL2000/detailed_fpl.html</A></tt><tt></tt>
<p><tt>Regards,</tt><tt></tt>
<p><tt>Reiner W. Hartenstein</tt>
<br><tt>Program Chair FPL 2000</tt>
<br><tt><A HREF="http://xputers.informatik.uni-kl.de/FPL/fpl2000/">http://xputers.informatik.uni-kl.de/FPL/fpl2000/</A></tt></html>

--------------C682648B0DE78FBE50859F2B--

Article: 21959
Subject: Re: multiprocessor support of IC design tools
From: "Jean-Paul GOGLIO" <goglio@getris.com>
Date: Mon, 10 Apr 2000 10:03:53 +0200
Links: << >>  << T >>  << A >>

Ray Andraka wrote in <38EE3920.E5EBBEAA@ids.net>...
>If you go to a dos pox and run par without arguments you get the help
screen.
>From there I quote:
>"-m = Multi task par run.  File <node list file> ",
>    contains a list of node names on which to run the jobs.
>    (This option is not currently supported on WIN NT/WIN 95
>    systems)."
>
>Also, I have not seen any evidence that Aldec 3.6c supports multiple
processors
>either (if you know different, then please educate me on how to set it up
to do
>so).  I know that synplicity and modelsim also run just one processor.
Note: If
>you have a two processor system, the tasks will be spread out to the two
>processors, but the combined processor load while running just synplicity
or
>xilinx (or substitute other EDA package) under NT only totals 50%,
indicating
>that teh programs are single threaded.  The advantage two processors gets
you is
>that you can run two things at once even if they are both processor
intensive
>(where it slows down is on disk access).
>


For Aldec, there are 2 different versions : The base version and the FPGA
Booster version. The second one increases the simulation speed for
post-implemented netlists.
Few months a go, i tried the 10 days evaluation version of the FPGA Booster
on a design with 3 FPGA post-implemented netlists and i saw the CPU reaching
100%. The simulation was at least 10 times faster than with the base
version.
So, i suppose that in this case, the simulation is multi threaded, but i'm
not sure of that, because as the Booster option is $10,000 more expensive
than the base option and as i only make few post-implemented simulations, i
didn't buy this option, and so, i can't retry.


That's why i was asking if someone could confirm this point.

Note that with the base version, the CPU never totals more than 50%.


 --
 J-P GOGLIO
 GETRIS S.A.
 13 Chemin des Prés
 38240 Meylan
 Tel : (+33) 4 76 18 52 10
 E-mail : goglio@getris.com
 Fax : (+33) 4 76 18 52 01



Article: 21960
Subject: Re: multiprocessor support of IC design tools
From: Jonas Rangell <jonas.rangell@emw.ericsson.se>
Date: Mon, 10 Apr 2000 12:30:49 +0200
Links: << >>  << T >>  << A >>
Bret Wade wrote:
> 
> Hello Jonus,
> 
> The "-m node_list" option of PAR is related to the Multi-Pass Place & Route
> feature which farms out multiple PAR runs to the various machines in your
> node list file, to be run concurrently.  Each pass gets a different
> placement seed. If your PAR command uses the -m switch but does not specify
> multiple passes using the "-n #" switch, then you will see the message
> "Multi-task PAR is not needed for this job", because you have only
> specified a single pass. This has nothing to do with using multiple
> processors on a single machine, and as others have said, it's only
> supported on Solaris and HP-UX machines.
> 
> Regards,
> Bret Wade
> Xilinx Product Applications

OK, I have to try again.
I did not set any value to the -n parameter. 
Have to look in the manuals for this flag.

And, yes machine was a SUN running SunOS 5.5.1



Kind regards
/Jonas
Article: 21961
Subject: Java to HDL compiler, Free Beta
From: Ian Miller <miller@lists.lavalogic.com>
Date: Mon, 10 Apr 2000 12:30:36 GMT
Links: << >>  << T >>  << A >>
Hello, 

LavaLogic (http://www.lavalogic.com) is seeking experienced chip
designers to download a FREE beta copy of our Java to Verilog compiler.  
The "Forge" allows chip designers to write high level algorithmic
descriptions of their chip directly in pure Java, then translate that
description to synthesizable Verilog.

We are finding, through our early access program, that designers are
able to capture the functionality of their chip more rapidly in Java
than in Verilog, and the synthesis results of "Forge" produced Verilog
are on-par with hand coded designs.  Designs accomplished through use of
the "Forge" have included complex algorithms such as a Floating Point
Unit to more interface oriented designs like a DS3 serialization
interface.

The "Forge" is written in Java and will run on any platform running a
Java2 virtual machine (available for free from Sun Microsystems).
Automated install is supported for Solaris 2.6 and Linux (x86), however
installation instructions are available for any platform.

The current beta version of the "Forge" is available for FREE download
right now.  Simply let us know who you are at:
http://www.lavalogic.com/join.html  
Then once you have had a chance to use the tool, let us know what you
think (if you are so inclined!)

Sincerely,
Ian Miller
Article: 21962
Subject: Re: multiprocessor support of IC design tools
From: Ray Andraka <randraka@ids.net>
Date: Mon, 10 Apr 2000 14:17:06 GMT
Links: << >>  << T >>  << A >>
I have the Aldec FPGA booster version.  It accelerates simulation of the FPGA
netlist, apparently by replacing the primitives with streamlined code.  It is a
very nice feature for doing back-annotated simulations for functional or timing
simulation of the mapped or placed and routed FPGA design.  It won't do anything
for you before the FPGA is mapped.  AFAIK, that does not take advantage of
multiple processors.

Jean-Paul GOGLIO wrote:

> Ray Andraka wrote in <38EE3920.E5EBBEAA@ids.net>...
> >If you go to a dos pox and run par without arguments you get the help
> screen.
> >From there I quote:
> >"-m = Multi task par run.  File <node list file> ",
> >    contains a list of node names on which to run the jobs.
> >    (This option is not currently supported on WIN NT/WIN 95
> >    systems)."
> >
> >Also, I have not seen any evidence that Aldec 3.6c supports multiple
> processors
> >either (if you know different, then please educate me on how to set it up
> to do
> >so).  I know that synplicity and modelsim also run just one processor.
> Note: If
> >you have a two processor system, the tasks will be spread out to the two
> >processors, but the combined processor load while running just synplicity
> or
> >xilinx (or substitute other EDA package) under NT only totals 50%,
> indicating
> >that teh programs are single threaded.  The advantage two processors gets
> you is
> >that you can run two things at once even if they are both processor
> intensive
> >(where it slows down is on disk access).
> >
>
> For Aldec, there are 2 different versions : The base version and the FPGA
> Booster version. The second one increases the simulation speed for
> post-implemented netlists.
> Few months a go, i tried the 10 days evaluation version of the FPGA Booster
> on a design with 3 FPGA post-implemented netlists and i saw the CPU reaching
> 100%. The simulation was at least 10 times faster than with the base
> version.
> So, i suppose that in this case, the simulation is multi threaded, but i'm
> not sure of that, because as the Booster option is $10,000 more expensive
> than the base option and as i only make few post-implemented simulations, i
> didn't buy this option, and so, i can't retry.
>
> That's why i was asking if someone could confirm this point.
>
> Note that with the base version, the CPU never totals more than 50%.
>
>  --
>  J-P GOGLIO
>  GETRIS S.A.
>  13 Chemin des Prés
>  38240 Meylan
>  Tel : (+33) 4 76 18 52 10
>  E-mail : goglio@getris.com
>  Fax : (+33) 4 76 18 52 01

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 21963
Subject: Distributed Arithmetic
From: Jamil Khatib <jamilkhatib75@yahoo.com>
Date: Mon, 10 Apr 2000 16:35:09 +0200
Links: << >>  << T >>  << A >>
Is there anyone know anything about distributed arithmetic and its uses
in the DSP implementation on FPGAs?

Thanks

Article: 21964
Subject: Re: multiprocessor support of IC design tools
From: husby@fnal.gov (Don Husby)
Date: Mon, 10 Apr 2000 14:36:50 GMT
Links: << >>  << T >>  << A >>
Ray Andraka <randraka@ids.net> wrote:
> That said, I have successfully run two separate PAR sessions on my dual
> processor machine concurrently.  Granted, that doesn't accelerate the
> PAR for one, but where you might want to run PAR with more than one seed
> or have more than one FPGA in a design it can be helpful.  If you run
> two copies of PAR on one design, I think you'll need to copy that design
> to a second directory to keep them from interfering.

I do this with the Lucent (Neocad) software running 16 instances of
PAR on a "farm" of 8 dual-cpu NT boxes.  They can all run from the same directory
as long as the command line specifies a different output directory.  This is really
useful on a tight design, where each of the 100 "cost tables" takes 3 hours to run.
I can run all 100 cost tables over night, and try multiple hand-placements during
the day.
  I see no degradation due to disk thrashing, since this is a CPU-bound task.

It also helps that Lucent gives away their software for free (for all but the
biggest chips.)



--
Don Husby <husby@fnal.gov>             http://www-ese.fnal.gov/people/husby
Fermi National Accelerator Lab                          Phone: 630-840-3668
Batavia, IL 60510                                         Fax: 630-840-5406
Article: 21965
Subject: Re: Virtex Trivia
From: Peter Alfke <peter@xilinx.com>
Date: Mon, 10 Apr 2000 09:37:23 -0700
Links: << >>  << T >>  << A >>
Just use the search engine  <google.com>, type in <distributed
arithmetic>, and you get many hits.
The best beginning may be Ray Andraka"s web page, followed by various
Xilinx papers.
Neat stuff. Have fun!

Peter Alfke
====================
"Kevin T. Mortimer" wrote:

> I need to know the physical size of a CLB and IOB for the .22um Xilinx
> Virtex CMOS process.
>
> Thanks in advance for your help...
>
> -Kevin Mortimer
>
>

Article: 21966
Subject: Re: Distributed Arithmetic
From: Peter Alfke <peter@xilinx.com>
Date: Mon, 10 Apr 2000 09:40:49 -0700
Links: << >>  << T >>  << A >>
Just use the search engine  <google.com>, type in <distributed
arithmetic>, and you get many hits.
The best beginning may be Ray Andraka"s web page, followed by various
Xilinx papers.
Neat stuff. Have fun!

Peter Alfke
====================
Jamil Khatib wrote:

> Is there anyone know anything about distributed arithmetic and its uses
> in the DSP implementation on FPGAs?
>
> Thanks

Article: 21967
Subject: Re: Virtex Trivia
From: Peter Alfke <peter@xilinx.com>
Date: Mon, 10 Apr 2000 09:56:54 -0700
Links: << >>  << T >>  << A >>
Sorry, that was an answer to a different posting.
I had answered Kevin already privately.
Peter
==================
Peter Alfke wrote:

> Just use the search engine  <google.com>, type in <distributed
> arithmetic>, and you get many hits.
> The best beginning may be Ray Andraka"s web page, followed by various
> Xilinx papers.
> Neat stuff. Have fun!
>
> Peter Alfke
> ====================
> "Kevin T. Mortimer" wrote:
>
> > I need to know the physical size of a CLB and IOB for the .22um Xilinx
> > Virtex CMOS process.
> >
> > Thanks in advance for your help...
> >
> > -Kevin Mortimer
> >
> >

Article: 21968
Subject: setup and hold time violation
From: redbens@my-deja.com
Date: Mon, 10 Apr 2000 17:01:41 GMT
Links: << >>  << T >>  << A >>
Hello,

I have a little design (a Logiblox updown counter plus a vhdl based
macro to give the updown signal to the counter).
The functional simulation works fine but when I use the timing
simulation I have a setup and hold time violation with a clock
frequency of 30 MHz. When I use a clock of 20Mhz the design works fine!

I know from the data book that the fpga I am targeting (XC4000E) can be
clocked up to 80MHz. So what is the problem here and what can I do to
resolve it.

Thank you in advance for your answer.

Red.


Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 21969
Subject: Xilinx Foundation 2.1 error
From: Steven Sanders <sanders@imec.be>
Date: Mon, 10 Apr 2000 19:13:05 +0200
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.
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Hello,

When I try to implement a simple design (completely HDL), I get
following error message:
"logical blok xxxx is unexpanded". I already checked support.xilinx.com
for an answer but no solution there. Any advice?

Thanx!!!

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 name="sanders.vcf"
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Content-Disposition: attachment;
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begin:vcard 
n:Sanders;Steven 
x-mozilla-html:FALSE
org:imec ;DTS
adr:;;Flanders Language Valley 44;Ieper;;8900;Belgium
version:2.1
email;internet:sanders@imec.be
fn:Steven Sanders
end:vcard

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Article: 21970
Subject: Re: JTAG programming
From: "Alain Cloet" <alain_cloet@hotmail.com>
Date: Mon, 10 Apr 2000 20:38:46 +0200
Links: << >>  << T >>  << A >>
Sorry for the late reply, but here is something I had a while ago with
Foundation 1.5, which was an actual SW-problem (shouldn't be in later
versions AFAIK) ; maybe someone can get some help from it
(part from a reply to Neil Jacobson at Xilinx who got me on the right track)

>>>
<snip>
A little more info on the old question, your answer, and how it got me where
I had to be
<snip>

The problem I had, was that I weren't able to program a Xilinx XC95216-CPLD
with the parallel-JTAG-cable from Xilinx, and JTAG-programmer M.1.5.25, once
the chain was bigger than 1 element, and I needed to program the CPLD as the
1st element in a chain of 8 elements (the chain consisted of the
XC95216-CPLD, one 68360-Quicc processor from Motorola, 5 DSP-processors from
TI, and a XC4028-FPGA).

You gave me the hint that I should use the XC4003E-bsdl files for the other
elements, but it didn't work for the complete chain.  Anyway, it was already
an improvement, as a 2 element-chain worked (CPLD+Quicc).  SO I needed to
know why the BSDL-file of the XC4003E had more than the one of the Quicc
that made that chain work, so maybe it would bring me to the solution for
the whole chain.

After a 'game of cut&paste' I brought the original quicc-bsdl in a state
that made the jtag-programmer happy, and the programming possible.  The
problem was that I had changed already that much that it wasn't clear what
brought the break-through.  In the second try I changed the thing I changed
the last in the first try as first, but that wasn't enough, but I knew I was
on the right track, and it didn't take me long to 'break the code'.
It seemed I only needed to change 2 things:
1. Change the instance-name from m68360 to XC4003E_PC84 (although the last
part of that name didn't matter)
2. Change the used standard from 1990 to 1994 (not really rewrite the file
to the new standard, just tell that the 1994-standard is used - line 'use
std_1049_1_1990' - are something close to that, I just haven't a bsdl file
around)

If a changed the standard bsdl-files from the FPGA and the DSP's with the
1st change (in both the 1994-standard was already in use) I got an other
error than before, but it wasn't ok yet.  Then I saw that the DSP's had
instruction-lenghts of 4 instead of 3 (like the quicc, xc4028 and xc4003e).
So I searched if there was a xilinx-bsdl-file around that had
instruction-lenghts of 4 as well, but it seemed that only the CPLD's had
more than 3, to be more specific 8.  I was afraid it wouldn't work with that
(double instruction lenght, and if would try with two bsdl-files for 4
elements, the problem that not enough bypass-registers were counted).  So,
remembering maths, I thought of trying with defining 4 dsp's as xc4003e, and
one as xc9536, giving me an instruction-length of 20 as well, and 5
bypass-cells too.  Mathematically OK, but not for the JTAG-programmer.
However the error changed on the placement of the ''xc9536-dsp''.
Last try : Define them all as xc9536.  Finally I got 'Checking
Integrity...OK', but now I had an other problem.  The DSP-elements were
questioned for their ID-code, which they happened to have, and the
programmer saw they weren't xilinx at all.
Leaving the ID-instruction out of the bsdl-file made it even worse, than the
ID-code was still checked, but than it came to complete chaos, as he wanted
to know the ID for one or another reason, but he didn't know how to ask it
in a nice way.

So I had the feeling I was close to victory - close, but no cigar - but I
didn't have a clue how to go further, just until I wanted to shutdown the
computer I thought of one more thing.  As the name XC4003E could be followed
by things other than '_PC84', e.g. '_PC85' it had to do something with first
part of the name.  So I searched for all files having the text 'XC4003E' in
them, hoping it made me any wiser.  One of the files brought me to the
solution, a definition-file.  It had all the supported names in them, and as
the last line there stood 'IDCODE USERCODE' for the CPLD's and 'NO_IDCODE
NO_USERCODE' for the FPGA's.  So I changed that line to 'NO_IDCODE USERCODE'
for the XC9536, and than, finally : I could program the CPLD...
(After that I changed the instance-name for the DSP's to XC9572, and changed
the definition file for that element, and restored the definition of the
XC9536, as we use the CPLD as well, and there the ID-code checking is maybe
better allowed)
I don't know the complete name of the file anymore, but if you want to, I
can look it up for you (it's in the data-directory, where also the
bsdl-files are located, and the name starts with 'isp' and I guess the
extention is '.def')
<<<
Hope this hlps someone,
Alain


Article: 21971
Subject: Re: Distributed Arithmetic
From: Thomas Loftus <tloftus@intrinsix.com>
Date: Mon, 10 Apr 2000 15:24:57 -0400
Links: << >>  << T >>  << A >>
See the March 2000 issue of Embedded Systems Programming for
a good article.

http://www.embedded.com/2000/0003/

Tom

Jamil Khatib wrote:
> 
> Is there anyone know anything about distributed arithmetic and its uses
> in the DSP implementation on FPGAs?
> 
> Thanks
Article: 21972
Subject: Re: Xilinx Foundation 2.1 error
From: Christian Mautner <at@utanet.cmautner>
Date: 10 Apr 2000 21:48:48 +0200
Links: << >>  << T >>  << A >>
Steven Sanders <sanders@imec.be> writes:
>
> When I try to implement a simple design (completely HDL), I get
> following error message:
> "logical blok xxxx is unexpanded". I already checked support.xilinx.com
> for an answer but no solution there. Any advice?
> 

We might be able to help you if you would post your code and the full 
error message. 

That "... is unexpanded" messages is usually due to library problems.

chm.

-- 
cmautner@  -  Christian Mautner
utanet.at  -  Vienna/Austria/Europe
Article: 21973
Subject: Re: setup and hold time violation
From: Christian Mautner <at@utanet.cmautner>
Date: 10 Apr 2000 21:51:52 +0200
Links: << >>  << T >>  << A >>

redbens@my-deja.com writes:

> I have a little design (a Logiblox updown counter plus a vhdl based
> macro to give the updown signal to the counter).
> The functional simulation works fine but when I use the timing
> simulation I have a setup and hold time violation with a clock
> frequency of 30 MHz. When I use a clock of 20Mhz the design works fine!
> 
> I know from the data book that the fpga I am targeting (XC4000E) can be
> clocked up to 80MHz. So what is the problem here and what can I do to
> resolve it.

You should not depend on simulation only. What does the static timing
analysis say? What timing constraints did you specify?

chm.

-- 
cmautner@  -  Christian Mautner
utanet.at  -  Vienna/Austria/Europe
Article: 21974
Subject: Re: Distributed Arithmetic
From: Ray Andraka <randraka@ids.net>
Date: Mon, 10 Apr 2000 20:26:29 GMT
Links: << >>  << T >>  << A >>
For starters, try my web page.  You'll find distributed arithmetic under
the DSP page.  Basically, it is a rearrangement of the bitwise
multiplications and adds to take advantage of the small tables in the FPGA.

Jamil Khatib wrote:

> Is there anyone know anything about distributed arithmetic and its uses
> in the DSP implementation on FPGAs?
>
> Thanks

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka




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