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Messages from 22025

Article: 22025
Subject: Re: Parallel to serial
From: allan.herriman.hates.spam@fujitsu.com.au (Allan Herriman)
Date: Thu, 13 Apr 2000 12:21:51 GMT
Links: << >>  << T >>  << A >>
On Thu, 13 Apr 2000 12:58:01 +0200, Jamil Khatib
<jamilkhatib75@yahoo.com> wrote:

>    Please is there any way to convert from parallel to serial without
>using a counter to control the shift register?

You can use a "sentinel" bit (perhaps a 1) that gets loaded into an
extra bit at the end of the shift register during the parallel load.
The serial input of the shift register is set to the opposite state
(0).  When the sentinel is shifted out (after the data bits) the shift
register will be all 0.  You can detect this (or more usefully, the
state before it), and trigger a new parallel load.

This is a common programming technique.

Allan.
Article: 22026
Subject: XCHECKER 3V adapter
From: rimomol@teleco.upv.es (Ricardo Matias Moreno Moll)
Date: 13 Apr 2000 17:54:44 GMT
Links: << >>  << T >>  << A >>
Hello,
I'm student from Spain and I must configure a FPGA 4085XLA from Xilinx with 
the XCHECKER. I read in the Xilinx web that a 3V adapter is needed to do it, 
because the XCHECKER works at 5V. What is it? Is there a schematic to do it? 
Does anyone help me?   
Thanks.
  
Article: 22027
Subject: Re: jtag/jtagprog and fpga-demo-board
From: Robert Binkley <robert.binkley@xilinx.com>
Date: Thu, 13 Apr 2000 13:21:23 -0700
Links: << >>  << T >>  << A >>

Spaces or long names in the path can also cause problems.

Robert

marko.udvanc@trilus-spe.si wrote:

> Hello!
>
> Command line? I presume DOS-Prompt.
> As I saw the .bsd file has a long file name not 8.3 format.
> The DOS prompt can't find file beyond 8.3 format.
>
> Try changing names or similar.
>
> Greetings
> Marko
>
> >>>>>>>>>>>>>>>>>> Original Message <<<<<<<<<<<<<<<<<<
>
> On 7.4.00, 10:00:32, Joerg RiTTer <ritter@informatik.uni-halle.de> wrote
> regarding jtag/jtagprog and fpga-demo-board:
>
> > Hi,
>
> > I've successfully downloaded designs to a fpga-demo-board with the
> > hardware-debugger-software and the xchecker-cable.
> > Now I was looking for a command line version.
> > I've realized, that the jtagprog command line tool could be a
> solution.
> > Downloading with jtag / jtagprog fails with the following error
> message
> > :
>
> > JTAG Programmer Started 2000/04/06 10:20:37
> >     Loading Boundary-Scan Description Language (BSDL) file
> > 'g:/Xilinx/xc4000e/data/xc4005e_pc84.bsd'.....completed
> > successfully.
> >     Checking boundary-scan chain integrity...ERROR:JTag -
> Boundary-scan
> > chain test failed at bit position '1' on instance 'addsub(Device1)'.
> >      Check that the cable, system and device JTAG TAP connections are
> > correct,
> >      that the target system power supply is set to the correct level,
> >       that the system grounds are connected and that the parts are
> > properly decoupled.
> >     ERROR:JTag - Boundary scan chain has been improperly specified.
> > Please check your configuration and re-enter the     boundary-scan
> chain
>
> > information.
> >     Boundary-scan chain validated unsuccessfully.
> >     ERROR:JTag - : The boundary-scan chain has not been declared
> > correctly.
> >      Verify the syntax and correctness of the device BSDL files,
> correct
>
> > the files,
> >      reset the cable and retry this command.
>
> > I was using the same xchecker cable, fpga-board and the exactly the
> same
>
> > switch/flying leads settings.
> > Any ideas ?
> > Is there a command line version of the hardware debugger ?
>
> > Thanks
> > Joerg

Article: 22028
Subject: Re: A Question on Verilog
From: "Gary Spivey" <spivey@ieee.org>
Date: 13 Apr 2000 17:58:02 -0500
Links: << >>  << T >>  << A >>

I didn't take a long look at your code or your waveform, but one problem
jumps out immediately in your code. You have three always blocks that have
interdependencies and blocking assignments within these blocks. The
execution order of the always blocks is not deterministic in verilog. Use
just one always block and put your three cases inside of the one always
block.  Verilog uses blocking vs. non-blocking assignments ( = vs. <=).
When inside a synchronous block, you should be using non-blocking
assignments (that way it looks like a flip-flop - data doesn't change
exactly on the clock edge, but after everything has settled - it is
generally a good idea to do your flip-flop assignments like this

always @ (posedge clk or posedge reset) begin
   if (reset) ....
   else  begin
      a <= #1 b;
   end
end


The intra-assignment delay will be ignored by synthesis, but will insure
that the assignment doesn't have any chance of "feeding through" (the
non-blocking operator does this as well, but sometimes you can run into
issues with interdependencies with multiple clocks).  Another advantage is
that you see the data change after the clock edge in your waveform. This
delay won't have any adverse effect on your RTL simulations and won't exist
in any gate-level simulations - so it has no negatives and has positives.
That seems like a good idea.

As for your waveform viewing, you are seeing the data at then end of the
time-unit, but you don't have the order information on when the transitions
occured.

For  instance, if DataIN and test and TargetWRCtrl are all changing (as in
your code), there is no determinism in the order they change (according to
the Verilog language - and believe me, different simulators do it
differently). So, It could be that your TargetWRCtrl get's changed first,
then DataIN, then test. However, it could also be that test get's set before
DataIN.

Now, if you were using non-blocking assignments (<=) - this would all
resolve itself as the assignements wouldn't actually be done until all of
the blocks in a given dependency list have been processed.

Here is one more way to look at it in Verilog.

always @ (posedge clock) begin
   a <= b;
   b <= a;
end

This case has a and b as two flip-flops whose inputs feed each other
(neigher a or b are changed until all events in the current time-unit event
queue are resolved.

always @ (posdege clock) begin
  a= b;
  b = a;
end

 This case has 2 flip-flops - with a being set to b and b feeding back on
itself (as the value of a has changed before the assignment of b).

always @ (posedge clock) begin
   a <= b;
always @( posedge clock) begin
  b <= a;


Same as case 1 - we don't know which will be evaluated first, but it doesn't
matter as the non-blocking assignments mean that we won't assign the values
until the event queue processing has completed

always @ (posedge clock) begin
   a = b;
always @( posedge clock) begin
  b = a;

Completely non-deterministic.
Don't know if a get's assigned first or if b does.


Check out a good Verilog book - like Palnitkar's Verilog HDL. As for the
event queue, there is a very good description in Thomas and Moorby's ' The
Verilog Hardware Description Language'

Cheers,
Gary Spivey


"Ben" <ejhong@future.co.kr> wrote in message
news:9mTI4.1567$jO2.37191@news2.bora.net...
> Hi,
>
> For a few weeks I've been coding synchronous system with Verilog.
> I thought I was doing quite well with Verilog just as I did with VHDL.
> But I bumped into an unexpected, confusing problem.
>
> You can see my problem at the code attached.
> In the code, I wanted to implement 'test1' and 'test2' as edge-triggered
DFF
> with 'Target_WrCtrl' as a load signal for both DFFs.
>
> The load signal 'Target_WrCtrl' is also an output from an edge-triggered
> DFF.
> The value of 'TargetWrite' is captured on the rising edge of 'clock', and
> gives out 'Target_WrCtrl'.
>
> The input for DFF 'test1' and 'test2' is another synchronous signal DataIn
> that is edge-triggered version of 'Data'.
>
> Now I expect the 'test1' and 'test2' to be set each with 'DataIn[1]' and
> 'DataIn[0]'
> on the rising edge of clock where 'Target_WrCtrl' is high;
> i.e. on the rising edge of clock right after the clock edge where
> 'TargetWrite' was
> captured as logic high
>
> But when I compiled the code and simulated with Vsystem,
> I could see 'test1' doesn't go high
> when both 'DataIn[1]' and 'Target_WrCtrl' are considered to be high.
> As for 'test2', it goes high but one clock earlier;
> i.e. when 'DataIn[0]' and 'TargetWrite' are high, but 'Target_WrCtrl' is
> low.
>
> This beats me.
> Sombody please help me.
> I also attach the wave view of the simulation.
>
> TIA
>
> Regards,
> Ben
>
>
>


Article: 22029
Subject: Re: Java to HDL compiler, Free Beta
From: Reiner Hartenstein <hartenst@rhrk.uni-kl.de>
Date: Fri, 14 Apr 2000 07:09:14 +0200
Links: << >>  << T >>  << A >>


Ian Miller wrote:

> Hello,
>
> LavaLogic (http://www.lavalogic.com) is seeking experienced chip
> designers to download a FREE beta copy of our Java to Verilog compiler.
> The "Forge" allows chip designers to write high level algorithmic
> descriptions of their chip directly in pure Java, then translate that
> description to synthesizable Verilog.

Seeking Experienced Designers: come to FPL 2000

as a participant or as an exhibitor.  --  see:
http://xputers.informatik.uni-kl.de/FPL/fpl2000/

Best,
Reiner

>
>
> ........
>
> Sincerely,
> Ian Miller

--

Reiner Hartenstein

Configware Lab
University of Kaiserslautern
http://configware.de


Article: 22030
Subject: Re: US - Engineering Opportunities in NH,MA,NJ,NY,CA
From: Reiner Hartenstein <hartenst@rhrk.uni-kl.de>
Date: Fri, 14 Apr 2000 07:32:05 +0200
Links: << >>  << T >>  << A >>


taetzsch@asic-alliance.com wrote:

> Career Opportunities at ASIC Alliance
>
> ASIC Alliance is recognized as a leading provider of ASIC, FPGA, SoC,
> and systems design and verification services and solutions. With a
> rapidly growing list of new customers and some of the industry's most
> challenging projects, we are expanding all areas of our company to
> support this growth.
>
> We have many interesting and challenging positions available in all
> ASIC Alliance locations including Portsmouth New Hampshire, the heart
> of the e-Coast.

as a head hunter, as well as a service provider you should come to

              FPL 2000

as a participant, or, as an exhibitor.

Annual FPL is the eldest international conference on FPGAs
founded 1991 at Oxford University (UK)
high yearly growth rate (attendence 44%, submissions: 50%)
see:   http://xputers.informatik.uni-kl.de/FPL/fpl2000/

Regards,
Reiner Hartenstein

>
>
> The e-Coast stretches from northern Massachusetts to southern Maine
> with Portsmouth, New Hampshire designated as its capital. According to
> a 1999 survey by the American Electronics Association, New Hampshire
> has the highest density of technology employees of any state. There
> are as many as 400 high tech firms in the Greater Portsmouth area and
> hundreds more throughout the region.
>
> The Greater Portsmouth region is attractive to high technology
> companies because it combines several uncommon characteristics:
>
> - Upscale lifestyle Ocean/seaport locale, close proximity to mountains
>
> - Close to UNH, and other area universities with technology focus
>
> - 1-hour to Manchester, Portland, and Boston with easy access to Rt.95.
>
> - Large pool of skilled high-tech workers
>
> - A "hot" place to live (Money magazine rated Portsmouth #5 best place
>   to live in America)
>
> - Numerous cultural and historical amenities
>
> Visit the ASIC Alliance website for more information about
> ASIC Alliance and our employment openings
>
> http://www.asicalliance.com/careers
>
> Visit portsmouthnh.com for information about the Portsmouth region.
> http://www.portsmouthnh.com/
>
> Send resumes to wilcox@asic-alliance.com and
> please cc taetzsch@asic-alliance.com also.
>
> Sent via Deja.com http://www.deja.com/
> Before you buy.

Article: 22031
Subject: Re: XCHECKER 3V adapter
From: Tom Burgess <tom.burgess@home.com>
Date: Fri, 14 Apr 2000 06:11:42 GMT
Links: << >>  << T >>  << A >>
The Xchecker cable drawing on page http://www.xilinx.com/support/programr/cables.htm
also has a little drawing of the HW-XCH3V adapter. Looks like it contains a couple of
5V-3V buffer packages and a simple DC-DC converter to convert the 3.3V device VCC to 5V
for the Xchecker. Avnet lists it (in stock) at $104.50 (http://www.avnetmarshall.com).

I recall that the XLA has 5V tolerant inputs. Maybe all you need is a separate 5V supply
for the Xchecker cable, and a couple of transistors or a relay to gate the 5V so that the
Xchecker is never powered up (and driving device inputs) when the device VCC is off.
Note: You might want to get a second opinion before you go off and start frying
4085XLA parts :) It might be simpler to just buy the adapter.

regards, tom
 

Ricardo Matias Moreno Moll wrote:
> 
> Hello,
> I'm student from Spain and I must configure a FPGA 4085XLA from Xilinx with
> the XCHECKER. I read in the Xilinx web that a 3V adapter is needed to do it,
> because the XCHECKER works at 5V. What is it? Is there a schematic to do it?
> Does anyone help me?
> Thanks.
>
Article: 22032
Subject: Virtex readback
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Fri, 14 Apr 2000 09:24:35 +0100
Links: << >>  << T >>  << A >>
Has anybody managed to do readback from a Virtex part via the JTAG.
AFAIK neither the JTAG programmer nor the Java s/w available on the web
have this facility although it is supposed to be possible.


Article: 22033
Subject: Re: Virtex readback
From: "Alex Flitwick" <benbrick.business@carrotmail.com>
Date: Fri, 14 Apr 2000 02:56:01 -0700
Links: << >>  << T >>  << A >>
Hello

I am looking for PCMCIA IP. I am doing a design using PLDs and I would prefer to avoid having to develop PCMCIA Cores myself. I was wondering if anyone can direct me to a website or company who can provide HDL PCMCIA cores or something similar.

Thank you

Alex
Article: 22034
Subject: PCMCIA Intellectual Property
From: "Alex Flitwick" <benbrick.business@carrotmail.com>
Date: Fri, 14 Apr 2000 03:11:15 -0700
Links: << >>  << T >>  << A >>
Hello

I am working with PLDs at the moments. I need a PCMCIA core or IP I can add to my design. I have had a look around for IP, but I have not had much luck.

I am working with two teams, one using VHDL, the other Verilog. Since like most PLD and FPGA users we want fast time to market, I was wondering if anyone can recommend PCMCIA cores (of any sort) or companies who can provide them.

I am working with Altera technology at the moment, but I am curious about what other companies have to offer.
 
Thank you
 
Alex Flitwick
Benbrick Technology
benbrick.business@carrotmail.com
Article: 22035
Subject: Re: Actel fpgas
From: "Alex Flitwick" <benbrick.business@carrotmail.com>
Date: Fri, 14 Apr 2000 03:22:30 -0700
Links: << >>  << T >>  << A >>
I personally use Altera if it is a PLD. I also find Altera software easier to use.

Alex Flitwick
Article: 22036
Subject: Re: Demo - board
From: Markus Wannemacher <markus.wannemacher@fernuni-hagen.de>
Date: Fri, 14 Apr 2000 13:12:31 +0200
Links: << >>  << T >>  << A >>


Philipp wrote:
> 
> Hello,
>   I'm looking for demo board to do some design practice on my own (the
> university board is not very good). It should work with the Xilinx 4000
> series, have at least 3 7-seg displays and some switches, buttons, ADC,
> etc. and serial download.
> Maybe somebody can recommend me a cheap and good one.

You can find a list of demo boards here:

http://www.aufzu.de/FPGA/boards.html

This list includes also links to other demo board lists:
Optimagic, Altera, Xilinx, Guccione, FreeCore, ...


Markus
Article: 22037
Subject: Re: Demo - board
From: "Gary Watson" <gary@nexsan.sex>
Date: Fri, 14 Apr 2000 14:02:25 +0100
Links: << >>  << T >>  << A >>
Markus Wannemacher <markus.wannemacher@fernuni-hagen.de> wrote in message
news:38F6FD1F.723E9627@fernuni-hagen.de...
>
>
> Philipp wrote:
> >
> > Hello,
> >   I'm looking for demo board to do some design practice on my own (the
> > university board is not very good). It should work with the Xilinx 4000
> > series, have at least 3 7-seg displays and some switches, buttons, ADC,
> > etc. and serial download.
> > Maybe somebody can recommend me a cheap and good one.
>
> You can find a list of demo boards here:
>
> http://www.aufzu.de/FPGA/boards.html
>
> This list includes also links to other demo board lists:
> Optimagic, Altera, Xilinx, Guccione, FreeCore, ...

I would like to suggest the Xess boards at http://www.xess.com as they are
low-cost and very well thought out.  I'm very happy with mine, and they
shipped it to me in England within 3 days of my order.  It appears that the
guy who wrote "The Practical Xilinx Designer Lab Book", which comes with the
Xilinx 1.5 student edition, also runs Xess or works there.  Anyway, good
book, good people, good product.

--

Gary Watson
gary@nexsan.sex  (Change dot sex to dot com to reply!!!)
Nexsan Technologies Ltd.
Derby DE21 7BF  ENGLAND
http://www.nexsan.com







Article: 22038
Subject: Re: XCHECKER 3V adapter
From: rimomol@teleco.upv.es (Ricardo Matias Moreno Moll)
Date: 14 Apr 2000 16:28:58 GMT
Links: << >>  << T >>  << A >>
Thank you very much to Tom Burguess, you were in the right direction.
In Xilinx web I found (http://support.xilinx.com/techdocs/5501.htm) this:

"The power that you provide to an xchecker and JTAG cable is what the control 
signals will be at. If you provide 5 volts to a cable and you are programming 
a 3.3 volt part, you will be driving it with 5 volt control signals which is 
ok in 5 volt tolerant devices.
The XChecker cable needs to be powered at 3.6 volts or higher.
The JTAG cable can run at 3.3 volts and up."

I'm doing a PCB with both 3.3V and 5V, so I don't have any trouble.




In article <8d51l4$vge$1@polaris.cc.upv.es>,
   rimomol@teleco.upv.es (Ricardo Matias Moreno Moll) wrote:
>Hello,
>I'm student from Spain and I must configure a FPGA 4085XLA from Xilinx with 
>the XCHECKER. I read in the Xilinx web that a 3V adapter is needed to do it, 
>because the XCHECKER works at 5V. What is it? Is there a schematic to do it? 
>Does anyone help me?   
>Thanks.
>  
Article: 22039
Subject: Re: Demo - board
From: Laurent Gauch <laurent.gauch@aps-euro.com>
Date: Fri, 14 Apr 2000 12:41:56 -0400
Links: << >>  << T >>  << A >>
Look at www.aps-euro.com

Laurent
( every day is a new beginning)

Gary Watson a écrit :

> Markus Wannemacher <markus.wannemacher@fernuni-hagen.de> wrote in message
> news:38F6FD1F.723E9627@fernuni-hagen.de...
> >
> >
> > Philipp wrote:
> > >
> > > Hello,
> > >   I'm looking for demo board to do some design practice on my own (the
> > > university board is not very good). It should work with the Xilinx 4000
> > > series, have at least 3 7-seg displays and some switches, buttons, ADC,
> > > etc. and serial download.
> > > Maybe somebody can recommend me a cheap and good one.
> >
> > You can find a list of demo boards here:
> >
> > http://www.aufzu.de/FPGA/boards.html
> >
> > This list includes also links to other demo board lists:
> > Optimagic, Altera, Xilinx, Guccione, FreeCore, ...
>
> I would like to suggest the Xess boards at http://www.xess.com as they are
> low-cost and very well thought out.  I'm very happy with mine, and they
> shipped it to me in England within 3 days of my order.  It appears that the
> guy who wrote "The Practical Xilinx Designer Lab Book", which comes with the
> Xilinx 1.5 student edition, also runs Xess or works there.  Anyway, good
> book, good people, good product.
>
> --
>
> Gary Watson
> gary@nexsan.sex  (Change dot sex to dot com to reply!!!)
> Nexsan Technologies Ltd.
> Derby DE21 7BF  ENGLAND
> http://www.nexsan.com

Article: 22040
Subject: XSOC news: articles, Verilog, talk
From: "Jan Gray" <jsgray@acm.org.nospam>
Date: Fri, 14 Apr 2000 17:09:17 GMT
Links: << >>  << T >>  << A >>
1. The second article in my Circuit Cellar magazine series, "Building a RISC
System in an FPGA", is now on newsstands. The first two articles are also
available online -- see www.fpgacpu.org.

2. The XSOC Project (www.fpgacpu.org/xsoc) now includes a synthesizable
Verilog model of XSOC/xr16, in addition to the schematic version.

3. I'll be speaking on XSOC, for Circuit Cellar, at the San Jose, CA,
Computer Literacy bookstore, on this Sunday, April 16, at noon.  See
www.circuitcellar.com/gray-presentation.htm for more information.  My talk
slides are at www.fpgacpu.org/xsoc/talk.html.

Jan Gray
Gray Research LLC



Article: 22041
Subject: Re: XCHECKER 3V adapter
From: "Andy Peters" <apeters.Nospam@nospam.noao.edu.nospam>
Date: Fri, 14 Apr 2000 10:47:51 -0700
Links: << >>  << T >>  << A >>
Tom Burgess wrote in message <38F6B817.5600785C@home.com>...
>
>I recall that the XLA has 5V tolerant inputs.

Only if you set the magic bit during configuration.

-- a
-----------------------------------------
Andy Peters
Sr Electrical Engineer
National Optical Astronomy Observatories
950 N Cherry Ave
Tucson, AZ 85719
apeters (at) noao \dot\ edu

"Money is property; it is not speech."
            -- Justice John Paul Stevens



Article: 22042
Subject: Re: FPGA controlling S-7600A TCP/IP ...
From: "Steven K. Knapp" <sknapp@optimagic.com>
Date: Fri, 14 Apr 2000 16:06:16 -0700
Links: << >>  << T >>  << A >>
I don't know if helps or not but AllAmerican sells a board with a Triscend
device and the Seiko S-7600A.  Take a look at http://www.ikit2000.com.


--
-----------------------------------------------------------
Steven K. Knapp
OptiMagic, Inc. -- "Great Designs Happen 'OptiMagic'-ally"
E-mail:  sknapp@optimagic.com
   Web:  http://www.optimagic.com
-----------------------------------------------------------


"Laurent Gauch" <laurent.gauch@aps-euro.com> wrote in message
news:38E923F1.FA4BBC50@aps-euro.com...
> Hi,
>
> I am searching a example of a VHDL State-Machine working like a MPU
> implementation controlling the new S-7600A chip (TCP/IP Network Protocol
> Stack LSI from Seiko).
>
> Or if somebody know where I can find some flow diagrams about a MPU
> implementation controlling the S-7600A chip, that will be a big help for
> me.
>
> Also, I need to know the gates number in a FPGA or CPLD of a minimal
> State-Machine like this up with only the minimum of controls
> possibilities. If somebody has a idea about this gates number ...
>
> Thank you in advance for your help.
> Have an happy week on this blue planet!
> Laurent
>
> ~~~ laurent.gauch@aps-euro.com ~~~
> Laurent Gauch
> APS-Euro
> www.aps-euro.com
> info@aps-euro.com
> ~~~~~~~~~~~~~~~~~~~~~~~~~~~
>
>


Article: 22043
Subject: Re: Actel fpgas
From: "Simon Ramirez" <s_ramirez@email.msn.com>
Date: Fri, 14 Apr 2000 19:44:58 -0400
Links: << >>  << T >>  << A >>
And you are from Xilinx, Inc.?


Alex Flitwick <benbrick.business@carrotmail.com> wrote in message
news:ee6bdcf.0@WebX.sUN8CHnE...
> I personally use Altera if it is a PLD. I also find Altera software easier
to use.
>
> Alex Flitwick


Article: 22044
Subject: Re: Actel fpgas
From: rk <stellare@nospam.erols.com>
Date: Fri, 14 Apr 2000 20:10:29 -0400
Links: << >>  << T >>  << A >>
Simon Ramirez wrote:

> And you are from Xilinx, Inc.?
>
> Alex Flitwick <benbrick.business@carrotmail.com> wrote in message
> news:ee6bdcf.0@WebX.sUN8CHnE...
> > I personally use Altera if it is a PLD. I also find Altera software easier
> to use.
> >
> > Alex Flitwick

The organization was labelled Xilinx, the Subject was Actel, and the preference
was Altera!

:-)


Article: 22045
Subject: Re: XCHECKER 3V adapter
From: Tom Burgess <tom.burgess@hia.nrc.ca>
Date: Fri, 14 Apr 2000 17:51:24 -0700
Links: << >>  << T >>  << A >>
Good point - This would be the "5V tolerant I/O" checkbox in 
the configuration options dialog. When checked, this presumably
prevents the VCC I/O clamping diodes (needed for 3.3V PCI compliance)
from being enabled after configuration. Since the data sheet does
not say that the config and JTAG pins do or do not have these diodes,
one must assume the worst.

regards, tom

Andy Peters wrote:
> 
> Tom Burgess wrote in message <38F6B817.5600785C@home.com>...
> >
> >I recall that the XLA has 5V tolerant inputs.
> 
> Only if you set the magic bit during configuration.
> 

-- 
Tom Burgess
Digital Engineer
Dominion Radio Astrophysical Observatory
P.O. Box 248, Penticton, B.C.
Canada V2A 6K3
Article: 22046
Subject: synchronous FIFO
From: Taras Zima <tzima1@jps.net>
Date: Sat, 15 Apr 2000 13:34:28 -0700
Links: << >>  << T >>  << A >>
<!doctype html public "-//w3c//dtd html 4.0 transitional//en">
<html>
I am looking for a way to synchronizes an asynchronous FIFO.&nbsp; The
verilog module of FIFO was generated by Xilinx Core Generator.&nbsp; I
am using Spartan XL FPGA family.&nbsp; Does any one can point me to a site
with information on this topic?
<br>Thanks,
<br>tz</html>

Article: 22047
Subject: FPGA/PLD design tools?
From: Vasant Ram <12111_1vasantr6_32_3@utdallas.edu>
Date: 15 Apr 2000 22:24:17 GMT
Links: << >>  << T >>  << A >>
Hey all.

I have a few questions on on the VHDL/FPGA software that is available.

I've heard of several packages like ModelSim, FPGA Express, Leonardo
Spectrum, VeriBest, etc.

What I want to know is to these tools produce files that you can use to
directly program into a part? Also do they allow free-mixing of VHDL code
and schematic capture like Altera's Max+Plus II (where you can make a .GDF
of AHDL/VHDL code and then use it in schematic entry)?

The design flow as I know it goes something like:

Come up with an idea 

Start a new project 

Write the VHDL / Schematic entry / State Machines / Verilog

Fix all the errors to satisfaction so it compiles 

After it compiles, use a "waveform editor" and apply input stimuli and
look at timing etc. 

Repeat above steps if timing isn't satisfactory

Recompile

When finished, take output file and program to part

Granted I skipped a lot of important steps (timing constraints, etc) but
does one tool do all of these? From what I've seen on the many products'
websites, the are generally 4 components to the software package:

A) VHDL & Schematic capture
B) Compiling
C) Simulating (looking at waveforms)
D) Programming part?

As for the last step however, I've always been led to believe that
something like ModelSim can be used to do all the work up to coming up
with the program for the part which has to be done by the part vendors'
Place & Route tool?

Thanks for any clarification,
Vasant.
Article: 22048
Subject: Re: synchronous FIFO
From: Peter Alfke <palfke@earthlink.net>
Date: Sat, 15 Apr 2000 22:26:43 GMT
Links: << >>  << T >>  << A >>
At Xilinx, we use the name "asynchronous FIFO" for a FIFO with
completely independent write and read clocks. Such a FIFO bridges the
gap between different clock domains.
There is no need to synchronize such a FIFO. It does the
synchronization.

A "synchronous FIFO" would use the same clock for write and read. Such a
design is a trivial subset of the more general asynchronous case.

Sorry if we confused you by our nomenclature.

Peter Alfke, Xilinx Applications
=============================================
Taras Zima wrote:

> I am looking for a way to synchronizes an asynchronous FIFO.  The
> verilog module of FIFO was generated by Xilinx Core Generator.  I am
> using Spartan XL FPGA family.  Does any one can point me to a site
> with information on this topic?
> Thanks,
> tz

Article: 22049
Subject: Re: FPGA/PLD design tools?
From: Ray Andraka <randraka@ids.net>
Date: Sun, 16 Apr 2000 01:07:46 GMT
Links: << >>  << T >>  << A >>
Nope, modelsim is pretty much just a simulator.

Here's the some of what's what, but by no means a complete list

Schematic capture:
    Viewlogic
    Aldec (foundation)
    Orcad

HDL design entry
    Aldec
    others

simulation
    Aldec (VHDL and soon verilog)
    modelsim (VHDL/verilog)
    viewlogic (great for schematics, weak for vhdl, no vhdl93 support)

Synthesis  (VHDL/verilog to netlist with logic primitives)
    Synplicity
    Exemplar (leonardo)
    FPGA express

Place and Route
    from the FPGA vendors.


You'll need something from each category (HDL entrya nd schematic fall under
the same category).  The simulator and synthesis tools have text editors and
debug features in them, but they are not very good for design entry.  Veribest
is, I think a formal verification tool so it is an additional piece.  Only the
FPGA place and route tools generate the bitstreams for the part.  Altera has a
schematic and hdl facility built into their maxplus tools, but it locks you
into that device and toolset.  You can generally mix VHDL and schematic at the
input of the FPGA tools, but you will have to instantiate one or the other
into your top level to get it all to play nice.


Vasant Ram wrote:

> Hey all.
>
> I have a few questions on on the VHDL/FPGA software that is available.
>
> I've heard of several packages like ModelSim, FPGA Express, Leonardo
> Spectrum, VeriBest, etc.
>
> What I want to know is to these tools produce files that you can use to
> directly program into a part? Also do they allow free-mixing of VHDL code
> and schematic capture like Altera's Max+Plus II (where you can make a .GDF
> of AHDL/VHDL code and then use it in schematic entry)?
>
> The design flow as I know it goes something like:
>
> Come up with an idea
>
> Start a new project
>
> Write the VHDL / Schematic entry / State Machines / Verilog
>
> Fix all the errors to satisfaction so it compiles
>
> After it compiles, use a "waveform editor" and apply input stimuli and
> look at timing etc.
>
> Repeat above steps if timing isn't satisfactory
>
> Recompile
>
> When finished, take output file and program to part
>
> Granted I skipped a lot of important steps (timing constraints, etc) but
> does one tool do all of these? From what I've seen on the many products'
> websites, the are generally 4 components to the software package:
>
> A) VHDL & Schematic capture
> B) Compiling
> C) Simulating (looking at waveforms)
> D) Programming part?
>
> As for the last step however, I've always been led to believe that
> something like ModelSim can be used to do all the work up to coming up
> with the program for the part which has to be done by the part vendors'
> Place & Route tool?
>
> Thanks for any clarification,
> Vasant.

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka




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