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As I know the foundation i version has some internet "Java based" cabibilities. Can I install it on a server then allow group of designers to use it over the internet not only on local network? Thanks Jamil KhatibArticle: 22126
In the early days Viewlogic introduced, like many others, its own multi-value logic type: 'vlbit'. Viewlogic also added in 1990 a package 'pack1076' that makes it possible to simulate the vlbit and related functions on other platforms. This package is still available in the current version of the Viewlogic tooling. Look for the file 'pack1076.vhd' (probably you can find it in: ..\wvoffice\standard\VHDLLIBS\ ) Copying a file is often not allowed, but it is allowed for this file! On 04-Mar-91 the copyright notice is removed. Probably this will help you. You want to port your description to the IEEE standard logic type. But this is not enough. In the current description 'addum' is used: addum means "ADD with UNSIGNED MAGINUTED interpretation of the operands. There is also a function 'add2c', with twos complement interpretation of the operands. The std_logic type (IEEE package std_logic_1164) does not include an interpretation for the vector. So addition of std_logic_vector is not possible. You also need to use the package NUMERIC_STD (also an IEEE standard since 1997). This package defines the type SIGNED and UNSIGNED, similar to std_logic_vector but the arithmetic operators are supported. (If your tool does not yet support this package, you can probably use package std_logic_arith). There are a number of things that are to be taken care off, e.g.: - v1d2int interpretates the operants as a twos complement number! (when I'm corect, it's a long time ago I used this package) - addum interpretates de operands as an unsigned AND the output vector includes a carry bit. The length of the output is ONE LONGER then the longest input vector. Whereas in the package NUMERIC_STD the length of the result is the same as the longest input vector (NO carry is included). Maybe this helps, Regards, Egbert Molenkamp University of Twente the Netherlands Tobin Fricke wrote: > Hello, > I have a VHDL model written for a xilinx environment which uses the > "vlbit" and "vlbit_1d" types, as well as operators such as "vld2int" and > "addum". I'd like to port this over to an altera environment (maxplus) > and use IEEE standard logic, but I'm not sure what the analogous > operations are for stdlogic and stdlogic_vector. Could anyone help me > out or point me in the right direction? I found this question asked a > couple times in the past on dejanews, but no solutions. > > Thanks, > Tobin <tobin@cory.eecs.berkeley.edu>Article: 22127
As far as I know there is now such tool, but there is a tool called vpr it is free and opensource but it does not generate bitstreem file. but the problem I do not remember anymore the http address Jamil Khatib Chris Plachta wrote: > Hi, > > I was wondering if there are any good third-party place and route tools > for FPGAs out there. > > Specifically, I am looking for a tool that preserves the hierarchy and > net names in the post-route database. I just finished an Altera design > that had post-route timing problems, and we had no way of performing a > good static timing analysis or post-route simulation since all of the > registers and nets were renamed by the Altera tool, and there is no > known mapping back to the original source code. We had to debug the > problem in the lab. > > Thanks. > > -- > Chris Plachta > Alcatel USA > Phone: 707-792-7271 > FAX: 707-792-6310Article: 22128
Could someone tell me why it is a disadvantage to have a high gate count?Article: 22129
rja3 wrote: > > Could someone tell me why it is a disadvantage to have a high gate > count? Er, because you have to put them somewhere, and silicon costs money ? -- Cheers, John ________________________________________ Philips Semiconductors - CD Systems mailto:John.Ireland@philips.com Tel. +44 (0) 23 80312 667 FAX. +44 (0) 23 80316 304 ________________________________________Article: 22130
>>you can also do the PID or other control fucntion in the FPGA >>and eliminate the processor, I'm look for information on how to do just that. Can you point me to sources of information onImplementing a PID controller using a FPGA. Thanx Koma Tose * Sent from RemarQ http://www.remarq.com The Internet's Discussion Network * The fastest and easiest way to search and participate in Usenet - Free!Article: 22131
>>you can also do the PID or other control fucntion in the FPGA >>and eliminate the processor, I'm look for information on how to do just that. Can you point me to sources of information for Implementing a PID controller using a FPGA. Thanx Koma Tose * Sent from RemarQ http://www.remarq.com The Internet's Discussion Network * The fastest and easiest way to search and participate in Usenet - Free!Article: 22132
I design Xilinx FPGA based circuit boards. Some of my customers in the past have copied and manufactured my boards to avoid buying them from me. How can I design my circuit boards to vastly reduce the chances of them being copied. The main problem is the Xilinx bitstream is easy to copy. Thanks DanArticle: 22133
I did a quick test design, and got the same error. IPAD connected to both the input of an IBUF and an IFD. I agree this should work, and the view in FPGA editor indicates that it should be possible. This type of connection is often used in pulling apart a miltiplexed address/data bus coming into a FPGA, and I know it works in all XC3K, and all XC4K families. It certainly looks like the hardware in Virtex is designed to support it too. I expect that this will fail with VHDL and Verilog design entry too. Looks like a bug. You should report it to Xilinx hotline, so they can start on fixing it. Philip In article <01bfaf0c$176497c0$c4f262d1@Dan.i-tech.com>, Dan Kuechle <dan_kuechle@i-tech.com> wrote: >I'm trying to use an IBUF and an IFD on an input signal on a single pin. >I know this is ok in the 4000 series, but I'm getting errors in Virtex: >"ERROR:NgdHelpers:342 - input pad net "A_IN" drives multiple buffers". >If I go into fpga editor it seems like I should be able to do this. >Is this a S/W bug or is there a reason why I can't use both the IBUF >and the IDF of an input pin? I'm running F2.1I on a PC. > >ThanksArticle: 22134
Johnny, I agree with Dan, this is a bug. Please see my other posting on this thread for details. The failing topology is NOT IPAD though an IBUF to an IFD (which I agree is not valid), it is an IPAD connected to the input of both an IBUF and an IFD, which should be valid. Philip Freidin In article <ee6c4e0.0@WebX.sUN8CHnE>, Johnny <> wrote: >Hello Dan, > >This is not a bug in the software. The IFD is connected to an IPAD or an IOPAD (without using an IBUF). This information is in the Libraries Guide which can be viewed at http://toolbox.xilinx.com/docsan/2_1i/data/common/lib/lib.htm > >Best Regards, >Johnny >Xilinx Customer ApplicationsArticle: 22135
In article <h8EN4.148779$1C2.3655423@news20.bellglobal.com>, Dan <daniel.deconinck@sympatico.ca> wrote: >I design Xilinx FPGA based circuit boards. >Some of my customers in the past have copied and manufactured my boards to >avoid buying them from me. >How can I design my circuit boards to vastly reduce the chances of them >being copied. The main problem is the Xilinx bitstream is easy to copy. >Thanks Dan Get better customers?Article: 22136
You can achieve this using schematics or HDL entry methods. Probably what you should consider is that constraints would apply to the design no matter how it was specified. Your design would be more flexible in this respect if you designed using IBUF and FD rather than IBUF and IFD and let the software decide the implementation based on these constraints. You can force an FD to be placed in an IOB (giving an IFD) by using map -pr b which places both input and output flip flops in the IOB's. IF you use the unregistered pin signal elsewhere in the design then the signal will bypass the IFD and you will have the result you were after. Bill Philip Freidin <fliptron@netcom.com> wrote in message news:8e743l$bnk$1@slb0.atl.mindspring.net... > > I did a quick test design, and got the same error. IPAD connected to > both the input of an IBUF and an IFD. I agree this should work, and the > view in FPGA editor indicates that it should be possible. This type > of connection is often used in pulling apart a miltiplexed address/data > bus coming into a FPGA, and I know it works in all XC3K, and all XC4K > families. It certainly looks like the hardware in Virtex is designed to > support it too. > > I expect that this will fail with VHDL and Verilog design entry too. > > Looks like a bug. You should report it to Xilinx hotline, so they can > start on fixing it. > > Philip > > > In article <01bfaf0c$176497c0$c4f262d1@Dan.i-tech.com>, > Dan Kuechle <dan_kuechle@i-tech.com> wrote: > >I'm trying to use an IBUF and an IFD on an input signal on a single pin. > >I know this is ok in the 4000 series, but I'm getting errors in Virtex: > >"ERROR:NgdHelpers:342 - input pad net "A_IN" drives multiple buffers". > >If I go into fpga editor it seems like I should be able to do this. > >Is this a S/W bug or is there a reason why I can't use both the IBUF > >and the IDF of an input pin? I'm running F2.1I on a PC. > > > >Thanks > >Article: 22137
In article <8e74ct$bs3$1@slb2.atl.mindspring.net>, fliptron@netcom.com (Philip Freidin) wrote: > > Johnny, > I agree with Dan, this is a bug. Please see my other posting on > this thread for details. The failing topology is NOT IPAD though an IBUF > to an IFD (which I agree is not valid), it is an IPAD connected to the > input of both an IBUF and an IFD, which should be valid. > > Philip Freidin > > In article <ee6c4e0.0@WebX.sUN8CHnE>, Johnny <> wrote: > >Hello Dan, > > > >This is not a bug in the software. The IFD is connected to an IPAD or an IOPAD (without using an IBUF). This information is in the Libraries Guide which can be viewed at http://toolbox.xilinx.com/docsan/2_1i/data/common/lib/lib.htm > > > >Best Regards, > >Johnny > >Xilinx Customer Applications > > I followed the link provided by Johnny, pushed down a little further, and found this: http://toolbox.xilinx.com/docsan/2_1i/data/common/lib/fig192.htm So then, it looks like the simultaneous IBUF and IFD is valid, but it must be specified differently for Spartan II and Virtex. It looks like you use a normal FD, and apply an attribute that says IOB = TRUE. See: http://toolbox.xilinx.com/docsan/2_1i/data/common/lib/lib12_6.htm#X83760 So it isn't a bug. It is only a highly annoying and non-portable change in methodology for specifying an IFD. -- Greg Neff VP Engineering *Microsym* Computers Inc. greg@guesswhichwordgoeshere.com Sent via Deja.com http://www.deja.com/ Before you buy.Article: 22138
Komatose wrote in message <133bccca.3a116135@usw-ex0106-045.remarq.com>...
>>>you can also do the PID or other control fucntion in the FPGA
>>>and eliminate the processor,
>
>I'm look for information on how to do just that. Can you point
>me to sources of information for Implementing a PID controller
>using a FPGA.
Do you know what a PID loop is? Can you write a block diagram for it? Can
you write C code to implement it? Do you know an HDL?
-- a
-----------------------------------------
Andy Peters
Sr Electrical Engineer
National Optical Astronomy Observatories
950 N Cherry Ave
Tucson, AZ 85719
apeters (at) noao \dot\ edu
"Money is property; it is not speech."
-- Justice John Paul Stevens
Article: 22139BTW, the reason for the error message is that the Virtex IFD macro instantiates an IBUF, and with Virtex it is illegal to have two IBUFs in the same IOB. So, you need an IBUF in series with an FDxx, where the FDxx has an attribute of IOB = TRUE. In other words, duplicate the IFD macro, but use IBUF output to feed you logic as well. This should produce the desired implementation. -- Greg Neff VP Engineering *Microsym* Computers Inc. greg@guesswhichwordgoeshere.com Sent via Deja.com http://www.deja.com/ Before you buy.Article: 22140
Suggestions:
1. Add to your services contract the usual clauses about conflict arbitration, etc.
2. Add to your services contract clauses about "you retain all rights, production
rights for intellectual property are available for a fee".
3. Enforce/defend your property rights. Retain and use a lawyer. If bitstreams
were copied without reverse engineering, it should be pretty simple to establish
the act of theft/copying (no source code, your honour ?).
4. Add little things like version number registers into the design which would
help establish the origin and uniqueness of the design.
5. And the suggestion by another respondent is very very appropriate:
pick better customers. Never do business with someone who doesn't
honour/respect others. There are too many good/honourable clients
out there. Eventually the irresponsible/dishonourable ones will
need services, and noone competent will be willing to do business
with them (including their own employees).
-- Bob Elkind
Dan wrote:
>
> I design Xilinx FPGA based circuit boards.
>
> Some of my customers in the past have copied and manufactured my boards to
> avoid buying them from me.
>
> How can I design my circuit boards to vastly reduce the chances of them
> being copied. The main problem is the Xilinx bitstream is easy to copy.
>
> Thanks Dan
Article: 22141Hi and please help... I am converting a design (inherited and 95% of the real-estate is full) from ACTmap to Synplify synthesis tool for a 54SX chip. Synplify seems to have reduced the real-estate usage to 78% (how??) but the final design which worked with the ACTmap path does not work with the sunplify path. I had to force synplify to not use global (HCLK) buffers to keep the pinout I needed. I know, this is not much to go on, but I hope some one has been there before! How can I gain almost 20% real-estate just by switching to synplify....what am I doing wrong???? Thanks... Mike * Sent from RemarQ http://www.remarq.com The Internet's Discussion Network * The fastest and easiest way to search and participate in Usenet - Free!Article: 22142
Hi,
I am interested in contracting out the
following HW + the accompanying software
drivers. Please contct me via email if this
is something you might be interested in?
Thanks,
Peter Wyckoff
wyckoff@xpdisk.com
-----------------------------------------
------------------
| |
| PC #1 |
| motherboard |
| | ----------
| | | |
| *-|-------------| IDE |
| (1)*-|-------------| HD |
| *-|-------------| |
| | | |
------------------ ----------
(1) standard IDE (AT) host adapter
The above diagram shows a (host) PC
motherboard connected to a IDE HD via a
standard ribbon. The above diagram is
standard; it is drawn to illustrate the next
thing. What I want to do is shown in the
diagram below.
------------------
| |
| PC #1 | --------------
| motherboard | | |
| | | PC #2 | ----------
| | | | | |
| *-|----|-* *-|-----| IDE |
| (1)*-|----|-*(2) (1)*-|-----| HD |
| *-|----|-* *-|-----| |
| | | | | |
------------------ | | ----------
-------------
(1) standard IDE (AT) host adapter
(2) HW board, see below.
In a nutshell, I would like PC #2, in
conjunction with the HW board to pretend it
is a standard IDE hard drive to PC #1.
Specifically, I would like to add a new
motherboard between PC #1 and the disk. The
job of this new motherboard, PC #2, is to
bridge the two devices and to execute a
proprietary algorithm - the algorithm is not
important. What is important is to realize
that the PC #2 intercepts the read/write
requests directed to the HD, and processes
the requests as it chooses. The function of
the HW board (2 in the above diagram) is to
implement the disk-side of the ATA protocol,
and send the read/write requests to a
user-level process on PC #2. Obviously the
HW board requires a device driver. The bus
the HW board plugs into can be any standard
bus (e.g., PCI, ISA --- I am not worried
about performance at this time).
I would prefer to run Linux on PC #2.
Clearly the items marked with "1" on the
diagram are standard IDE adapters (where a
ribbon plugs in).
Article: 22143The Data IO programmers cost $1500ish to program Xilinx SPROM. Does anyone know of a more reasonably priced one ? Thanks DanArticle: 22144
Hi, I am conducting a study on logic design practices and am now surveying the opinions of different designers in the field. A first set of circuits have been posted at url http://rk.gsfc.nasa.gov/DesignStudy.htm and are real; not academic exercises. They are implemented in Actel technology and were originally intended for the hi-rel environment without the potential for service or repair. What do you think of these circuits and design styles and practices? There are no severe performance or resource issues associated with these circuits and they operate at speeds that are reasonable for the technology. Please note that there are no names or organizations shown on these schematics as this is a technical exercise. Please send me your responses at rich.katz@NOSPAMPLEASE.gsfc.nasa.gov if you do not wish to post here. Thank you, Richard B. Katz National Aeronautics and Space AdministrationArticle: 22145
Hi!!
This is what I get from Max+Plus2's help...... I really have no idea what
that means.... &
what I can do to solve the problem.
In fact, I find that this warning mesg "Design doctor warning: Unknown
combinatorial feedback structure
detected at primitive 'lpm_RAM_IO:9|'altram:sram|segment0_4' "
also occurs to my other bus (which is a bidir bus)
I have sent the multiple cycles instructions to synplicity online help..
I'll see what they can do....
Any advice is much appreciated!!
Rgds
VHDL beginner
*****
CAUSE: A network of cross-coupled logic cannot be identified. This logic is
creating a latch, flipflop, or delay, and is not an Altera-provided
primitive, megafunction,or macrofunction. You should use only the expander
flipflop and expander latch macrofunctions provided with MAX+PLUS II. In
addition, you should use these expander flipflop and expander latch
macrofunctions only after all dedicated flipflop and latch resources in the
device (i.e., logic cells and I/O cells) have been used.
ACTION: If dedicated flipflop and latch resources are available in the
device and the logic was a latch or flipflop function, replace it with LATCH
or DFF primitive. If all dedicated resources have already been used, replace
the logic with an equivalent Altera-provided expander macrofunction such as
expdff or explatch. If this message occurs for a delay structure, redesign
the network so that it does not depend on internal timing parameters. For an
example of a good design alternative to a delay chain, see Delay Chain
Examples.
*****
<rajkumar@gdatech.com> wrote in message news:8dr97g$v7m$1@nnrp1.deja.com...
> Hi!
> I dont know what this Warning means Top of my head.
> But there is one way, Just double click on this warning, and MaxplusII
> will give you the reasons for this warning.
> Also it will tell you about the seriousness of the warning, and what
> steps you need to take.
>
> As far as multicycle path or false path is concerned, i do not think
> there is any way to make it known to the Altera MaxPlusII.
> But i have heard ( never tried) Quartus tool, which probably has all
> this features.
>
>
> Rajkumar...
>
> In article <8dlmug$m4k$1@violet.singnet.com.sg>,
> "MK Yap" <mkyap@REMOVE.ieee.org> wrote:
> > Hi all,
> >
> > [1]
> >
> > I'm writing VHDL codes using synplify (5.3.1) to interface with
> Altera's
> > LPM-RAM_IO (single IO port RAM).... I'm using Max+Plus2 9.3, device
> > Flek10k100e
> >
> > During compilation, i encounter this warning message....
> > "Design doctor warning: Unknown combinatorial feedback structure
> detected
> > at primitive 'lpm_RAM_IO:9|'altram:sram|segment0_4' "
> >
> > During timing simulation, it works fine... but haven't tried out on
> the real
> > hardware platform yet...
> >
> > I believe the problem lies in the fact that the data bus is
> bidirectional.
> > In the VHDL module, it is always at the receiving end (config. as
> input)
> > unless it needs to write data to the RAM.... Pls advice on the warning
> > message.
> >
> > [2]
> > I have a simple code below... Since j is a 12 bit counter, the
> execution (12
> > bit addition) is pretty slow. The maximum frequency this circuit can
> work is
> > ard 80+MHz on flex 10k100e-3... esp if there is an IF
> statement.....
> > To overcome this, I define a constraint
> > define_multicycle_path -to {j[11:0]} 3
> > recompile and the max frequency improves to 137MHz (in synplify 5.3.1)
> >
> > I copied the edf and acf file to another directory and import to
> altera
> > max+plus2, recompile... but the timing analysis shows that the max
> frequency
> > this circuit can run is only 40+Mhz??????????
> > btw, I tried normal, fast & WYSIWYG, all shows frequency ard
> 40-50MHz!!!!!!
> > How can I tell explicitly max++2 that that is a multiple cycle
> instruction
> > or edf file has already taken care of that??
> >
> > Pls advice. Thank you very much!!!
> >
> > Regards
> > MK
> >
> > LIBRARY ieee ;
> > USE ieee.std_logic_1164.all;
> > USE ieee.std_logic_arith.all;
> > USE ieee.std_logic_unsigned.all;
> >
> > ENTITY test IS
> > PORT(
> > nReset : in STD_LOGIC;
> > MClk : in STD_LOGIC;
> > FIFO_Data1 : in STD_LOGIC_VECTOR(15 downto 0);
> > FIFO_Data2 : in STD_LOGIC_VECTOR(15 downto 0);
> > FIFO_DataAvail : in STD_LOGIC;
> > FIFO_Answer : out STD_LOGIC_VECTOR(15 downto 0);
> > Cntr : out STD_LOGIC_VECTOR(11 downto 0)
> > );
> > END test;
> >
> > ARCHITECTURE Controller OF test IS
> >
> > SIGNAL j : INTEGER RANGE 0 TO 2353;
> > BEGIN
> >
> > MainInterface: PROCESS(nReset,MClk)
> > BEGIN
> > IF nReset='0' THEN
> > j<=0;
> > FIFO_Answer <=(OTHERS=>'0');
> > ELSIF (MClk'event AND MClk='0') THEN
> > IF FIFO_DataAvail='1' THEN
> > IF j=2352 THEN
> > j <=0;
> > ELSE
> > j<=j+1;
> > END IF;
> > FIFO_Answer <= FIFO_Data1+FIFO_Data2;
> > END IF;
> >
> > END IF;
> > END PROCESS MainInterface;
> >
> > Cntr <=CONV_STD_LOGIC_VECTOR(j,12);
> > END Controller;
> >
> >
>
>
> Sent via Deja.com http://www.deja.com/
> Before you buy.
Article: 22146Dan, I wrote some simple software to program ATMEL AT17LV512 EEPROMs with Xilinx bitstreams. I am using a Xilinx Parallel Cable 3 to interface with the I2C bus, but any other hardware could do. Would this help? Best regards Felix In article <TVLN4.82050$2D6.2061048@news20.bellglobal.com>, "Dan" <daniel.deconinck@sympatico.ca> wrote: > The Data IO programmers cost $1500ish to program Xilinx SPROM. Does anyone > know of a more reasonably priced one ? > > Thanks Dan > > Sent via Deja.com http://www.deja.com/ Before you buy.Article: 22147
>>Do you know what a PID loop is? Yes. >>Can you write a block diagram for it? Yes. >>Can you write C code to implement it? Yes. >>Do you know an HDL? I know ABEL - HDL and I'm learning VHDL. But I don't know much about FPGAs and that's where I was poping you could help. Thanks Koma Tose * Sent from RemarQ http://www.remarq.com The Internet's Discussion Network * The fastest and easiest way to search and participate in Usenet - Free!Article: 22148
In article <MxUGOV2Poq+mZWykDEX+aNBcErxq@4ax.com>, Florindo Santoro <flosan@tin.it> wrote: > Where can I Buy the FPGAs chip ?(On line) > Try http://chipcenter.com You probably can get better price from your local dealer. Regards, Rotem ------------------------------------------------------------- Rotem Gazit MystiCom LTD. mailto:rotemg@mysticom.com http://www.mysticom.com ------------------------------------------------------------ Sent via Deja.com http://www.deja.com/ Before you buy.Article: 22149
<felix_bertram@my-deja.com> wrote in message news:8e8oqo$3cv$1@nnrp1.deja.com... > Dan, > > I wrote some simple software to program ATMEL AT17LV512 EEPROMs with > Xilinx bitstreams. I am using a Xilinx Parallel Cable 3 to interface > with the I2C bus, but any other hardware could do. Would this help? Atmel sell a "cheap" programmer unit for their serial EEPROMs, called the ATDH2200E. It plugs into a PC parallel port, and in the UK it costs around £235. MH.
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