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Messages from 22150

Article: 22150
Subject: Xilinx "length count" question
From: Kevin Klopfenstein <kevin.klopfenstein@si.com>
Date: Thu, 27 Apr 2000 09:43:36 -0400
Links: << >>  << T >>  << A >>

I'm trying to reconcile the length count and final address
of a .mcs file generated by Xilinx's promgen tool.
According to the datasheet for my Xilinx part (XC4020E),
the PROM size requirement is 329,312 bits.  The last
byte address of the .mcs file is 0xA0CC = 41164.  Multiplying
that by 8 bits/byte yields the expected result, 329,312.

The length count field, however, works out to 329,305.  Here's
the second line of my .mcs file:

:10000000FF040AA6F9EAFF7CFDF5D7DF6CF7DDD720

The command used to generate the file was

> promgen -s 512 -u 0 mydesign

It seems to me that the length count should match the PROM
size, shouldn't it?  What am I missing?

Thanks,
Kevin Klopfenstein
Smiths Industries Aerospace
Article: 22151
Subject: AHDL to Verilog
From: Jerry English <jenglish@planetc.com>
Date: Thu, 27 Apr 2000 14:14:16 -0400
Links: << >>  << T >>  << A >>
 Looks like we are going to consolidate some FPGAs into one big one.
Of course some where done in AHDL while others in Verilog. What
I would like to know/find is a program that converts AHDL to verilog
so incorporation, simulation and maintenance of the one FPGA is
simplified.
Anybody know of such program??

Thanks
Jerry


Article: 22152
Subject: Re: Xilinx "length count" question
From: Tom Fischaber <tom.fischaber@xilinx.com>
Date: Thu, 27 Apr 2000 13:30:10 -0600
Links: << >>  << T >>  << A >>
I believe that the prom file size is rounded up to the next byte.  Since
your Length Count is 329305, the prom size is thus rounded up to 329312.

Tom Fischaber
Xilinx Customer Applications

Kevin Klopfenstein wrote:

> I'm trying to reconcile the length count and final address
> of a .mcs file generated by Xilinx's promgen tool.
> According to the datasheet for my Xilinx part (XC4020E),
> the PROM size requirement is 329,312 bits.  The last
> byte address of the .mcs file is 0xA0CC = 41164.  Multiplying
> that by 8 bits/byte yields the expected result, 329,312.
>
> The length count field, however, works out to 329,305.  Here's
> the second line of my .mcs file:
>
> :10000000FF040AA6F9EAFF7CFDF5D7DF6CF7DDD720
>
> The command used to generate the file was
>
> > promgen -s 512 -u 0 mydesign
>
> It seems to me that the length count should match the PROM
> size, shouldn't it?  What am I missing?
>
> Thanks,
> Kevin Klopfenstein
> Smiths Industries Aerospace

Article: 22153
Subject: Instantiating and Compiling Altera LPM Macros with Synplify
From: nestor@stansync.com (Nestor)
Date: Thu, 27 Apr 2000 19:51:25 GMT
Links: << >>  << T >>  << A >>
Hi.

Has anyone ever tried to instantiate Altera lpm components in VHDL for
synthesis in synplify with place and route in Maxplus2.  

I will be using the black_box attribute in VHDL, but I am not clear on
what I need to do in Maxplus2 to generate the required component.  I
would like as much as possible to have Maxplus2 automatically create
the macro function I would like to use (lpm_rom, for instance), based
on generics that I will specify in my VHDL code, i.e., the ROM
filename (MIF file) and the data widths.   Is this possible, or do I
need to manually create the macro in Maxplus2 using the wizard every
time I need a new ROM?

Your help is greatly appreciated.

Nestor


Article: 22154
Subject: testing
From: khoi ha <kha@fallschurch.esys.com>
Date: Thu, 27 Apr 2000 16:48:22 -0400
Links: << >>  << T >>  << A >>


Article: 22155
Subject: Verilog Compiler ?
From: antera@mweb.co.za (Anton Erasmus)
Date: Thu, 27 Apr 2000 21:55:26 GMT
Links: << >>  << T >>  << A >>
Hi,

I Have done some simple EPLD designs in AHDL, but I want to start to
use Verilog and/or VHDL. Unfortuanetly the Free License version of
Alteras Max+Plus II does not support Verilog and VHDL. Is there a free
Compiler which I can use to test Compile simple Verilog and maybe
simulate ? 

Regards
   Anton Erasmus

Article: 22156
Subject: FPGA + DSP24 = Super Performance DSP
From: Rick Milado <rqmilado@my-deja.com>
Date: Thu, 27 Apr 2000 15:31:24 -0700
Links: << >>  << T >>  << A >>

We have been using a new DSP chip called the
DSP24, see:

http://www.DSParchitectures.com

This chip is attached to a FPGA is a perfect for
high data rate, or multi-channel DSP applications.

The DSP24 comes in a wide variety of price and
performance.

Thought you might want to check it out.

Rick Milado
Consultant

Article: 22157
Subject: Re: Xilinx "length count" question
From: Peter Alfke <peter@xilinx.com>
Date: Thu, 27 Apr 2000 17:33:33 -0700
Links: << >>  << T >>  << A >>
When you multiply the number of bytes by 8 you obviously get a
bit-count that is a multiple of eight  :-)
But the chip does not have this requirement. In this particular case
it is filled up with seven fewer bits. So the final bits in the bit
stream are jut fill bits.
If you feel like beefing up the length count to a higher number, you
can do that. It will just result in slightly longer configuration
time.

Peter Alfke, Xilinx Applications

Kevin Klopfenstein wrote:

> I'm trying to reconcile the length count and final address
> of a .mcs file generated by Xilinx's promgen tool.
> According to the datasheet for my Xilinx part (XC4020E),
> the PROM size requirement is 329,312 bits.  The last
> byte address of the .mcs file is 0xA0CC = 41164.  Multiplying
> that by 8 bits/byte yields the expected result, 329,312.
>
> The length count field, however, works out to 329,305.  Here's
> the second line of my .mcs file:
>
> :10000000FF040AA6F9EAFF7CFDF5D7DF6CF7DDD720
>
> The command used to generate the file was
>
> > promgen -s 512 -u 0 mydesign
>
> It seems to me that the length count should match the PROM
> size, shouldn't it?  What am I missing?
>
> Thanks,
> Kevin Klopfenstein
> Smiths Industries Aerospace

Article: 22158
Subject: Re: Is there any DSP and FPGA based board suitable to motor
From: Rickman <spamgoeshere4@yahoo.com>
Date: Thu, 27 Apr 2000 23:20:31 -0400
Links: << >>  << T >>  << A >>
Komatose wrote:
> 
> >>you can also do the PID or other control fucntion in the FPGA
> >>and eliminate the processor,
> 
> I'm look for information on how to do just that. Can you point
> me to sources of information onImplementing a PID controller
> using a FPGA.
> 
> Thanx
> 
> Koma Tose


No sorry, I am not familiar with motor control. But if you can define
how your PID controller should operate, I am sure that we could
implement it in the FPGA for you. But we would likely need to construct
a motor control interface module unless you can work with digital IO or
sigma-delta ADCs to generate an analog voltage output. 

The FPGAs are on our DSP board. We have one which controls a 44 pin
connector, pinned out like an IDE interface. The others are intended to
drive our AIO modules. We currently do not have an AIO module for motor
control. But we do have an AIO module for analog IO via sigma-delta
converters at up to 16 bits and 48 KHz sample rates. 

The intent is that if you need a special AIO module, then we can build
one for you or you can design your own. AIO modules are very small
boards at 1.45" x 2.0". The only part of the AIO module that is
specified is the mechanical design and the connectors to the FPGA. The
rest of the design including the external IO can be specified for your
application. 


-- 

Rick Collins

rick.collins@XYarius.com

remove the XY to email me.



Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX

Internet URL http://www.arius.com
Article: 22159
Subject: Re: Xilinx "length count" question
From: Rickman <spamgoeshere4@yahoo.com>
Date: Fri, 28 Apr 2000 01:42:29 -0400
Links: << >>  << T >>  << A >>
Kevin Klopfenstein wrote:
> 
> I'm trying to reconcile the length count and final address
> of a .mcs file generated by Xilinx's promgen tool.
> According to the datasheet for my Xilinx part (XC4020E),
> the PROM size requirement is 329,312 bits.  The last
> byte address of the .mcs file is 0xA0CC = 41164.  Multiplying
> that by 8 bits/byte yields the expected result, 329,312.
> 
> The length count field, however, works out to 329,305.  Here's
> the second line of my .mcs file:
> 
> :10000000FF040AA6F9EAFF7CFDF5D7DF6CF7DDD720
> 
> The command used to generate the file was
> 
> > promgen -s 512 -u 0 mydesign
> 
> It seems to me that the length count should match the PROM
> size, shouldn't it?  What am I missing?
> 
> Thanks,
> Kevin Klopfenstein
> Smiths Industries Aerospace

I don't know for sure that this is necessary. The bitstream is a bit
oriented format. Your MCS file is a byte oriented format. The actual
bitstream is 7 bits less than the file size. Since the bitstream is not
an exact multiple of 8 bits the last 7 bits in the file are padded with
ones. These extra bits have no effect when loading but are ignored in
the length count. 

Essentially, the FPGA stops loading data internally when the length
count is reached, but you still have more bits in your last byte. You
can load them or not, it won't matter to the part. 


-- 

Rick Collins

rick.collins@XYarius.com

remove the XY to email me.



Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX

Internet URL http://www.arius.com
Article: 22160
Subject: maxplus2 lpm in renoir
From: sduduma <sduduma@t2.technion.ac.il>
Date: Fri, 28 Apr 2000 08:58:43 +0300
Links: << >>  << T >>  << A >>
hi !

i need to use a fifo design in the renoir and i prefer to use a lpm but
i dont know how to use the maxplus2 lpms in the renoir.

thanks

yaniv chen
yaniv@elbit.co.il

Article: 22161
Subject: A Question on Virtex Configuration
From: "Ben" <ejhong@future.co.kr>
Date: Fri, 28 Apr 2000 06:36:34 GMT
Links: << >>  << T >>  << A >>
I'm using a virtex device, and now in the stage of configuring it. I've
tried JTAG boundary scan and Hardware Debugger with parallel download cable,
but both failed.

As for JTAG boundary scan, the integrity check was reported ok, and
programming was also done ok(at least it looked so), but verification
resulted in almost whole mismatch.
When I used Hardware Debugger, I ran into an error that says DONE doesn't go
high.
I have no clue about what's wrong with the configuration.

But surely I switched the M0, M1, M2 settings properly as I use JTAG and
Hardware Debugger.
The 3.3V power and ground seem okay, too.
And I used .bit file that was generated from Foundation project manager.

Somebody please tell me what I could do to get out of this pit!
TIA

Regards,

Ben


Article: 22162
Subject: [HELP] - Express Mode for XC5000
From: Nak <favardse@utc.fr>
Date: Fri, 28 Apr 2000 09:33:35 +0200
Links: << >>  << T >>  << A >>
Hi,

I must rapidely desigmed a small board for students activities. I want
use a XC5200 on a ISA board which could be configurate by the PC
computer.

I have two problems (software and hardware) :

The bitstream generated by the bitgen program on the Alliance package
could not generate a bitstream for the express mode (BITGEN: Xilinx
Bitstream Generator M1.5.19).
I must translate the bitstream file with :

1 - add a dummy byte before the bitsrtream to force the first clock
before the byte 0 ;
2 - inverse all bits (d0 at left and d7 at right !) ;
3 - add two Fill Byte at the end of the header ;
4 - remove the Preambule byte on the end of the bitstream.

Is-it correct for your ?


Secondly, how can i configurate the XC5200 ? I don't understand the
chronogram. :-( Could you help me to understand it in the power-on and
dynamicaly ? The problem for me is to correctly apply lewels on the
INIT/ and Program/ signals...


Thanks for all,


Seb

Article: 22163
Subject: Re: A Question on Virtex Configuration
From: "Peter Schulz" <p.schulz@signaal.de>
Date: Fri, 28 Apr 2000 09:50:55 +0200
Links: << >>  << T >>  << A >>
Did you select "JTAG Clock" for the Start-up Clock?
You can reach it through "Implementation
                                       -> Implementation Option
                                       -> Program Option Templates
                                       -> Congiguration, Edit Template
                                       -> Startup"
Regards

Peter


Ben schrieb in Nachricht ...
>I'm using a virtex device, and now in the stage of configuring it. I've
>tried JTAG boundary scan and Hardware Debugger with parallel download
cable,
>but both failed.
>
>As for JTAG boundary scan, the integrity check was reported ok, and
>programming was also done ok(at least it looked so), but verification
>resulted in almost whole mismatch.
>When I used Hardware Debugger, I ran into an error that says DONE doesn't
go
>high.
>I have no clue about what's wrong with the configuration.
>
>But surely I switched the M0, M1, M2 settings properly as I use JTAG and
>Hardware Debugger.
>The 3.3V power and ground seem okay, too.
>And I used .bit file that was generated from Foundation project manager.
>
>Somebody please tell me what I could do to get out of this pit!
>TIA
>
>Regards,
>
>Ben
>
>


Article: 22164
Subject: Re: A Question on Virtex Configuration
From: "Ben" <ejhong@future.co.kr>
Date: Fri, 28 Apr 2000 08:26:35 GMT
Links: << >>  << T >>  << A >>
Oops...no I didn't set start-up clock to JTAG clcok.

So I cleared the implementation, changed the option, and implemented again.
But the result is just same.

Peter Schulz 이(가) <8ebfsv$bug$1@ezri.addix.net> 메시지에서
작성하였습니다...
>Did you select "JTAG Clock" for the Start-up Clock?
>You can reach it through "Implementation
>                                       -> Implementation Option
>                                       -> Program Option Templates
>                                       -> Congiguration, Edit Template
>                                       -> Startup"
>Regards
>
>Peter


Article: 22165
Subject: DSP (FPGA) description
From: "Mrcio Longaray" <longaray@vortex.ufrgs.br>
Date: Fri, 28 Apr 2000 07:10:47 -0300
Links: << >>  << T >>  << A >>
Hi there!

Anyone know if I can find somwehere a vdhl description for a controller to
process mp3?
If yes, then where?

Thanks in advance.


Mrcio Longaray


Article: 22166
Subject: Re: Verilog Compiler ?
From: "JPC" <cachemi@cppm.in2p3.fr>
Date: Fri, 28 Apr 2000 13:56:08 +0200
Links: << >>  << T >>  << A >>
Anton,

You can use the SilosIII compiler and simulator.
They have a demo working with some limitations  that you can download at the
following address :
http://www.simucad.com/Demo/
I have tried it : it works fine.

Jean-Pierre


Anton Erasmus a crit dans le message <3908b6ae.9769433@news.mweb.co.za>...
>Hi,
>
>I Have done some simple EPLD designs in AHDL, but I want to start to
>use Verilog and/or VHDL. Unfortuanetly the Free License version of
>Alteras Max+Plus II does not support Verilog and VHDL. Is there a free
>Compiler which I can use to test Compile simple Verilog and maybe
>simulate ?
>
>Regards
>   Anton Erasmus
>


Article: 22167
Subject: xilinx prom 2nd source.
From: "giuseppe" <g.triani@usa.net>
Date: Fri, 28 Apr 2000 14:56:07 +0200
Links: << >>  << T >>  << A >>
Could anyone suggest an alternative to XC17128/256 serial Prom?
thanks to everyone.

Giuseppe.


Article: 22168
Subject: Re: DSP (FPGA) description
From: "Craig Slorach" <craigs@elec.gla.ac.uk>
Date: Fri, 28 Apr 2000 15:13:35 +0100
Links: << >>  << T >>  << A >>
Check out the Xilinx web site- there is a neat design in their app's section
for an MP3 system- though it does use an external IC to do all the decoding,
though may prove a good starting place.

> Anyone know if I can find somwehere a vdhl description for a controller to
> process mp3?
> If yes, then where?



Article: 22169
Subject: Re: A Question on Virtex Configuration
From: Tom Fischaber <tom.fischaber@xilinx.com>
Date: Fri, 28 Apr 2000 08:24:43 -0600
Links: << >>  << T >>  << A >>
In the 2.1i software, JTAG Verification is not supported. Thus, if you are
getting mismatches, this does not mean that the device is not configured.   If
you are programming through JTAG, you will want to make sure that the startup
clk is jtagclk, as mentioned before.  Also, you will want to make sure that the
disable Readback option is not selected, otherwise it will error that DONE did
not go high.  Once the JTAG Programmer has stated that configuration has
completed, is the DONE pin actually high on the device?  If so, then the device
is configured correctly.  Also, you will want to make sure that you are running
the latest Service Pack, available at
http://www.xilinx.com/support/techsup/sw_updates/

For Hardware Debugger programming, I assume that the mode pins are set to slave
serial?  There are no special bitgen options that need to be set (just make sure
that startup clk is CCLK again).  Also, are INIT and DONE pulled up externally?
For additional troubleshooting hints, you can refer to the Configuration Problem
Solver at http://support.xilinx.com --> Troubleshoot --> Configuration Problem
Solver

Tom Fischaber
Xilinx Customer Applications

Ben wrote:

> I'm using a virtex device, and now in the stage of configuring it. I've
> tried JTAG boundary scan and Hardware Debugger with parallel download cable,
> but both failed.
>
> As for JTAG boundary scan, the integrity check was reported ok, and
> programming was also done ok(at least it looked so), but verification
> resulted in almost whole mismatch.
> When I used Hardware Debugger, I ran into an error that says DONE doesn't go
> high.
> I have no clue about what's wrong with the configuration.
>
> But surely I switched the M0, M1, M2 settings properly as I use JTAG and
> Hardware Debugger.
> The 3.3V power and ground seem okay, too.
> And I used .bit file that was generated from Foundation project manager.
>
> Somebody please tell me what I could do to get out of this pit!
> TIA
>
> Regards,
>
> Ben

Article: 22170
Subject: Re: xilinx prom 2nd source.
From: felix_bertram@my-deja.com
Date: Fri, 28 Apr 2000 14:50:53 GMT
Links: << >>  << T >>  << A >>
Guiseppe,

what about Atmels EEPROMs (17LV512)?
This is not a real 2nd source replacement
as programming and pinout are a bit different,
but works just fine with our SpartanXL design.

Best regards

Felix

In article <8ec1ge$237$1@fe2.cs.interbusiness.it>,
  "giuseppe" <g.triani@usa.net> wrote:
> Could anyone suggest an alternative to XC17128/256 serial Prom?
> thanks to everyone.
>
> Giuseppe.
>
>


Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 22171
Subject: Re: xilinx prom 2nd source.
From: Greg Neff <gregneff@my-deja.com>
Date: Fri, 28 Apr 2000 15:05:05 GMT
Links: << >>  << T >>  << A >>
In article <8ec8g5$v49$1@nnrp1.deja.com>,
  felix_bertram@my-deja.com wrote:
> Guiseppe,
>
> what about Atmels EEPROMs (17LV512)?
> This is not a real 2nd source replacement
> as programming and pinout are a bit different,
> but works just fine with our SpartanXL design.
>
> Best regards
>
> Felix
>
> In article <8ec1ge$237$1@fe2.cs.interbusiness.it>,
>   "giuseppe" <g.triani@usa.net> wrote:
> > Could anyone suggest an alternative to XC17128/256 serial Prom?
> > thanks to everyone.
> >
> > Giuseppe.
> >
> >
>
> Sent via Deja.com http://www.deja.com/
> Before you buy.
>

The Atmel 17C series is 5V, the Atmel 17LV series is 3.3V.  One nice
thing about the Atmel parts is that they are reprogrammable, which is
handy during development.

--
Greg Neff
VP Engineering
*Microsym* Computers Inc.
greg@guesswhichwordgoeshere.com


Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 22172
Subject: Re: FPGA price vs Size
From: Tim Forcer <tmf@ecs.soton.ac.uk.nojunk>
Date: Fri, 28 Apr 2000 16:54:09 +0100
Links: << >>  << T >>  << A >>
Peter Alfke wrote:
> 
> For a mature, high-yielding product family, the die
> cost is essentially proportional to die area.  Therefore,
> the price will, to the first approximation, be proportional to
> area, i.e. number of CLBs.  ...
> 
> There are two important additional modifiers:
> At the low end, the relatively higher package cost often 
> results in a disproportionally higher price.
> At the high end, especially with a young family, the
> lower yield of the biggest chips ( suffering most from
> the defect density on the wafer) makes
> them overproportionally expensive.
> 
>  ...

Ah, if only it were that simple.

Several additional points.

The newer TECHNOLOGY silicon can be much cheaper (partly because die
area is lower, because fab standards have moved on), so Xilinx 3V/3.3V
parts are often much cheaper than 5V equivalents.

Package type can have an enormous influence on cost, far outweighing die
size.

Pin count will affect cost - go for the smallest number of pins
consistent with design needs.  Exact relationship between pins and
pounds (or dollars) depends on package type.  Some package styles are
easier to bond out than others, so their per-pin cost isn't so
significant in the overall equation.

Unless you are going for large quantities, actual costs will be
influenced by "pack size".  Many FPGAs are shipped in pre-packaged
containers.  The number per pack depends on package type and size.  Many
distributors will not split packs - if only because of the resultant
hassle of maintaining dry atmosphere of the part-packs.

For various reasons, I've recently had to buy XC4013s in pin grid array
(223 pins).  For slowest speed grade 5V parts I've paid almost 250 GBP
(including VAT) each.  That's US$ 400 each.  I could have cut the cost
by at least 60% and possibly 80% if I'd been able to use the cheapest
surface-mount package and 3.3V silicon.

-- 
Tim Forcer               tmf@ecs.soton.ac.uk
The University of Southampton, UK

The University is not responsible for my opinions
Article: 22173
Subject: Re: xilinx prom 2nd source.
From: Theron Hicks <hicksthe@egr.msu.edu>
Date: Fri, 28 Apr 2000 12:05:18 -0400
Links: << >>  << T >>  << A >>


Greg Neff wrote:

> In article <8ec8g5$v49$1@nnrp1.deja.com>,
>   felix_bertram@my-deja.com wrote:
> > Guiseppe,
> >
> > what about Atmels EEPROMs (17LV512)?
> > This is not a real 2nd source replacement
> > as programming and pinout are a bit different,
> > but works just fine with our SpartanXL design.
> >
> > Best regards
> >
> > Felix
> >
> > In article <8ec1ge$237$1@fe2.cs.interbusiness.it>,
> >   "giuseppe" <g.triani@usa.net> wrote:
> > > Could anyone suggest an alternative to XC17128/256 serial Prom?
> > > thanks to everyone.
> > >
> > > Giuseppe.
> > >
> > >
> >
> > Sent via Deja.com http://www.deja.com/
> > Before you buy.
> >
>
> The Atmel 17C series is 5V, the Atmel 17LV series is 3.3V.  One nice
> thing about the Atmel parts is that they are reprogrammable, which is
> handy during development.
>
> --
> Greg Neff
> VP Engineering
> *Microsym* Computers Inc.
> greg@guesswhichwordgoeshere.com
>
> Sent via Deja.com http://www.deja.com/
> Before you buy.

I have also used the atmel 17LV65 series to program a SpartanXL (XL05
device to be exact.)  No problem.  They are reprogrammable and appear to
be both somewhat more available and CHEAPER.

Article: 22174
Subject: Re: A Question on Virtex Configuration
From: "Ben" <ejhong@future.co.kr>
Date: Fri, 28 Apr 2000 16:24:34 GMT
Links: << >>  << T >>  << A >>

Tom Fischaber 이(가) <39099F2B.9D0A0540@xilinx.com> 메시지에서
작성하였습니다...
>In the 2.1i software, JTAG Verification is not supported. Thus, if you are
>getting mismatches, this does not mean that the device is not configured.

You are right. Before I installed service pack, verification was a possible
choice of operations. But after installation, it is not.

>If you are programming through JTAG, you will want to make sure that the
startup
>clk is jtagclk, as mentioned before.

Yes, this was proved to be necessary, too!

>Also, you will want to make sure that you are running
>the latest Service Pack, available at
>http://www.xilinx.com/support/techsup/sw_updates/

The software update really mattered.




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