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Messages from 22175

Article: 22175
Subject: Re: [HELP] - Express Mode for XC5000
From: Rickman <spamgoeshere4@yahoo.com>
Date: Fri, 28 Apr 2000 12:58:53 -0400
Links: << >>  << T >>  << A >>
Nak wrote:
> 
> Hi,
> 
> I must rapidely desigmed a small board for students activities. I want
> use a XC5200 on a ISA board which could be configurate by the PC
> computer.
> 
> I have two problems (software and hardware) :
> 
> The bitstream generated by the bitgen program on the Alliance package
> could not generate a bitstream for the express mode (BITGEN: Xilinx
> Bitstream Generator M1.5.19).
> I must translate the bitstream file with :
> 
> 1 - add a dummy byte before the bitsrtream to force the first clock
> before the byte 0 ;
> 2 - inverse all bits (d0 at left and d7 at right !) ;
> 3 - add two Fill Byte at the end of the header ;
> 4 - remove the Preambule byte on the end of the bitstream.
> 
> Is-it correct for your ?
> 
> Secondly, how can i configurate the XC5200 ? I don't understand the
> chronogram. :-( Could you help me to understand it in the power-on and
> dynamicaly ? The problem for me is to correctly apply lewels on the
> INIT/ and Program/ signals...
> 
> Thanks for all,
> 
> Seb

I am not familiar with the express mode, but you don't have to swap the
bits in software unless you have already made your hardware. If you are
designing your own, you might just want to swap the bits in hardware.
This is just a convention used in the documentation and has no bearing
on your designs in the FPGA. 

I recently did a design where I parallel loaded FPGAs and I connected my
FPGA to the bus with these 8 bits already swapped. This made debugging
much simpler since I could see the data on the bus in the same format as
the file. In fact I stored the bit file directly into the flash memory
with the header intact so that the file names and dates were stored with
it giving accurate information about the version. 




-- 

Rick Collins

rick.collins@XYarius.com

remove the XY to email me.



Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX

Internet URL http://www.arius.com
Article: 22176
Subject: which Conference Calendars on the web .... (FPL 2000)
From: Reiner Hartenstein <hartenst@rhrk.uni-kl.de>
Date: Fri, 28 Apr 2000 19:26:31 +0200
Links: << >>  << T >>  << A >>

Please, tell me, which conference' calendar(s) on the web you know:

URL: _________________________________________

URL: _________________________________________

Thank you!
Reiner Hartenstein


Article: 22177
Subject: Initial DFF value for Virtex in VHDL
From: Steven Derrien <sderrien@irisa.fr>
Date: Fri, 28 Apr 2000 19:48:23 +0200
Links: << >>  << T >>  << A >>
Hello,

I'd like to have a regsietr in my design initialized to a certain value
without the need for a Reset signal, is there any way to specify a
register initial value in VHDL for foundation express ?

Thanks

Steven



Article: 22178
Subject: Re: Instantiating and Compiling Altera LPM Macros with Synplify
From: David Bishop <dbishop@vhdl.org>
Date: Fri, 28 Apr 2000 14:58:20 -0400
Links: << >>  << T >>  << A >>
Nestor wrote:
> 
> Hi.
> 
> Has anyone ever tried to instantiate Altera lpm components in VHDL for
> synthesis in synplify with place and route in Maxplus2.
> 
> I will be using the black_box attribute in VHDL, but I am not clear on
> what I need to do in Maxplus2 to generate the required component.  I
> would like as much as possible to have Maxplus2 automatically create
> the macro function I would like to use (lpm_rom, for instance), based
> on generics that I will specify in my VHDL code, i.e., the ROM
> filename (MIF file) and the data widths.   Is this possible, or do I
> need to manually create the macro in Maxplus2 using the wizard every
> time I need a new ROM?

Synplicity can actually understand the Altera LPMs used by Maxplus2,
as long as it's JUST the lpms.

First off, in Maxplus2 land, the wizard "need some work".  If you want
a ROM, use "genmem".  It's an older tool, but it works consistantly
for the Flex10K parts.  Just type "genmem -help" and it will tell you
what it needs.  You still need to generate a MIF file, and feed that
to the "LPM_FILE" generic.

-- 
David W. Bishop           INTERNET: dbishop@vhdl.org            (  \  )
US MAIL:  Hilton NY 14468-9101      A Long time ago,             \__\/
PHYSICAL: 43:17:17N 77:47:37W 281'  In a Galaxy far, far away...  | |
For Supernova info:  http://www.ggw.org/asras/snimages            | |
For VHDL/Synthesis info:  http://www.vhdl.org/siwg              _/___\_
All standard disclaimers apply.                                [_______]
Article: 22179
Subject: Re: Interface with Altera's LPM_RAM_IO && Multiple cycle instruction
From: David Bishop <dbishop@vhdl.org>
Date: Fri, 28 Apr 2000 15:09:46 -0400
Links: << >>  << T >>  << A >>
MK Yap wrote:

> > > I'm writing VHDL codes using synplify (5.3.1) to interface with
> > Altera's
> > > LPM-RAM_IO (single IO port RAM)....    I'm using Max+Plus2 9.3, device
> > > Flek10k100e

I hit the same thing.

Basic problem. There is no single port ram in the Flex 10Ke parts.

Use a dual port ram and the problem will disappear.

-- 
David W. Bishop           INTERNET: dbishop@vhdl.org            (  \  )
US MAIL:  Hilton NY 14468-9101      A Long time ago,             \__\/
PHYSICAL: 43:17:17N 77:47:37W 281'  In a Galaxy far, far away...  | |
For Supernova info:  http://www.ggw.org/asras/snimages            | |
For VHDL/Synthesis info:  http://www.vhdl.org/siwg              _/___\_
All standard disclaimers apply.                                [_______]
Article: 22180
Subject: Re: How to Prevent theft of FPGA design
From: David Bishop <dbishop@vhdl.org>
Date: Fri, 28 Apr 2000 15:23:07 -0400
Links: << >>  << T >>  << A >>
Dan wrote:
> 
> I design Xilinx FPGA based circuit boards.
> 
> Some of my customers in the past have copied and manufactured my boards to
> avoid buying them from me.
> 
> How can I design my circuit boards to vastly reduce the chances of them
> being copied. The main problem is the Xilinx bitstream is easy to copy.

This is a basic problem that I've brought up to Xilinx.  ANYTHING you
put into an FPGA, anybody who wants to can copy.

Sometimes you can just make it tough to do, one game I've played is to
download the parts via a micro.  The Virtex parts are "partially programmable".
Thus you get a basic interface working, load the new programming data
into the memory of the board and reprogram it.  You can still reverse
engineer it, but it's much harder than copying the prom.

They've talked about adding some encoding logic on the bit stream, but
they haven't done anything about it.

-- 
David W. Bishop           INTERNET: dbishop@vhdl.org            (  \  )
US MAIL:  Hilton NY 14468-9101      A Long time ago,             \__\/
PHYSICAL: 43:17:17N 77:47:37W 281'  In a Galaxy far, far away...  | |
For Supernova info:  http://www.ggw.org/asras/snimages            | |
For VHDL/Synthesis info:  http://www.vhdl.org/siwg              _/___\_
All standard disclaimers apply.                                [_______]
Article: 22181
Subject: Re: Quartus "clock skew excedes data delay" error
From: David Bishop <dbishop@vhdl.org>
Date: Fri, 28 Apr 2000 15:29:31 -0400
Links: << >>  << T >>  << A >>
qaz wrote:
> 
> Has anyone else experienced the "clock skew excedes data delay"
> error" reported by Quartus? If so, has anyone found a way around
> it WITHOUT utilizing an on chip PLL? How? Apparently the problem
> exists in the timing analyzer software, not in the actual
> silicon.

Yup.  Hit it today.

To make it work, find out what the parameter "inclock_period" is in
your code.  Then setup the first edge of your clock to be at
"inclock_period/2" ps from the start of your simulation.  My Altera AE
is reporting this as a bug.

-- 
David W. Bishop           INTERNET: dbishop@vhdl.org            (  \  )
US MAIL:  Hilton NY 14468-9101      A Long time ago,             \__\/
PHYSICAL: 43:17:17N 77:47:37W 281'  In a Galaxy far, far away...  | |
For Supernova info:  http://www.ggw.org/asras/snimages            | |
For VHDL/Synthesis info:  http://www.vhdl.org/siwg              _/___\_
All standard disclaimers apply.                                [_______]
Article: 22182
Subject: Why are there no "cheap" FPGAs?
From: z80@ds2.com (Peter)
Date: Sat, 29 Apr 2000 08:03:25 +0000
Links: << >>  << T >>  << A >>

Xilinx are busy churning out devices with billions of gates, and the
cost per gate is certainly falling.

But they don't seem to do something for say $2 - at the same cost per
gate this should yield a few thousand gates, for the cost of a low
power 22V10.

I know Xilinx etc are growing and doing well, but the fact remains
that only a very tiny proportion of today's products actually contains
an FPGA. Far more designs use a PLD somewhere, with some ordinary
logic as well.

A few years ago I met a large direct Xilinx user who said he was
getting the XC3020 for $4.50 on a 50k/year quantity - so low prices
are possible but only in vast quantities, and such prices would never
be officially mentioned.


Peter.
--
Return address is invalid to help stop junk mail.
E-mail replies to zX80@digiYserve.com but remove the X and the Y.
Please do NOT copy usenet posts to email - it is NOT necessary.
Article: 22183
Subject: Re: [HELP] - Express Mode for XC5000
From: Nak <favardse@utc.fr>
Date: Sat, 29 Apr 2000 10:27:58 +0200
Links: << >>  << T >>  << A >>
Rickman,

Yes its not necessary to swap all bits if the data bus hardware is already
swapping. But for the bistream format, I have read that this mode in not
supported by the BitGen program.

So must I add a dummy byte to start the upload of the bitsream like the
chronograms specs ?
Can I replace in the header, the Fill Byte with 3 Fill Bytes ? or can I
replace the length count and the fill byte per 3 fill byte ?

The Data book is not really explicite for me... (poor french man with very
very poor english notion :-) )

"The configuration data stream begins with a string of eight ones, a
preambule code, followed by a 24-bit length count and a separator field of
ones (or 24 fill bits, in Express mode)"

(p7-107)

To finish, I must remove the Postambule byte in the end of the bitstream
and eventually add 5 dummy byte to force the complete configuration of the
FPGA.

"An additional five CCLKs will guarantee completion of configuration"

(p 7-106)


So after the bitstream problem, how can I do my state machine to support
the power on and reconfiguration process.
I don't understand how I must use the Program/ and Init/ signals.

Perhaps the function is similar at the others modes ? How I must apply a
good sequence on these lines ? In fact O don't understand WHEN I must apply
levels on theses signals and WHEN the FPGA uses them 8-( ...


Thanks for all,

Seb


Article: 22184
Subject: Re: How to Prevent theft of FPGA design
From: Rickman <spamgoeshere4@yahoo.com>
Date: Sun, 30 Apr 2000 10:05:36 -0400
Links: << >>  << T >>  << A >>
Dan wrote:
> 
> I design Xilinx FPGA based circuit boards.
> 
> Some of my customers in the past have copied and manufactured my boards to
> avoid buying them from me.
> 
> How can I design my circuit boards to vastly reduce the chances of them
> being copied. The main problem is the Xilinx bitstream is easy to copy.
> 
> Thanks Dan

I have looked at a similar problem having to do with protecting software
on my hardware. But it comes down to the same thing. You need to key the
software/FPGAware to the board itself with a serial number of some kind. 

The way I am looking at doing this is to use one of the "one-wire"
serial number parts from Dallas Semiconductor. These parts contain a 48
bit serial number that is guaranteed to be unique. You can use one pin
on the FPGA to communicate with these parts. They can also contain PROM
and EEPROM. So this provides all the elements of preventing your
hardware from being copied or software being run on unauthorized
hardware. 

The protection scheme will require that a one way process be developed
that you can implement in the FPGA to allow a key to be "compared" to
the serial number. The key can be stored in the "one-wire" part for the
FPGA to selfload, or in software to be loaded into the FPGA. The FPGA
could be designed so that major functionality is disabled until the
correct key is loaded. 

The trick here is in developing the algorithm that can be used in the
FPGA without using tons of resources. To properly protect yourself, I
believe you would have to assume that this could be reverse engineered
so the algorithm should not be considered secret. Instead, there needs
to be many combinations of valid keys with a single serial number and
have the FPGA only work with one. This may end up being a three way key. 

This would work somewhat like a public key encryption algorithm. The
serial number would be readily read, the key could also be read. So the
third part that controls how they are validated would have to contain a
"secret" number. Since this "secret number" could also be read if enough
effort is put into it, there should be a different "secret number" for
each FPGA design or customer. 

I believe the only way to circomvent this protection scheme is to either
reverse engineer the FPGA design to "fix" the hardware disable, or to
design a copy of the "one-wire" chip with the serial number that matches
the FPGA. Both of these are likely cost prohibitive for any one company. 

If anyone has an idea for an algorithm to implement this, please let me
know. 



-- 

Rick Collins

rick.collins@XYarius.com

remove the XY to email me.



Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX

Internet URL http://www.arius.com
Article: 22185
Subject: Re: Why are there no "cheap" FPGAs?
From: Rickman <spamgoeshere4@yahoo.com>
Date: Sun, 30 Apr 2000 10:46:42 -0400
Links: << >>  << T >>  << A >>
Peter wrote:
> 
> Xilinx are busy churning out devices with billions of gates, and the
> cost per gate is certainly falling.
> 
> But they don't seem to do something for say $2 - at the same cost per
> gate this should yield a few thousand gates, for the cost of a low
> power 22V10.
> 
> I know Xilinx etc are growing and doing well, but the fact remains
> that only a very tiny proportion of today's products actually contains
> an FPGA. Far more designs use a PLD somewhere, with some ordinary
> logic as well.
> 
> A few years ago I met a large direct Xilinx user who said he was
> getting the XC3020 for $4.50 on a 50k/year quantity - so low prices
> are possible but only in vast quantities, and such prices would never
> be officially mentioned.
> 
> Peter.
> --
> Return address is invalid to help stop junk mail.
> E-mail replies to zX80@digiYserve.com but remove the X and the Y.
> Please do NOT copy usenet posts to email - it is NOT necessary.

I can't tell you for sure why there are not very low cost FPGAs (<$4).
But at least part of the problem is the cost of the IOs. The smallest
package I have seen FPGAs in is 100 pins with the parts cost over $10 in
smaller quantities ~100. 

I would expect that there really is not much call for even low end FPGAs
in smaller packages. I personally would love to see some 64 PQFP parts.
Or I could use larger parts in the 100 PQFP package. But it would appear
that I am alone in that need. For the most part the demand for FPGAs is
at the high end with very large IO counts. Also it is a whole lot easier
to sell $1M worth of parts at $1000 apiece than when they are $10
apiece. 


-- 

Rick Collins

rick.collins@XYarius.com

remove the XY to email me.



Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX

Internet URL http://www.arius.com
Article: 22186
Subject: Help!
From: "George" <g_roberts75@hotmail.com>
Date: Sun, 30 Apr 2000 20:25:42 +0100
Links: << >>  << T >>  << A >>
Hi Folks,

I have a basic question to ask: I know that 2-D DCT does not take the phase
information of an image into account. FFT, however, does. Where is DCT used,
and where is FFT used? Am I true in thinking that Phase in Freq. domain
means delay in Time domain. So DCT works on stil images, whereas FFT works
on both stil and moving images. DCT is simpler to compute and thus more used
in still image compression... Is that true??

Any comment is much appraciated!

Cheers.




Article: 22187
Subject: Re: How to Prevent theft of FPGA design
From: "Joel Kolstad" <Joel.Kolstad@USA.Net>
Date: Sun, 30 Apr 2000 14:41:46 -0700
Links: << >>  << T >>  << A >>
"Rickman" <spamgoeshere4@yahoo.com> wrote in message
news:390C3DB0.B82F738D@yahoo.com...

> I believe the only way to circomvent this protection scheme is to either
> reverse engineer the FPGA design to "fix" the hardware disable, or to
> design a copy of the "one-wire" chip with the serial number that matches
> the FPGA. Both of these are likely cost prohibitive for any one company.

The first two are, but isn't emulating a Dallas serial ID chip something
some hacker could whip up in under a week?  I can just see someone replacing
your Dallas ID chip with a CPLD that acts just like it, but of course is
programmed with the one magic ID code necessary for the one genuined copy of
the board the hacker owns.  Since they're already going to the effort to
copy your board anyway, an additional week's worth of effort probably won't
discourage them much.  Of course, you could take the usual approaches to
making that all important data pin inaccessible, but you know what would
really help would be if Xilinx had unique serial numbers in each FPGA, like
Intel does with Pentiums these days.

I've also always liked the idea suggested here where the FPGA does the
decryption using a decryption key known only to Xilinx while providing
anybody who wants it with the public encryption key so that it's still easy
to generate bitstreams.

---Joel Kolstad



Article: 22188
Subject: Re: How to Prevent theft of FPGA design
From: nweaver@boom.CS.Berkeley.EDU (Nicholas C. Weaver)
Date: 30 Apr 2000 21:51:26 GMT
Links: << >>  << T >>  << A >>
In article <sgpa7umfo6q143@corp.supernews.com>,
Joel Kolstad <Joel.Kolstad@USA.Net> wrote:
>I've also always liked the idea suggested here where the FPGA does the
>decryption using a decryption key known only to Xilinx while providing
>anybody who wants it with the public encryption key so that it's still easy
>to generate bitstreams.

	Public key is probably not a viable solution.  A better
solution would be a burnable symmetric key.  The key could be written
once, and then used to decrypt a bitstream as it is loaded.  Unless
the hacker extracts the key (doable, but very difficult) from the
FPGA, they can't copy the bitfile.

	Also, the encryption hardware itself should implement whatever
the AES winner is, and be accessable from designs, allowing this
hardware to be used for efficient, high performance cryptography,
outside of the context of securing bitfiles.
-- 
Nicholas C. Weaver                                 nweaver@cs.berkeley.edu
Article: 22189
Subject: Re: How to Prevent theft of FPGA design
From: nweaver@boom.CS.Berkeley.EDU (Nicholas C. Weaver)
Date: 30 Apr 2000 23:08:18 GMT
Links: << >>  << T >>  << A >>
In article <390CB497.5B614794@yahoo.com>,
Rickman  <spamgoeshere4@yahoo.com> wrote:

>Using a public encryption key would still provide a copyable data
>stream. To make this work, you would have to have a programmable keyas
>Nick suggested. 
>
>The process of burning the key into the FPGA would add a step that would
>increase the cost and complexity of using the chips. Of course that is
>also true of using the one-wire parts. But Xilinx or other FPGA
>manufacturers don't want to add cost to every unit made for the benefit
>of a few critical designs. 

	Probably a better solution is to NOT burn the key into the
design at the factory, but to just have an EPROM or similar element
which can be written once.  However, this does add a processing step.

	Yet since there is also considerable call for a small amount
of accessable nonvolatise storage on the order of a few dozen words
(EG, MAC addresses, serial numbers), the cost of the additional steps
becomes more justifiable, because a larger set of customers would use
it.

	Similarly, the crypto engine itself, if it implements the AES
winner, would be highly useful, even for those who aren't using it to
encrypt the bitstream.  Since the winner will be a fixed design, of
ubiquitous use, this allows the silicon necessary to perform the
encryption to also be useful by a wide number of people for other
applications.

	The key when convincing the vendors to add such a feature
(support for encrypted bitstreams) is to show that the silicon and
steps they use to make this operation work are also useful to a wide
group of individuals.

Note:

	The AES program (Advanced Encryption Standard, see
http://csrc.nist.gov/encryption/aes/ for details) is the federal
government's process of choosing a replacement to DES.  The winner is
expected to be announced sometime this summer.  It is anticipated that
the winner will be the block cypher of choice, similarly to how for
many years, DES was the only block cypher commonly implemented.
-- 
Nicholas C. Weaver                                 nweaver@cs.berkeley.edu
Article: 22190
Subject: Re: How to Prevent theft of FPGA design
From: Rickman <spamgoeshere4@yahoo.com>
Date: Sun, 30 Apr 2000 18:32:55 -0500
Links: << >>  << T >>  << A >>
"Nicholas C. Weaver" wrote:
> 
> In article <sgpa7umfo6q143@corp.supernews.com>,
> Joel Kolstad <Joel.Kolstad@USA.Net> wrote:
> >I've also always liked the idea suggested here where the FPGA does the
> >decryption using a decryption key known only to Xilinx while providing
> >anybody who wants it with the public encryption key so that it's still easy
> >to generate bitstreams.
> 
>         Public key is probably not a viable solution.  A better
> solution would be a burnable symmetric key.  The key could be written
> once, and then used to decrypt a bitstream as it is loaded.  Unless
> the hacker extracts the key (doable, but very difficult) from the
> FPGA, they can't copy the bitfile.
> 
>         Also, the encryption hardware itself should implement whatever
> the AES winner is, and be accessable from designs, allowing this
> hardware to be used for efficient, high performance cryptography,
> outside of the context of securing bitfiles.
> --
> Nicholas C. Weaver                                 nweaver@cs.berkeley.edu


Using a public encryption key would still provide a copyable data
stream. To make this work, you would have to have a programmable keyas
Nick suggested. 

The process of burning the key into the FPGA would add a step that would
increase the cost and complexity of using the chips. Of course that is
also true of using the one-wire parts. But Xilinx or other FPGA
manufacturers don't want to add cost to every unit made for the benefit
of a few critical designs. 

In my design I already have a one-wire part on board and already program
it before shipping. So this method would not be a big variation from
what I am doing now. 

The process of copying a "one-wire" part is not as simple as you might
think. Any CPLD will use a much larger package and require a clock
input. So now the improper copying of the board will really be a reverse
engineering task and re-layout rather than a cloning operation. 


-- 

Rick Collins

rick.collins@XYarius.com

remove the XY to email me.



Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX

Internet URL http://www.arius.com
Article: 22191
Subject: Bi-dir pass-thru w/switch in MAX+Plus II?
From: Russ Magee <rmagee@home.com>
Date: Sun, 30 Apr 2000 23:35:13 GMT
Links: << >>  << T >>  << A >>
Hi there,

We're having trouble defining a bi-directional pass-through in the
MAX+Plus II (8.1) schematic editor. here's what we want:

              ENABLE---+
              logic    |
                       |
                   +--|>--+
                   |   |  |
<====>-------------+   |  +-----------------<====> 
                   |   |  |
                   +--<|--+

We just want the pins to function as bi-directional, open-collector pass
throughs UNLESS our internal logic decides to suppress the connection.

We can't seem to find a valid way to represent this in the schematic, as
hooking two bidir pins to each other (as above) has so far given us only
"Error: Node missing source:" messages.

What is the simplest way to implement this?

Thanks in advance,
-Russ Magee
Article: 22192
Subject: Re: ? economical SPROM programmer for Xilinx
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Mon, 01 May 2000 00:45:39 +0100
Links: << >>  << T >>  << A >>


Dan wrote:

> The Data IO programmers cost $1500ish to program Xilinx SPROM. Does anyone
> know of a more reasonably priced one ?
>
> Thanks Dan

If you're in smallish volume why not consider the reprogrammable 1800 series
devices from Xilinx. They are JTAG programmable. Once you've got the design
stable you could get your SPROM distributor to program one-time ones for you.

Alternatively avoid SPROMs altogether & use a standard EPROM+small CPLD to
generate the bit stream.


Article: 22193
Subject: Re: A Question on Virtex Configuration
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Mon, 01 May 2000 00:55:53 +0100
Links: << >>  << T >>  << A >>


Tom Fischaber wrote:

> In the 2.1i software, JTAG Verification is not supported. Thus, if you are

Do Xilinx ever intend to support for verification [and readback for Virtex devices]
to the  JTAG programmer ?

Its not like these functions are hidden since for Virtex parts all the required info
is in apps notes 138, 139, 151.

Article: 22194
Subject: Re: How to Prevent theft of FPGA design
From: Jim Granville <jim.granville@designtools.co.nz>
Date: Mon, 01 May 2000 12:02:16 +1200
Links: << >>  << T >>  << A >>
Rickman wrote:
> 
> The process of copying a "one-wire" part is not as simple as you might
> think. Any CPLD will use a much larger package and require a clock
> input. 

 Not if they use an 8 pin SMD device :-)
Current candidates are ACE1101 (TSSOP8), or ATtinyXX ( both ISP Flash )
The ACE1101 has 64 Bytes EEPROM, and could be coded to 
both record/replay any 1 wire ID.

> So now the improper copying of the board will really be a reverse
> engineering task and re-layout rather than a cloning operation.

 Any secure device on the PCB, will improve things, over a straight
Config-loader.
 Since a 1 wire pasrt is a response-only security device, it 
is exposed to simple stream-recording cracking schemes.

 Another level of protection is stimulus-response devices, also
called rolling code devices.

 There are other avenues you can take :-

 Use a small Loader iC ( uc or CPLD ). This effectively encrypts the 
bitstream, and requires reasonable cracking effort ( a FPGA capture
scheme )
 Such devices also allow lower cost SPI/i2c/DataFLASH devices, so can
cost
effectively 'nothing'.

 Use a small CPLD ( ATF750CL or similar ) that is secure, and has buried
registers. This can form a hard to crack stimulus/response combination
with
your FPGA, needing load time, and ideally, also run-time checking to see
that the 'key device' is valid.
 With any-clock capability, and up to 21 possible connections to the 
FPGA, hacking such a F750 scheme is very difficult - only you know 
'what matters when'. 
 A uC can also be used, if you can keep the speeds down.

 This very quickly moves beyond stream recording cracking, and the
hacker is
never 100% sure they have covered all combinations, more so if you can 
arrange lame-mode failures, rather than drop-dead ones.

- jg

-- 
======= 80x51 Tools & IP Specialists  =========
= Want to work smarter than C ?
= http://www.DesignTools.co.nz/modbench.htm
= http://www.DesignTools.co.nz

Article: 22195
Subject: Re: How to Prevent theft of FPGA design
From: "Joel Kolstad" <Joel.Kolstad@USA.Net>
Date: Sun, 30 Apr 2000 17:27:08 -0700
Links: << >>  << T >>  << A >>
"Rickman" <spamgoeshere4@yahoo.com> wrote in message
news:390CB497.5B614794@yahoo.com...
> The process of copying a "one-wire" part is not as simple as you might
> think. Any CPLD will use a much larger package and require a clock
> input. So now the improper copying of the board will really be a reverse
> engineering task and re-layout rather than a cloning operation.

Perhaps I overestimate the skills of the copy artists... :-)  If you sold
such a board commercially, and it was something like a cable TV descrambler,
I'd expect some hacker to have a little board that stood up vertically and
was tack soldered to where your Dallas chip used to be!

Nick definitely had the better approach to bitstream protection...

---Joel Kolstad



Article: 22196
Subject: real clock generation
From: dharmesh_halani@my-deja.com
Date: Mon, 01 May 2000 09:55:05 GMT
Links: << >>  << T >>  << A >>
Hi all,
       Clock generation for simulation, we have following way,
always
#delay clock <= ~clock;

       I would like to generate real clock. Is is possible?

-Dharmesh
(Sr. Engineer - VLSI group)
(einfochips inc.)


Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 22197
Subject: Re: Why are there no "cheap" FPGAs?
From: Theron Hicks <hicksthe@egr.msu.edu>
Date: Mon, 01 May 2000 09:03:52 -0400
Links: << >>  << T >>  << A >>


Rickman wrote:

> Peter wrote:
> >
> > Xilinx are busy churning out devices with billions of gates, and the
> > cost per gate is certainly falling.
> >
> > But they don't seem to do something for say $2 - at the same cost per
> > gate this should yield a few thousand gates, for the cost of a low
> > power 22V10.
> >
> > I know Xilinx etc are growing and doing well, but the fact remains
> > that only a very tiny proportion of today's products actually contains
> > an FPGA. Far more designs use a PLD somewhere, with some ordinary
> > logic as well.
> >
> > A few years ago I met a large direct Xilinx user who said he was
> > getting the XC3020 for $4.50 on a 50k/year quantity - so low prices
> > are possible but only in vast quantities, and such prices would never
> > be officially mentioned.
> >
> > Peter.
> > --
> > Return address is invalid to help stop junk mail.
> > E-mail replies to zX80@digiYserve.com but remove the X and the Y.
> > Please do NOT copy usenet posts to email - it is NOT necessary.
>
> I can't tell you for sure why there are not very low cost FPGAs (<$4).
> But at least part of the problem is the cost of the IOs. The smallest
> package I have seen FPGAs in is 100 pins with the parts cost over $10 in
> smaller quantities ~100.
>
> I would expect that there really is not much call for even low end FPGAs
> in smaller packages. I personally would love to see some 64 PQFP parts.
> Or I could use larger parts in the 100 PQFP package. But it would appear
> that I am alone in that need.

NO, you are not.  I agree whole heartedly.  The SpartanXL05 series in a
plcc84 is the closest for me (5K gates ~$10 each in small quantities).  I
would love a small Virtex-E series part (fast, with LVPECL I/O capability).
For that part I would probably be willing to pay as much as $30 or more.
(If it were fast enough.)



> For the most part the demand for FPGAs is
> at the high end with very large IO counts. Also it is a whole lot easier
> to sell $1M worth of parts at $1000 apiece than when they are $10
> apiece.
>
> --
>
> Rick Collins
>
> rick.collins@XYarius.com
>
> remove the XY to email me.
>
> Arius - A Signal Processing Solutions Company
> Specializing in DSP and FPGA design
>
> Arius
> 4 King Ave
> Frederick, MD 21701-3110
> 301-682-7772 Voice
> 301-682-7666 FAX
>
> Internet URL http://www.arius.com

Article: 22198
Subject: Re: Xilinx "length count" question
From: "Ed McCauley" <ed.mccauley@bltinc.com>
Date: Mon, 1 May 2000 09:46:07 -0400
Links: << >>  << T >>  << A >>
Hey Rick!

Kevin,

Rick is 100% correct.  Each FPGA knows how many bits it will need therefor,
excess bits are ignored.  When the required number of bits are received AND
the DONE pin is high (not externally held low), the device will continue
with its configuration state machine.

Why have a length count then?  Daisychain: The master device needs to know
how many bits to extract from PROM.  When daisychain mode, this will be more
than the master device itself will need.  Each device in the chain 'gobbles'
up the necessary data during daisychain config and then passes the excess on
to downstream devices.  When all have 'had their fill', and released their
DONE pins, they all finish configuration together.

Hope this helps.

--
Ed McCauley
President
Bottom Line Technologies Inc.
Specializing Exclusively in Xilinx Design, Development and Training
Voice: (908) 996-0817
FAX:   (908) 996-0787

See us on the Web at:
   The Bottom Line Technologies Home Page
      http://www.bltinc.com
   The Xilinx XPERTS - U.S Partners Page
      http://www.xilinx.com/company/consultants/us_consultants.htm
   The Programmable Logic Jump Station
      http://www.optimagic.com/consultants.html


Rickman <spamgoeshere4@yahoo.com> wrote in message
news:390924C5.D92E9E0F@yahoo.com...
> Kevin Klopfenstein wrote:
> >
> > I'm trying to reconcile the length count and final address
> > of a .mcs file generated by Xilinx's promgen tool.
> > According to the datasheet for my Xilinx part (XC4020E),
> > the PROM size requirement is 329,312 bits.  The last
> > byte address of the .mcs file is 0xA0CC = 41164.  Multiplying
> > that by 8 bits/byte yields the expected result, 329,312.
> >
> > The length count field, however, works out to 329,305.  Here's
> > the second line of my .mcs file:
> >
> > :10000000FF040AA6F9EAFF7CFDF5D7DF6CF7DDD720
> >
> > The command used to generate the file was
> >
> > > promgen -s 512 -u 0 mydesign
> >
> > It seems to me that the length count should match the PROM
> > size, shouldn't it?  What am I missing?
> >
> > Thanks,
> > Kevin Klopfenstein
> > Smiths Industries Aerospace
>
> I don't know for sure that this is necessary. The bitstream is a bit
> oriented format. Your MCS file is a byte oriented format. The actual
> bitstream is 7 bits less than the file size. Since the bitstream is not
> an exact multiple of 8 bits the last 7 bits in the file are padded with
> ones. These extra bits have no effect when loading but are ignored in
> the length count.
>
> Essentially, the FPGA stops loading data internally when the length
> count is reached, but you still have more bits in your last byte. You
> can load them or not, it won't matter to the part.
>
>
> --
>
> Rick Collins
>
> rick.collins@XYarius.com
>
> remove the XY to email me.
>
>
>
> Arius - A Signal Processing Solutions Company
> Specializing in DSP and FPGA design
>
> Arius
> 4 King Ave
> Frederick, MD 21701-3110
> 301-682-7772 Voice
> 301-682-7666 FAX
>
> Internet URL http://www.arius.com


Article: 22199
Subject: Xilinx CPLD Make file
From: "VIRMAN" <w.cherry@virinc.com>
Date: Mon, 1 May 2000 10:42:11 -0400
Links: << >>  << T >>  << A >>
Hi;

    Does anyone know if there is a "make" file in cpld implementation for
xilinx similar to "C".  The reason i ask is i have a cpld design that is
used on six different projects and the only thing that changes between these
projects is a board ID register in the xilinx.  I wanted to know about
"make" files because i was wondering if i would be able to compile the cpld
design six different ways instead of having six different projects that each
need to be compiled.  This will make maintenance of the design easier in the
future, because i will only need to change one schematic and comile it six
ways instead of changing six schematics and compiling each.
    Any info will be helpfull.

thanks
wes




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