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Messages from 22200

Article: 22200
Subject: Re: Initial DFF value for Virtex in VHDL
From: "Jamie Sanderson" <jamie@nortelnetworks.com>
Date: Mon, 1 May 2000 11:02:53 -0400
Links: << >>  << T >>  << A >>
I'm not using Foundation, but in other tools, the DFF value assigned on
asynchronous reset is also the initial value when it completes the
configuration phase. At least, that's what I've observed using Synplify with
Xilinx 4000 and Virtex FPGA's. The down side of this solution is that you'd
need to create a reset signal which you don't plan on using.

Cheers,
Jamie

"Steven Derrien" <sderrien@irisa.fr> wrote in message
news:3909CEE7.706C8F50@irisa.fr...
> Hello,
>
> I'd like to have a regsietr in my design initialized to a certain value
> without the need for a Reset signal, is there any way to specify a
> register initial value in VHDL for foundation express ?
>
> Thanks
>
> Steven



Article: 22201
Subject: Re: Xilinx CPLD Make file
From: "Mark Harvey" <mark.harvey@iol.it>
Date: Mon, 01 May 2000 15:46:34 GMT
Links: << >>  << T >>  << A >>
Try the "Running Foundation from a Makefile" document which is available
from http://www.xess.com/fndmake.pdf - also see example at
http://www.xess.com/fndmake.zip


Mark Harvey.



VIRMAN <w.cherry@virinc.com> wrote in message
news:sgr5rg67oog90@corp.supernews.com...
> Hi;
>
>     Does anyone know if there is a "make" file in cpld implementation for
> xilinx similar to "C".  The reason i ask is i have a cpld design that is
> used on six different projects and the only thing that changes between
these
> projects is a board ID register in the xilinx.  I wanted to know about
> "make" files because i was wondering if i would be able to compile the
cpld
> design six different ways instead of having six different projects that
each
> need to be compiled.  This will make maintenance of the design easier in
the
> future, because i will only need to change one schematic and comile it six
> ways instead of changing six schematics and compiling each.
>     Any info will be helpfull.
>
> thanks
> wes
>
>


Article: 22202
Subject: Re: Xilinx CPLD Make file
From: Dave Vanden Bout <devb@xess.com>
Date: Mon, 01 May 2000 12:11:53 -0400
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.
--------------26ED620143389CD6EB2443FB
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

Just a small correction if you are using Foundation 2.1: you will need to remove the call to hprep6 in the makefile since that program doesn't exist anymore.  No other changes are needed as far as I can tell.


Mark Harvey wrote:

> Try the "Running Foundation from a Makefile" document which is available
> from http://www.xess.com/fndmake.pdf - also see example at
> http://www.xess.com/fndmake.zip
>
> Mark Harvey.
>
> VIRMAN <w.cherry@virinc.com> wrote in message
> news:sgr5rg67oog90@corp.supernews.com...
> > Hi;
> >
> >     Does anyone know if there is a "make" file in cpld implementation for
> > xilinx similar to "C".  The reason i ask is i have a cpld design that is
> > used on six different projects and the only thing that changes between
> these
> > projects is a board ID register in the xilinx.  I wanted to know about
> > "make" files because i was wondering if i would be able to compile the
> cpld
> > design six different ways instead of having six different projects that
> each
> > need to be compiled.  This will make maintenance of the design easier in
> the
> > future, because i will only need to change one schematic and comile it six
> > ways instead of changing six schematics and compiling each.
> >     Any info will be helpfull.
> >
> > thanks
> > wes
> >
> >

--
|| Dr. Dave Van den Bout   XESS Corp.               (919) 387-0076 ||
|| devb@xess.com           2608 Sweetgum Dr.        (800) 549-9377 ||
|| http://www.xess.com     Apex, NC 27502 USA   FAX:(919) 387-1302 ||


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--------------26ED620143389CD6EB2443FB--

Article: 22203
Subject: PR: XESS Introduces Low-Cost Triscend CSoC Development Kit
From: Dave Vanden Bout <devb@xess.com>
Date: Mon, 01 May 2000 12:16:55 -0400
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.
--------------9159360DC3B6ECD932DC9517
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

This is shortened press-release about the new myCSoC Kit from XESS Corp.  You can get more information by following the links from http://www.xess.com.



XESS Introduces Low-Cost Triscend CSoC Development Kit for the Education Market

Apex, NC - May 1, 2000 - XESS Corp. announces the availability of its
myCSoC Kit which supports hardware and software development with
Triscend Configurable System-on-Chip (CSoC) devices.  While this
low-cost kit was designed for the educational market, it is also
a general-purpose development tool for applications in communications,
multimedia, and consumer electronics.

The Kit includes a copy of the FastChip development software,
a CDROM tutorial on designing with CSoC devices, a prototyping board
with a TE505 CSoC, a power supply and a downloading cable.  The tutorial
shows how the FastChip software is used to configure the TE505's
embedded programmable logic into peripheral functions that cooperate
with the integrated 8032 microcontroller core.  Each example design
can be downloaded into 1-Mb of Flash or SRAM on the prototyping board
and tested at speeds up to 25 MHz.    The board has 80 general-purpose
I/O pins for connections to external devices as well as connectors for
a keyboard/mouse and a VGA monitor.

The myCSoC Kit will be available in mid-May for $169.95 from
XESS Corporation (www.xess.com / 800-549-9377).

                              # # #

Notes:

XESS and myCSoC Kit are trademarks of XESS Corp.  Triscend, E5,
FastChip, and Configurable System-on-Chip for Communications are
trademarks of Triscend Corporation. All other products and brands
are the property of their respective holders.


--
|| Dr. Dave Van den Bout   XESS Corp.               (919) 387-0076 ||
|| devb@xess.com           2608 Sweetgum Dr.        (800) 549-9377 ||
|| http://www.xess.com     Apex, NC 27502 USA   FAX:(919) 387-1302 ||


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--------------9159360DC3B6ECD932DC9517--

Article: 22204
Subject: Re: Why are there no "cheap" FPGAs?
From: Peter Alfke <peter@xilinx.com>
Date: Mon, 01 May 2000 12:06:50 -0700
Links: << >>  << T >>  << A >>
Well, this newsgroup is supposed to be technical, not commercial.
But (the other) Peter asked the question, and here is the answer:

As of May 2000 you can buy an XC2S15 in quantity 1 through 24 for $ 7.10
:

You get 96 CLBs, i.e 384 LUT / flip-flop combinations ( Logic Cells )
plus four dual-ported BlockRAMs, each 4096 bits
plus four DLLs
plus 60 I/Os with lots of options.

That's less than 2 cents per flip-flop plus associated logic,
with 16K bits of RAM and four DLLs thrown in for free.

We just finished the design of a 256-deep, 16-wide FIFO with independent
read and write clocks running >100 MHz, that uses only half the memory
plus 10% of the CLBs on this chip.

"This is not your father's XC3020 anymore..."

Peter Alfke
========================
Peter wrote:

> Xilinx are busy churning out devices with billions of gates, and the
> cost per gate is certainly falling.
>
> But they don't seem to do something for say $2 - at the same cost per
> gate this should yield a few thousand gates, for the cost of a low
> power 22V10.
>
> I know Xilinx etc are growing and doing well, but the fact remains
> that only a very tiny proportion of today's products actually contains
> an FPGA. Far more designs use a PLD somewhere, with some ordinary
> logic as well.
>
> A few years ago I met a large direct Xilinx user who said he was
> getting the XC3020 for $4.50 on a 50k/year quantity - so low prices
> are possible but only in vast quantities, and such prices would never
> be officially mentioned.
>
> Peter.
> --
> Return address is invalid to help stop junk mail.
> E-mail replies to zX80@digiYserve.com but remove the X and the Y.
> Please do NOT copy usenet posts to email - it is NOT necessary.

Article: 22205
Subject: Verilog FAQ
From: rajesh52@hotmail.com
Date: Mon, 01 May 2000 19:13:12 GMT
Links: << >>  << T >>  << A >>
Greetings
 This is semimonthly announcement of Verilog FAQ.

 Verilog FAQ is located at
 http://www.angelfire.com/in/verilogfaq/

 Alternate Verilog FAQ is an attempt to gather the answers
 to most Frequently Asked Questions about Verilog HDL in
 one place. It also  contains list of publications, services,
 and products.

 Alternate Verilog FAQ is divided into three logical parts.

 Part 1 : Introduction and misc. questions
 Part 2 : Technical Topics
 Part 3 : Tools and Services

 What's New section outlines the changes in different versions
 and announcements. Links connects you to related
 informative
 links in internet.

 Your suggestions to make this FAQ more informative are
 welcome.

 Rajesh Bawankule
 (Also Visit Verilog Center :
 http://www.angelfire.com/in/rajesh52/verilog.html )


Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 22206
Subject: Re: Verilog Compiler ?
From: Christian Mautner <at@utanet.cmautner>
Date: 01 May 2000 21:21:11 +0200
Links: << >>  << T >>  << A >>
antera@mweb.co.za (Anton Erasmus) writes:

> Hi,
> 
> I Have done some simple EPLD designs in AHDL, but I want to start to
> use Verilog and/or VHDL. Unfortuanetly the Free License version of
> Alteras Max+Plus II does not support Verilog and VHDL. Is there a free
> Compiler which I can use to test Compile simple Verilog and maybe
> simulate ? 

Have you been to www.altera.com recently? If I understand them
correctly, they will give away FPGA express and/or another synthesis
tool (in a special OEM version) for free (starting in some weeks).

chm.

-- 
cmautner@  -  Christian Mautner
utanet.at  -  Vienna/Austria/Europe

Article: 22207
Subject: Re: Why are there no "cheap" FPGAs?
From: Ray Andraka <randraka@ids.net>
Date: Mon, 01 May 2000 19:45:54 GMT
Links: << >>  << T >>  << A >>
The XCV50E-6CS144C is $33.25 in single quantities on Avnet.  Seems this is
preety close to what you want, no?

Theron Hicks wrote:

> Rickman wrote:
>
> > Peter wrote:
>
> ... I would love a small Virtex-E series part (fast, with LVPECL I/O
> capability).
> For that part I would probably be willing to pay as much as $30 or more.
> (If it were fast enough.)

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 22208
Subject: Xilinx Applications Engineer
From: Vern Dunbrack <dunbrack@xilinx.com>
Date: Mon, 01 May 2000 15:51:56 -0400
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.
--------------84101979D6C45B8D8BA1037A
Content-Type: multipart/alternative;
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--------------71B3C82BC58701BCA1A5FF7F
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Hello All,

Our Design Center in Nashua NH is expanding and currently has one
opening for a Applications Engineer. If anyone is interested in the
position please contact me directly.

Thanks,
Vern
Email : dunbrack@xilinx.com
Phone : (603)891-1096 x15

Job Title: Applications Engineer


Job Responsibilities:       Responsible for providing support for Xilinx
Field Sales in the Boston market with design win activities, by
providing technical support for strategic customers including Design
Reviews, HDL code optimization, point solution IP generation and running
the Xilinx place and route software. Other activities include working
closely with the field and factory to analyze and solve strategic
customer problems, creation of application notes, reference designs,
training modules and become an expert in all aspects of Xilinx
architectures and software.


Job Requirements:   BSEE or MSEE with 5+ years of experience in FPGA or
ASIC design. Looking for candidates with experience in high-speed design
techniques with logic design experience using Verilog/VHDL languages and
a high level of experience with synthesis tools. Experience should
include FPGA, system and board level design responsibilities in:
Networking, Telecommunications, Wireless Communications and/or Embedded
System Designs.


--------------71B3C82BC58701BCA1A5FF7F
Content-Type: text/html; charset=us-ascii
Content-Transfer-Encoding: 7bit

<!doctype html public "-//w3c//dtd html 4.0 transitional//en">
<html>
Hello All,
<p>Our Design Center in Nashua NH is expanding and currently has one opening
for a Applications Engineer. If anyone is interested in the position please
contact me directly.
<p>Thanks,
<br>Vern
<br>Email : dunbrack@xilinx.com
<br>Phone : (603)891-1096 x15<b></b>
<p><b>Job Title: </b>Applications Engineer
<br>&nbsp;
<p><b>Job Responsibilities:&nbsp;&nbsp;</b>&nbsp;&nbsp;&nbsp;&nbsp; Responsible
for providing support for Xilinx Field Sales in the Boston market with
design win activities, by providing technical support for strategic customers
including Design Reviews, HDL code optimization, point solution IP generation
and running the Xilinx place and route software. Other activities include
working closely with the field and factory to analyze and solve strategic
customer problems, creation of application notes, reference designs, training
modules and become an expert in all aspects of Xilinx architectures and
software.
<br>&nbsp;
<p><b>Job Requirements:&nbsp;</b>&nbsp; BSEE or MSEE with 5+ years of experience
in FPGA or ASIC design. Looking for candidates with experience in high-speed
design techniques with logic design experience using Verilog/VHDL languages
and a high level of experience with synthesis tools. Experience should
include FPGA, system and board level design responsibilities in: Networking,
Telecommunications, Wireless Communications and/or Embedded System Designs.
<br>&nbsp;</html>

--------------71B3C82BC58701BCA1A5FF7F--

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--------------84101979D6C45B8D8BA1037A--

Article: 22209
Subject: Re: Instantiating and Compiling Altera LPM Macros with Synplify
From: nestor@stansync.com (Nestor)
Date: Mon, 01 May 2000 20:06:48 GMT
Links: << >>  << T >>  << A >>
Thanks for your reply David.

I have finally succeeded in instantiating the lpm_rom module in VHDL
as a black box in Synplify following some guidelines, that I found by
accident on the Altera site as I was searching for something else.

When you say that Synplify can actually undestand the Altera LPM, do
you mean that it is able to generate and edif netlist without the need
to pass through the Maxplus2?  If so, this would be great for my
design since I could then bypass the Maxplus2 tool and perform some
functional simulations.  If that is is what you mean, could you please
outline briefly what I need to do in synplify to achieve this.  So far
I have been stuck compiling the entire netlist downto to the fpga
level before I could any type of 3rd party simulation, and the only
kind at this level is timing.  I know from experience that xilinx
allows the user to quickly compile a design into a single netlist
(which may include a combination of VHDL and CoreGEN modules), which
can later be imported into a 3rd party simulation tool for functional
simulation, before placing and routing the design.


On Fri, 28 Apr 2000 14:58:20 -0400, David Bishop <dbishop@vhdl.org>
wrote:

>
>Synplicity can actually understand the Altera LPMs used by Maxplus2,
>as long as it's JUST the lpms.
>
>First off, in Maxplus2 land, the wizard "need some work".  If you want
>a ROM, use "genmem".  It's an older tool, but it works consistantly
>for the Flex10K parts.  Just type "genmem -help" and it will tell you
>what it needs.  You still need to generate a MIF file, and feed that
>to the "LPM_FILE" generic.

Article: 22210
Subject: Re: Xilinx CPLD Make file
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Tue, 02 May 2000 00:51:09 +0100
Links: << >>  << T >>  << A >>


Dave Vanden Bout wrote:

> Just a small correction if you are using Foundation 2.1: you will need to remove the call to hprep6 in the makefile since that program doesn't exist anymore.  No other changes are needed as far as I can tell.

You mean ``hplusas6'' don't you. hprep6 is the essential thing that actually generates the JEDEC file for CPLDs.

Also I find it useful in my make file to have general suffix based rules of the form:

.v.edn:
     <Run your Verilog synth tool here>
.edn.ngd:
    ngdbuild ....

for CPLDs you might then have something like

.ngd.jed:
    hitop ...
    hprep6 ...

These can then be kept in a common file & included in the project makefiles. That way your build chain is always the same for the same class of device.

One thing that would make this easier for CPLDs would a description somewhere of the command line options to hitop & hprep6. I've decoded the hprep ones, does anyone know the hitop ones ?


Article: 22211
Subject: Re: Instantiating and Compiling Altera LPM Macros with Synplify
From: David Bishop <dbishop@vhdl.org>
Date: Tue, 02 May 2000 02:28:46 GMT
Links: << >>  << T >>  << A >>


Nestor wrote:
> 
> Thanks for your reply David.
> 
> I have finally succeeded in instantiating the lpm_rom module in VHDL
> as a black box in Synplify following some guidelines, that I found by
> accident on the Altera site as I was searching for something else.

Yes, the Altera and Xilinx web sites are very useful.  I wouldn't want
to tackel one of these big FPGAs without web access these days.  That is
once you get over all of the bugs in their examples.

> When you say that Synplify can actually undestand the Altera LPM, do
> you mean that it is able to generate and edif netlist without the need
> to pass through the Maxplus2?  If so, this would be great for my
> design since I could then bypass the Maxplus2 tool and perform some
> functional simulations.  If that is is what you mean, could you please
> outline briefly what I need to do in synplify to achieve this.  So far
> I have been stuck compiling the entire netlist downto to the fpga
> level before I could any type of 3rd party simulation, and the only
> kind at this level is timing.

Synplicity has the Altera lpm library built into it.  Thus, when you
say "library lpm" it knows what you mean.  Maxplus2 will find the
correct
file (tdf?) along it's default search path.

> I know from experience that xilinx
> allows the user to quickly compile a design into a single netlist
> (which may include a combination of VHDL and CoreGEN modules), which
> can later be imported into a 3rd party simulation tool for functional
> simulation, before placing and routing the design.

"quickly" is a relative term. M2.1i_sp6 can run for days.
However, when you run "ngd2vhdl" remember to set the switches, they
can make your life debugging your design alot easier.

-- 
NAME:     David W. Bishop           INTERNET: dbishop@vhdl.org  (  \  )
US MAIL:  Hilton NY 14468-9101      A Long time ago,             \__\/
PHYSICAL: 43:17:17N 77:47:37W 281'  In a Galaxy far, far away...  | |
For Supernova info:  http://www.ggw.org/asras/snimages            | |
For VHDL/Synthesis info:  http://www.vhdl.org/siwg              _/___\_
All standard disclaimers apply.                                [_______]

Article: 22212
Subject: test
From: "Kelvin Law" <Kelvin.Law@amd.com>
Date: 2 May 2000 02:43:55 GMT
Links: << >>  << T >>  << A >>
testing

Article: 22213
Subject: Re: FPGA price vs Size
From: kayrock@geocities.com
Date: Tue, 02 May 2000 04:40:14 GMT
Links: << >>  << T >>  << A >>
In article <3909B421.60E@ecs.soton.ac.uk.nojunk>,
  Tim Forcer <tmf@ecs.soton.ac.uk.nojunk> wrote:
> Peter Alfke wrote:
> >
> > For a mature, high-yielding product family, the die
> > cost is essentially proportional to die area.  Therefore,
> > the price will, to the first approximation, be proportional to
> > area, i.e. number of CLBs.  ...
> >
> > There are two important additional modifiers:
> > At the low end, the relatively higher package cost often
> > results in a disproportionally higher price.
> > At the high end, especially with a young family, the
> > lower yield of the biggest chips ( suffering most from
> > the defect density on the wafer) makes
> > them overproportionally expensive.
> >
> >  ...
>
> Ah, if only it were that simple.
>
> Several additional points.
>
> The newer TECHNOLOGY silicon can be much cheaper (partly because die
> area is lower, because fab standards have moved on), so Xilinx 3V/3.3V
> parts are often much cheaper than 5V equivalents.
>
> Package type can have an enormous influence on cost, far outweighing
die
> size.
>
> Pin count will affect cost - go for the smallest number of pins
> consistent with design needs.  Exact relationship between pins and
> pounds (or dollars) depends on package type.  Some package styles are
> easier to bond out than others, so their per-pin cost isn't so
> significant in the overall equation.
>
> Unless you are going for large quantities, actual costs will be
> influenced by "pack size".  Many FPGAs are shipped in pre-packaged
> containers.  The number per pack depends on package type and size.
Many
> distributors will not split packs - if only because of the resultant
> hassle of maintaining dry atmosphere of the part-packs.
>
> For various reasons, I've recently had to buy XC4013s in pin grid
array
> (223 pins).  For slowest speed grade 5V parts I've paid almost 250 GBP
> (including VAT) each.  That's US$ 400 each.  I could have cut the cost
> by at least 60% and possibly 80% if I'd been able to use the cheapest
> surface-mount package and 3.3V silicon.
>
> --
> Tim Forcer               tmf@ecs.soton.ac.uk
> The University of Southampton, UK
>
> The University is not responsible for my opinions
>

Another issue that has a dramatic effect on pricing, and one that us
technical types ofter ignore is the market effects.  The cost of
production says what the margin will be and the viability of that
product but doesn't set the selling price.  When a new product line is
introducted, they are fighting for new designs and are more willing to
compromise on price to get a foot in the door.  A mature product line
has already been designed into products, and further price reductions
may only serve to reduce profits.  A good way to handle this is design
the PCB to take competing parts.  This allows you to play both ends
against the middle.  Okay, my 2 bits.

Josh



Sent via Deja.com http://www.deja.com/
Before you buy.

Article: 22214
Subject: new2fpga
From: "R. T. Finch" <robfinch@cyg.net>
Date: Tue, 2 May 2000 02:17:10 -0400
Links: << >>  << T >>  << A >>
Hi, I'm new to fpga designs. I'd like to experiment with some (at home) (I
am not new to dabbling in electronics, I've built several small computers)
a) Should I bother looking at pre-constructed systems such as offered by
Xess ? Or should I just go ahead and purchase the parts ? b) where can I get
parts in single quantities ? I like to use parts with a moderate number of
I/O's available say 100. c) How do you use quad flat packs "at home" (This
seems to be a popular packaging method) ? Do you solder very carefully ? Is
there some sort of "extender boards" to allow the parts to be reused ?

Thanx
Rob



Article: 22215
Subject: random integer
From: Jamil Khatib <jamilkhatib75@yahoo.com>
Date: Tue, 02 May 2000 08:32:51 +0200
Links: << >>  << T >>  << A >>
Hi,
Is there any simple method to generate random numbers "integers not
bits" that are constrained to a specific range?

Thanks in advance

Jamil Khatib

Article: 22216
Subject: L.E,G.A,L C,A.B,L.E T,V D,E-S,C.R,A.M,B.L,E.R............. 3277
From: mlzfgl@4r5g6hv5.net
Date: Tue, 02 May 2000 07:51:45 GMT
Links: << >>  << T >>  << A >>
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Article: 22217
Subject: Re: How to Prevent theft of FPGA design
From: Andreas Doering <doering@iti.mu-luebeck.de>
Date: Tue, 02 May 2000 12:09:59 +0200
Links: << >>  << T >>  << A >>
Why not try to make things mechanical difficult. 
If you put your FPGA and the configuration EPROM into 
resin, that is  this epoxy stuff, it is already very hard 
to get down to the contacts to measure. 
This method is rather convenient for harsh environments
thus there are service providers that will do that cheaply.
Another step further would be a multi-chip-module. 
AFAIK xilinx will sell you naked chips for wire bond 
usage if the amount is not too small. 
This also saves board space :-).
Andreas
-----------------------------------------------------------------
                        Andreas C. Doering
                        Medizinische Universitaet zu Luebeck
                        Institut fuer Technische Informatik
 		        Tel.: +49 451 500-3741, Fax: -3687
		        Email: doering@iti.mu-luebeck.de
"The fear of the LORD is the beginning of ... science" (Proverbs 1.7)
----------------------------------------------------------------

Article: 22218
Subject: Re: A Question on Virtex Configuration
From: "Daryl Bradley" <dwb105@nospam.ohm.york.ac.uk>
Date: Tue, 2 May 2000 11:54:24 +0100
Links: << >>  << T >>  << A >>
I may stand to be corrected, so tell me if I'm wrong as I'll be interested
to know the solution, but as far as I am aware from looking through the
xilinx support, the parallel cable (parallel cable iii dcl5?) does not
support readback adn so you can't debug with this cable.




Ben <ejhong@future.co.kr> wrote in message
news:%WbO4.259$mw2.4725@news2.bora.net...
> Oops...no I didn't set start-up clock to JTAG clcok.
>
> So I cleared the implementation, changed the option, and implemented
again.
> But the result is just same.
>
> Peter Schulz 이(가) <8ebfsv$bug$1@ezri.addix.net> 메시지에서
> 작성하였습니다...
> >Did you select "JTAG Clock" for the Start-up Clock?
> >You can reach it through "Implementation
> >                                       -> Implementation Option
> >                                       -> Program Option Templates
> >                                       -> Congiguration, Edit Template
> >                                       -> Startup"
> >Regards
> >
> >Peter
>
>


Article: 22219
Subject: Re: maxplus2 lpm in renoir
From: antonin@my-deja.com
Date: Tue, 02 May 2000 12:39:05 GMT
Links: << >>  << T >>  << A >>
In article <39092892.BEFF2B6E@t2.technion.ac.il>,
  sduduma <sduduma@t2.technion.ac.il> wrote:
> hi !
>
> i need to use a fifo design in the renoir and i prefer to use a lpm
but
> i dont know how to use the maxplus2 lpms in the renoir.
>
> thanks
>
> yaniv chen
> yaniv@elbit.co.il

In Renoir create a new library call LPM_ALTERA
(the name isn't important but it coudn't be LPM because Renoir has
already a LPM library)
Then do a "convert hdl to graphic" and take the file
\maxplus2\lpmsim\220model.vhd
(I recomend that you keep the VHDL format and doesn't allow Renoir to
extract state machine or flow chart)
That's it you have the Altera LPM library that is more complete than the
one you will find in Renoir.

Regards


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Article: 22220
Subject: Re: random integer
From: gazit@my-deja.com
Date: Tue, 02 May 2000 13:26:54 GMT
Links: << >>  << T >>  << A >>
You can use LFSR (Linear phase shift register) to generate pseudo
random series of numbers.
Each LFSR generates one "random" bit (zero or one) every clock cycle.
If you use n LFSRs The range of your random number is 0 - 2^(n-1).
For more details about LFSR implementation refer to xapp052 @
www.xilinx.com

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Rotem Gazit
MystiCom  LTD.
mailto:rotemg@mysticom.com  http://www.mysticom.com
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In article <390E7693.ED98DE3D@yahoo.com>,
  khatib@ieee.org wrote:
> Hi,
> Is there any simple method to generate random numbers "integers not
> bits" that are constrained to a specific range?
>
> Thanks in advance
>
> Jamil Khatib
>
>


Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 22221
Subject: Re: Verilog Compiler ?
From: "Nikolay Rognlien" <nikolayr@acte.no>
Date: Tue, 2 May 2000 15:28:56 +0200
Links: << >>  << T >>  << A >>
The free Max+plusII software does support VHDL and Verilog design entry.
You have to choose the "E+Max" license instead of "Baseline" to obtain it.

-Nikolay


Anton Erasmus <antera@mweb.co.za> wrote in message
news:3908b6ae.9769433@news.mweb.co.za...
> Hi,
>
> I Have done some simple EPLD designs in AHDL, but I want to start to
> use Verilog and/or VHDL. Unfortuanetly the Free License version of
> Alteras Max+Plus II does not support Verilog and VHDL. Is there a free
> Compiler which I can use to test Compile simple Verilog and maybe
> simulate ?
>
> Regards
>    Anton Erasmus
>


Article: 22222
Subject: Re: which Conference Calendars on the web .... (FPL 2000)
From: Daniel Kroening <kroening@handshake.de>
Date: Tue, 02 May 2000 15:42:19 +0200
Links: << >>  << T >>  << A >>
Hello,

Reiner Hartenstein wrote:

> Please, tell me, which conference' calendar(s) on the web you know:
> 
> URL: _________________________________________
> 
> URL: _________________________________________

http://www.kroening.com/conferences/conferences.html

-- 
Daniel Kroening

Article: 22223
Subject: Re: Why are there no "cheap" FPGAs?
From: Theron Hicks <hicksthe@egr.msu.edu>
Date: Tue, 02 May 2000 10:14:16 -0400
Links: << >>  << T >>  << A >>


Ray Andraka wrote:

> The XCV50E-6CS144C is $33.25 in single quantities on Avnet.  Seems this is
> preety close to what you want, no?
>

Close, but not quite close enough.  I need something I can hand solder for
prototype and small production runs.  I prefer a 84 pin plcc but if I were
desperate I might try a VQFP or even a TQFP type package.  Unless you have a
suggestion for handling a ball chip package I am afraid I will have to stick
with what I have.

Thanks for the suggestion anyway.

>
> Theron Hicks wrote:
>
> > Rickman wrote:
> >
> > > Peter wrote:
> >
> > ... I would love a small Virtex-E series part (fast, with LVPECL I/O
> > capability).
> > For that part I would probably be willing to pay as much as $30 or more.
> > (If it were fast enough.)
>
> --
> -Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930     Fax 401/884-7950
> email randraka@ids.net
> http://users.ids.net/~randraka

Article: 22224
Subject: VDHL and ASIC people
From: The ATM man <shawnNOshSPAM@whitridge.com.invalid>
Date: Tue, 02 May 2000 07:29:27 -0700
Links: << >>  << T >>  << A >>
First, If anybody is offended that I put this out here, let
me know and it will cease. Second, I realize that there are
a number of great VHDL and ASIC people out there. Some
might be looking for new positions and some not. I know you
do not like me calling you at work, and I can understand
that. What would you suggest is the best way to speak with
you about new positions I have just received?


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