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Messages from 22675

Article: 22675
Subject: Re: Best choice between FPGA and CPLD
From: Chris Shenton <chriss@px.uk.com>
Date: Wed, 17 May 2000 14:10:01 +0100
Links: << >>  << T >>  << A >>
CPLD's tend to allow wider product term functions per logic level than FPGA's.

This usually means that you can do faster wide decoders in a CPLD.

Cheers

Chris

Simon Bilodeau wrote:

> Hi i'm quite new in FPGA and CPLD world.
>
> I have to design a board with address decoding and a few event counters (16
> bit counters) interfaced with an PC104 bus.
>
> Is it better to use CPLD or FPGA? Why?
>
> Thanks
>
> Simon

Article: 22676
Subject: macros for reuse
From: Vipan Kakkar <v.kakkar@its.tudelft.nl>
Date: Wed, 17 May 2000 15:13:23 +0200
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.
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Hi:

I am working with XC4000 series and alliance software. I have saved the mapped

files as macros (without running the placement and routing).

My question is: how to make and use a library of these macros so that these can be instantiated

in the top level design. So, we can put all the synthesized modules (macros)

in the top level module (vhdl) without a need for resynthesizing them.

Regards

Vipan



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<pre>Hi:</pre>

<pre>I am working with XC4000 series and alliance software. I have saved the mapped</pre>

<pre>files as macros (without running the placement and routing).</pre>

<pre></pre>

<pre>My question is: how to make and use a library of these macros so that these can be instantiated</pre>

<pre>in the top level design. So, we can put all the synthesized modules (macros)</pre>

<pre>in the top level module (vhdl) without a need for resynthesizing them.</pre>

<pre></pre>

<pre>Regards</pre>

<pre>Vipan</pre>
&nbsp;</html>

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Article: 22677
Subject: Re: SMT 7 segment display ??
From: "Russ.Shaw" <russell@webaxs.net>
Date: Wed, 17 May 2000 23:33:44 +1000
Links: << >>  << T >>  << A >>
Thats called 'burning in a prom' :)


Spehro Pefhany wrote:
> 
> In sci.electronics.design Tim Shoppa <shoppa@trailing-edge.com> wrote:
> 
> > Wow, you mean if I pump enough current through some of those pins
> > that the GAL16V8 will visibly glow?  Cool!
> 
> Maybe if it's one of the ones with the quartz window you could make a
> digit with the glowing bonding wires? I don't think the shape is right
> though.

-- 
*******************************************
*   Russell Shaw, B.Eng, M.Eng(Research)  *
*   Electronics Consultant                *
*      email: russell@webaxs.net          *
*      Australia                          *
*******************************************
Article: 22678
Subject: Re: PC104+ FPGA Board
From: Rick Collins <spamgoeshere3@yahoo.com>
Date: Wed, 17 May 2000 09:58:52 -0400
Links: << >>  << T >>  << A >>
I don't think you will find many PC/104+ boards at all. This is a fairly new
extension to the PC/104 spec and it is a little difficult to implement due to
space constraints. The PC/104+ connector takes up additional space on the board
and the PCI bus interface chip takes up even more. So you severely limit the
amount of circuitry you can use by adding the PCI capability to a PC/104 board.

How many boards do you think you will need? If the quantity is sufficient, I am
sure that someone will work with you to add such a board to their product line.



Jean-Luc Nagel wrote:

> "James T. White" wrote:
>
> > Check out Associated Professional Systems (http://www.associatedpro.com).
>
> Thank you for your answers.
>
> Unfortunately they have only PC104 boards and no PC104+...

Rick Collins

rick.collins@XYarius.com

remove the XY to email me.



Arius, Inc - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX

Internet URL http://www.arius.com




Article: 22679
Subject: Re: Best choice between FPGA and CPLD
From: "Simon Bilodeau" <simon.bilodeau@htrc.com>
Date: Wed, 17 May 2000 10:21:42 -0400
Links: << >>  << T >>  << A >>
What do you mean by FF?



Simon Bilodeau <simon.bilodeau@htrc.com> a écrit dans le message :
9qhU4.91$3F3.1719@wagner.videotron.net...
> Hi i'm quite new in FPGA and CPLD world.
>
> I have to design a board with address decoding and a few event counters
(16
> bit counters) interfaced with an PC104 bus.
>
> Is it better to use CPLD or FPGA? Why?
>
> Thanks
>
>
> Simon
>
>
>


Article: 22680
Subject: Re: Best choice between FPGA and CPLD
From: "Andy Peters" <apeters.Nospam@nospam.noao.edu.nospam>
Date: Wed, 17 May 2000 09:30:52 -0700
Links: << >>  << T >>  << A >>
Simon Bilodeau wrote in message ...
>What do you mean by FF?

Flip-flop.


-- a
-----------------------------------------
Andy Peters
Sr Electrical Engineer
National Optical Astronomy Observatories
950 N Cherry Ave
Tucson, AZ 85719
apeters (at) noao \dot\ edu

"A sufficiently advanced technology is indistinguishable from magic"
     --Arthur C. Clarke



Article: 22681
Subject: FPL 2000 - Roadmap to Reconfigurable Systems
From: "hartenst@rhrk.uni-kl.de" <hartenst@rhrk.uni-kl.de>
Date: Wed, 17 May 2000 19:26:12 +0200
Links: << >>  << T >>  << A >>
10th International Conference
on Field-Programmable Logic
and Applications

August 28 - 30, 2000
Villach Austria

the advance programme is ready for inspection:

http://xputers.informatik.uni-kl.de/FPL/fpl2000/Program/FPLStart.html

 
Best regards,
Reiner Hartenstein
Program Chair
Article: 22682
Subject: Xilinx USB Multilinx download verrrrrrry slow
From: "Alun" <alun101@DELETEtesco.net>
Date: Wed, 17 May 2000 20:10:28 +0100
Links: << >>  << T >>  << A >>
We are getting a JTAG clock of about 30kHz with a Multilinx running on USB
from a Win98 laptop.
It's consistent. Xilinx say it shouldn't happen.
We tried the serial link and that gives a 5kHz JTAG clock.

Any clues?

ta
Alun


Article: 22683
Subject: Re: Xilinx USB Multilinx download verrrrrrry slow
From: "Alun" <alun101@DELETEtesco.net>
Date: Wed, 17 May 2000 20:17:34 +0100
Links: << >>  << T >>  << A >>
Before you ask, we're using a Virtex 1000BG560 on a prototyping card made by
ARM.

Alun

Alun <alun101@DELETEtesco.net> wrote in message
news:C2CU4.2311$86.38711@news2-win.server.ntlworld.com...
> We are getting a JTAG clock of about 30kHz with a Multilinx running on USB
> from a Win98 laptop.
> It's consistent. Xilinx say it shouldn't happen.
> We tried the serial link and that gives a 5kHz JTAG clock.
>
> Any clues?
>
> ta
> Alun
>
>


Article: 22684
Subject: Spartan II availability and pricing
From: ldoolitt@recycle (Larry Doolittle)
Date: 17 May 2000 20:00:13 GMT
Links: << >>  << T >>  << A >>
I'm resurrecting an old thread, because Avnet and Insight
now have reasonable prices listed for the Spartan-II chips.

The two distributors agree to the penny wherever they overlap,
so I assume these are Xilinx sanctioned prices in US$ for
small quantities as of May 16, 2000:

            TQ144C   PQ208C   FG256C   FG456C
XC2S50-5    $12.85   $14.75   $16.65
XC2S100-5   $17.60   $19.55   $24.65   $31.00
XC2S150-5            $21.60   $27.00   $35.10

These are a _lot_ lower than a month ago, even lower than
I predicted.  I thought they would be more sensitive to their
Virtex customers (Virtex prices haven't dropped, an XCV100
is still generally above $100).  Maybe they think most Virtex
customers have become addicted to the larger sizes available
in that line.

The remaining question is availability.  Those distributors
don't claim stock ("Please call").  Does anyone here know
the real scoop?  If not, I'll try to get something out of
Insight.

I have updated http://recycle.lbl.gov/xc2search.html with this
info.

      - Larry Doolittle   <LRDoolittle@lbl.gov>
Article: 22685
Subject: Re: SMT 7 segment display ??
From: z80@ds1.com (Peter)
Date: Wed, 17 May 2000 22:49:37 +0000
Links: << >>  << T >>  << A >>
>
>www.flint.co.uk

"Specialist" SMT disti with "specialist" pricing :)


Peter.
--
Return address is invalid to help stop junk mail.
E-mail replies to zX80@digiYserve.com but remove the X and the Y.
Please do NOT copy usenet posts to email - it is NOT necessary.
Article: 22686
Subject: Re: Spartan II availability and pricing
From: Ray Andraka <ray@andraka.com>
Date: Wed, 17 May 2000 23:03:56 GMT
Links: << >>  << T >>  << A >>
I'm looking for a small quantity of XC2S50-5FG256C for a prototype
build.  I need them for June 1st.   We had some on order, they were
supposed to be in a few weeks ago but now the date is pushed back.  If
anyone knows where I can get about a dozen right quick, please email me.

Larry Doolittle wrote:

> I'm resurrecting an old thread, because Avnet and Insight
> now have reasonable prices listed for the Spartan-II chips.
>
> The two distributors agree to the penny wherever they overlap,
> so I assume these are Xilinx sanctioned prices in US$ for
> small quantities as of May 16, 2000:
>
>             TQ144C   PQ208C   FG256C   FG456C
> XC2S50-5    $12.85   $14.75   $16.65
> XC2S100-5   $17.60   $19.55   $24.65   $31.00
> XC2S150-5            $21.60   $27.00   $35.10
>
> These are a _lot_ lower than a month ago, even lower than
> I predicted.  I thought they would be more sensitive to their
> Virtex customers (Virtex prices haven't dropped, an XCV100
> is still generally above $100).  Maybe they think most Virtex
> customers have become addicted to the larger sizes available
> in that line.
>
> The remaining question is availability.  Those distributors
> don't claim stock ("Please call").  Does anyone here know
> the real scoop?  If not, I'll try to get something out of
> Insight.
>
> I have updated http://recycle.lbl.gov/xc2search.html with this
> info.
>
>       - Larry Doolittle   <LRDoolittle@lbl.gov>

--
P.S.  Please note the new email address and website url

-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com  or http://www.fpga-guru.com


Article: 22687
Subject: Re: Spartan II availability and pricing
From: Rick Collins <spamgoeshere3@yahoo.com>
Date: Wed, 17 May 2000 20:35:16 -0400
Links: << >>  << T >>  << A >>
Ray,

I am looking at using the FG packages on a new board and I am not sure how
easy they are to use. I have used the BG256 package  before and the layout
ended up with a number of vias in between the pads that pushed my PCB design
rules down to 5 mil trace and 5 mil space. This ended up costing me a lot
more to get the PCBs made.

The FG256 and FG456 packages use an even smaller pin pitch. In addition, the
FG256 has no space in the center to place vias and the FG456 is not much
better.

How are you laying out your boards to use these parts? Are you going to 5/5
or smaller design rules on the PCB?

I am currently using the Lucent Orca parts because they provide a lot of IO
in a given package. When Xilinx went to the Virtex parts, they dramatically
cut down on the available IO counts. The Spartan II parts are even worse.
e.g. the XC4020 in a BG256 package gives 205 IOs. The Virtex part gives 180
IOs. The Spartan II only has 176 in the FG256. Any idea why?

To convert my current design over to Xilinx parts, I would have to move two
smaller parts from VQ100 packages to the TQ144 package to compensate for the
loss of IOs. Then to regain board space, I have to combine my large part
(currently a BG256 with 221 IOs) with a third smaller part and use an FG456
package. But I had enough trouble getting the BGA laidout and mounted that I
really don't want to go to a finer pitch part and run up the cost of the
PCB.

The design is modular so I can't combine all of the parts into one package.
My preferece is to have one large part with about 220 IOs and three smaller
parts with about 75 IOs. But this won't fit on the board with the Spartan
IIs unless I go with the fine pitch or chip scale packages.

Another problem is the multiple Vcc voltages that are showing up on the
board. The board will be powered from 5V and will have a small number of 5V
parts. An on board switcher provides 3.3V for the DSP IOs, memory, etc. The
DSP needs 1.8V and now the Spartan II/Virtex parts need 2.5V. That's 4 power
voltages on a PC/104 board! I really don't know what to do with that. The
1.8V is only 100 mA or so, but I expect the 3 or 4 FPGAs will need a lot
more current than that from the 2.5V supply so I would need a second
switcher on board. The Virtex E parts are out because I need 5V
compatibility on almost 100 pins. Xilinx says you can have a Virtex E pin as
input or output on a 5V signal, but they don't show you how to do a
bidirectional path.

If I stick with the older technology 3.3V FPGAs from Xilinx, I have to pay a
lot more for the same number of gates.

Any ideas?


Ray Andraka wrote:

> I'm looking for a small quantity of XC2S50-5FG256C for a prototype
> build.  I need them for June 1st.   We had some on order, they were
> supposed to be in a few weeks ago but now the date is pushed back.  If
> anyone knows where I can get about a dozen right quick, please email me.
>
> Larry Doolittle wrote:
>
> > I'm resurrecting an old thread, because Avnet and Insight
> > now have reasonable prices listed for the Spartan-II chips.
> >
> > The two distributors agree to the penny wherever they overlap,
> > so I assume these are Xilinx sanctioned prices in US$ for
> > small quantities as of May 16, 2000:
> >
> >             TQ144C   PQ208C   FG256C   FG456C
> > XC2S50-5    $12.85   $14.75   $16.65
> > XC2S100-5   $17.60   $19.55   $24.65   $31.00
> > XC2S150-5            $21.60   $27.00   $35.10
> >
> > These are a _lot_ lower than a month ago, even lower than
> > I predicted.  I thought they would be more sensitive to their
> > Virtex customers (Virtex prices haven't dropped, an XCV100
> > is still generally above $100).  Maybe they think most Virtex
> > customers have become addicted to the larger sizes available
> > in that line.
> >
> > The remaining question is availability.  Those distributors
> > don't claim stock ("Please call").  Does anyone here know
> > the real scoop?  If not, I'll try to get something out of
> > Insight.
> >
> > I have updated http://recycle.lbl.gov/xc2search.html with this
> > info.
> >
> >       - Larry Doolittle   <LRDoolittle@lbl.gov>
>
> --
> P.S.  Please note the new email address and website url
>
> -Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930     Fax 401/884-7950
> email ray@andraka.com
> http://www.andraka.com  or http://www.fpga-guru.com

--

Rick Collins

rick.collins@XYarius.com

remove the XY to email me.



Arius, Inc. - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX

Internet URL http://www.arius.com


Article: 22688
Subject: Re: Spartan II availability and pricing
From: Ray Andraka <ray@andraka.com>
Date: Thu, 18 May 2000 03:31:45 GMT
Links: << >>  << T >>  << A >>


Rick Collins wrote:

> Ray,
>
> I am looking at using the FG packages on a new board and I am not sure how
> easy they are to use. I have used the BG256 package  before and the layout
> ended up with a number of vias in between the pads that pushed my PCB design
> rules down to 5 mil trace and 5 mil space. This ended up costing me a lot
> more to get the PCBs made.
>
> The FG256 and FG456 packages use an even smaller pin pitch. In addition, the
> FG256 has no space in the center to place vias and the FG456 is not much
> better.

The center pins on the FG are all ground.  The signal pins are towards the outer
perimeter, so it may not be as bad as it first looked.  The layout house had no
problems with the FG256 packaging.

>
>
> How are you laying out your boards to use these parts? Are you going to 5/5
> or smaller design rules on the PCB?

4DI on Long Island (Haupaug I think) is doing the layout.  I believe we are
doing 5/5.  I've had good experiences with 4DI in the past.

> I am currently using the Lucent Orca parts because they provide a lot of IO
> in a given package. When Xilinx went to the Virtex parts, they dramatically
> cut down on the available IO counts. The Spartan II parts are even worse.
> e.g. the XC4020 in a BG256 package gives 205 IOs. The Virtex part gives 180
> IOs. The Spartan II only has 176 in the FG256. Any idea why?

Its the packaging mostly, and they are putting more grounds on to cut down on
ground bounce problems.  FWIW, the VIrtex also comes in an FG256, and from what
I can see the pinouts are identical with the exception of the temp sense diode:
spartanII replaces it with a power down and status pin.

>
>
> To convert my current design over to Xilinx parts, I would have to move two
> smaller parts from VQ100 packages to the TQ144 package to compensate for the
> loss of IOs. Then to regain board space, I have to combine my large part
> (currently a BG256 with 221 IOs) with a third smaller part and use an FG456
> package. But I had enough trouble getting the BGA laidout and mounted that I
> really don't want to go to a finer pitch part and run up the cost of the
> PCB.
>
> The design is modular so I can't combine all of the parts into one package.
> My preferece is to have one large part with about 220 IOs and three smaller
> parts with about 75 IOs. But this won't fit on the board with the Spartan
> IIs unless I go with the fine pitch or chip scale packages.
>
> Another problem is the multiple Vcc voltages that are showing up on the
> board. The board will be powered from 5V and will have a small number of 5V
> parts. An on board switcher provides 3.3V for the DSP IOs, memory, etc. The
> DSP needs 1.8V and now the Spartan II/Virtex parts need 2.5V. That's 4 power
> voltages on a PC/104 board! I really don't know what to do with that. The
> 1.8V is only 100 mA or so, but I expect the 3 or 4 FPGAs will need a lot
> more current than that from the 2.5V supply so I would need a second
> switcher on board. The Virtex E parts are out because I need 5V
> compatibility on almost 100 pins. Xilinx says you can have a Virtex E pin as
> input or output on a 5V signal, but they don't show you how to do a
> bidirectional path.
>
> If I stick with the older technology 3.3V FPGAs from Xilinx, I have to pay a
> lot more for the same number of gates.

>
>
> Any ideas?
>
> Ray Andraka wrote:
>
> > I'm looking for a small quantity of XC2S50-5FG256C for a prototype
> > build.  I need them for June 1st.   We had some on order, they were
> > supposed to be in a few weeks ago but now the date is pushed back.  If
> > anyone knows where I can get about a dozen right quick, please email me.
> >
> > Larry Doolittle wrote:
> >
> > > I'm resurrecting an old thread, because Avnet and Insight
> > > now have reasonable prices listed for the Spartan-II chips.
> > >
> > > The two distributors agree to the penny wherever they overlap,
> > > so I assume these are Xilinx sanctioned prices in US$ for
> > > small quantities as of May 16, 2000:
> > >
> > >             TQ144C   PQ208C   FG256C   FG456C
> > > XC2S50-5    $12.85   $14.75   $16.65
> > > XC2S100-5   $17.60   $19.55   $24.65   $31.00
> > > XC2S150-5            $21.60   $27.00   $35.10
> > >
> > > These are a _lot_ lower than a month ago, even lower than
> > > I predicted.  I thought they would be more sensitive to their
> > > Virtex customers (Virtex prices haven't dropped, an XCV100
> > > is still generally above $100).  Maybe they think most Virtex
> > > customers have become addicted to the larger sizes available
> > > in that line.
> > >
> > > The remaining question is availability.  Those distributors
> > > don't claim stock ("Please call").  Does anyone here know
> > > the real scoop?  If not, I'll try to get something out of
> > > Insight.
> > >
> > > I have updated http://recycle.lbl.gov/xc2search.html with this
> > > info.
> > >
> > >       - Larry Doolittle   <LRDoolittle@lbl.gov>
> >
> > --
> > P.S.  Please note the new email address and website url
> >
> > -Ray Andraka, P.E.
> > President, the Andraka Consulting Group, Inc.
> > 401/884-7930     Fax 401/884-7950
> > email ray@andraka.com
> > http://www.andraka.com  or http://www.fpga-guru.com
>
> --
>
> Rick Collins
>
> rick.collins@XYarius.com
>
> remove the XY to email me.
>
> Arius, Inc. - A Signal Processing Solutions Company
> Specializing in DSP and FPGA design
>
> Arius
> 4 King Ave
> Frederick, MD 21701-3110
> 301-682-7772 Voice
> 301-682-7666 FAX
>
> Internet URL http://www.arius.com

--
P.S.  Please note the new email address and website url

-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com  or http://www.fpga-guru.com


Article: 22689
Subject: Traning for Nallatech??
From: "A." <ahmad@frognet.net>
Date: Thu, 18 May 2000 00:38:44 -0400
Links: << >>  << T >>  << A >>
Hi all..
we have Nallatech Virtex XV800 board. Is their any short training courses
into how to use it?
Thank you in advanced.


Article: 22690
Subject: Re: Spartan II availability and pricing
From: Rick Collins <spamgoeshere3@yahoo.com>
Date: Thu, 18 May 2000 01:45:59 -0400
Links: << >>  << T >>  << A >>
I found what looks like a marketing glossy, but is really an app note in disguise
showing recommended pad and via layouts for the CS and FG packages. They show
annular rings of 5 mil widths. So I guess I can go with an FG or CS package and at
least not make my board fab any worse.

So instead of one larger part and three smaller parts, I could do a little
repartitioning and use two XC2S50-5FG256 and two XC2Sxx-5CS144 chips. But I don't
think I have heard when either the smaller two chips (XC2S15 or XC2S30) or the CS144
package for SpartanII will be out. But this combination will give me a lot more
gates, a few more pins, more flexibility in using larger parts and cost less than
what I am using now!

All I have to do is convince myself that a board full of BGA type packaging won't be
hard to debug!


Ray Andraka wrote:

> Rick Collins wrote:
>
> > Ray,
> >
> > I am looking at using the FG packages on a new board and I am not sure how
> > easy they are to use. I have used the BG256 package  before and the layout
> > ended up with a number of vias in between the pads that pushed my PCB design
> > rules down to 5 mil trace and 5 mil space. This ended up costing me a lot
> > more to get the PCBs made.
> >
> > The FG256 and FG456 packages use an even smaller pin pitch. In addition, the
> > FG256 has no space in the center to place vias and the FG456 is not much
> > better.
>
> The center pins on the FG are all ground.  The signal pins are towards the outer
> perimeter, so it may not be as bad as it first looked.  The layout house had no
> problems with the FG256 packaging.
>
> >
> >
> > How are you laying out your boards to use these parts? Are you going to 5/5
> > or smaller design rules on the PCB?
>
> 4DI on Long Island (Haupaug I think) is doing the layout.  I believe we are
> doing 5/5.  I've had good experiences with 4DI in the past.
>
> > I am currently using the Lucent Orca parts because they provide a lot of IO
> > in a given package. When Xilinx went to the Virtex parts, they dramatically
> > cut down on the available IO counts. The Spartan II parts are even worse.
> > e.g. the XC4020 in a BG256 package gives 205 IOs. The Virtex part gives 180
> > IOs. The Spartan II only has 176 in the FG256. Any idea why?
>
> Its the packaging mostly, and they are putting more grounds on to cut down on
> ground bounce problems.  FWIW, the VIrtex also comes in an FG256, and from what
> I can see the pinouts are identical with the exception of the temp sense diode:
> spartanII replaces it with a power down and status pin.

Any idea why the Spartan II has even fewer IOs in some of the packages?


--

Rick Collins

rick.collins@XYarius.com

remove the XY to email me.



Arius, Inc. - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX

Internet URL http://www.arius.com


Article: 22691
Subject: Re: Spartan II availability and pricing
From: Ray Andraka <ray@andraka.com>
Date: Thu, 18 May 2000 06:10:30 GMT
Links: << >>  << T >>  << A >>
Rick,

I've done somewhere around 200 FPGA designs now, and honestly, I can't remember putting
test equipment on the FPGA leads.  With the SRAM FPGAs, it isn't that hard to write test
designs to a) check out the board to make sure you don't have bad connections, and b)
put test stimulators, capture or compare logic in the design temporarily.  Even then, a
good simulation will get you running without even having to go that far.  Don't fret it,
you'll do fine as long as you apply some thought to your testing.

Rick Collins wrote:

> I found what looks like a marketing glossy, but is really an app note in disguise
> showing recommended pad and via layouts for the CS and FG packages. They show
> annular rings of 5 mil widths. So I guess I can go with an FG or CS package and at
> least not make my board fab any worse.
>
> So instead of one larger part and three smaller parts, I could do a little
> repartitioning and use two XC2S50-5FG256 and two XC2Sxx-5CS144 chips. But I don't
> think I have heard when either the smaller two chips (XC2S15 or XC2S30) or the CS144
> package for SpartanII will be out. But this combination will give me a lot more
> gates, a few more pins, more flexibility in using larger parts and cost less than
> what I am using now!
>
> All I have to do is convince myself that a board full of BGA type packaging won't be
> hard to debug!
>
> Ray Andraka wrote:
>
> > Rick Collins wrote:
> >
> > > Ray,
> > >
> > > I am looking at using the FG packages on a new board and I am not sure how
> > > easy they are to use. I have used the BG256 package  before and the layout
> > > ended up with a number of vias in between the pads that pushed my PCB design
> > > rules down to 5 mil trace and 5 mil space. This ended up costing me a lot
> > > more to get the PCBs made.
> > >
> > > The FG256 and FG456 packages use an even smaller pin pitch. In addition, the
> > > FG256 has no space in the center to place vias and the FG456 is not much
> > > better.
> >
> > The center pins on the FG are all ground.  The signal pins are towards the outer
> > perimeter, so it may not be as bad as it first looked.  The layout house had no
> > problems with the FG256 packaging.
> >
> > >
> > >
> > > How are you laying out your boards to use these parts? Are you going to 5/5
> > > or smaller design rules on the PCB?
> >
> > 4DI on Long Island (Haupaug I think) is doing the layout.  I believe we are
> > doing 5/5.  I've had good experiences with 4DI in the past.
> >
> > > I am currently using the Lucent Orca parts because they provide a lot of IO
> > > in a given package. When Xilinx went to the Virtex parts, they dramatically
> > > cut down on the available IO counts. The Spartan II parts are even worse.
> > > e.g. the XC4020 in a BG256 package gives 205 IOs. The Virtex part gives 180
> > > IOs. The Spartan II only has 176 in the FG256. Any idea why?
> >
> > Its the packaging mostly, and they are putting more grounds on to cut down on
> > ground bounce problems.  FWIW, the VIrtex also comes in an FG256, and from what
> > I can see the pinouts are identical with the exception of the temp sense diode:
> > spartanII replaces it with a power down and status pin.
>
> Any idea why the Spartan II has even fewer IOs in some of the packages?
>
> --
>
> Rick Collins
>
> rick.collins@XYarius.com
>
> remove the XY to email me.
>
> Arius, Inc. - A Signal Processing Solutions Company
> Specializing in DSP and FPGA design
>
> Arius
> 4 King Ave
> Frederick, MD 21701-3110
> 301-682-7772 Voice
> 301-682-7666 FAX
>
> Internet URL http://www.arius.com

--
P.S.  Please note the new email address and website url

-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com  or http://www.fpga-guru.com


Article: 22692
Subject: Translate to verilog
From: "Tomasz Brychcy" <tbrychcy@sensor.ime.pz.zgora.pl>
Date: Thu, 18 May 2000 08:18:13 +0200
Links: << >>  << T >>  << A >>
Hello,

I would like translate the part of vhdl source to verilog. Please about
correct translation the fragment of vhdl.

process(READ,RESET)
 begin
  if (RESET='1') then
   BYTE<='0';
  elsif (RISING_EDGE(READ)) then
   if (CS='1' and BACK='0') then
    BYTE<=not BYTE;
   end if;
  end if;
 end process;

I ask for any help on my e-mail below.

T.Brychcy@pz.zgora.pl


Article: 22693
Subject: Re: Do you know xilinx FPGAs well?
From: "EKC" <NOSPAMalpha3.1@ix.netcom.com>
Date: Thu, 18 May 2000 06:50:04 GMT
Links: << >>  << T >>  << A >>

Steve Casselman wrote in message ...
>You might think about this.
>
>http://www.sidsa.es/fipsoc_r.htm
>


Great. How do I order a development board, and how much does each FIPSOC
cost?

-EKC


Article: 22694
Subject: PCI & Virtex
From: William LenihanIii <lenihan3we@earthlink.net>
Date: Thu, 18 May 2000 07:07:33 GMT
Links: << >>  << T >>  << A >>
Can anyone point me to some resources to find out how much loading a PCI
bus can take, and specifically how many loads a Xilinx Virtex
represents? In the old TTL days, loading was just a factor of the
drivers static IOH/IOL vs. the receivers IIH/IIL, but I'm new to PCI and
I suspect the calculations aren't as trivial.

--
========================
William Lenihan
lenihan3we@earthlink.net
========================


Article: 22695
Subject: Re: PC104+ FPGA Board
From: Jean-Luc Nagel <jean-luc.nagel@imt.unine.ch>
Date: Thu, 18 May 2000 09:09:41 +0200
Links: << >>  << T >>  << A >>


Rick Collins wrote:

> How many boards do you think you will need? If the quantity is sufficient, I am
> sure that someone will work with you to add such a board to their product line.

Well the quantity is rather small because we would only use these boards for a
small number of demos. The asic is anyway the goal.
Ok I guess I will forget PC104+ ! :)

--
Jean-Luc

Article: 22696
Subject: Help with macrocell , explain it to me
From: "Eircom" <keith@suparule.com>
Date: Thu, 18 May 2000 08:32:23 +0100
Links: << >>  << T >>  << A >>
Can some one explain

What is a macrocell
It's use

keith@suparule.com


Article: 22697
Subject: Re: Reccomend an ASIC emulation board
From: Patrick Schulz <schulz@rumms.uni-mannheim.de>
Date: Thu, 18 May 2000 10:01:57 +0200
Links: << >>  << T >>  << A >>
Malachy Devlin wrote:
> 
> John,
> 
> You could try the Ballynuey card from Nallatech
> (http://www.nallatech.com/dime/ballynuey2/index.htm).
> This card has 4 DIME slots which can take a range of modules including
> one of the modules which has
> dual FPGAs (the Ballyblue), this would allow you to scale the card with
> the number of FPGAs that
> you require.
> 
> Malachy

Seams like advertising in two threads ;-)

Are you a guy from Nallatech? That would be fine, because I prefer personal contact to suppliers.

Patrick
-- 
Patrick Schulz (schulz@rumms.uni-mannheim.de, pschulz@ieee.org)
University of Mannheim - Dep. of Computer Architecture
68161 Mannheim - GERMANY / http://mufasa.informatik.uni-mannheim.de
Phone: +49-621-181-2720     Fax: +49-621-181-2713
Article: 22698
Subject: Re: Best choice between FPGA and CPLD
From: Patrick Schulz <schulz@rumms.uni-mannheim.de>
Date: Thu, 18 May 2000 10:27:29 +0200
Links: << >>  << T >>  << A >>
Simon Bilodeau wrote:
> 
> What do you mean by FF?
> 
Try http://www.chemie.fu-berlin.de/cgi-bin/acronym for decrypting acronyms and
http://wombat.doc.ic.ac.uk/foldoc/foldoc.cgi?query=flip-flop for explanation.

A complete description of FPGA and CPLD architecture you'll find at
http://www.eecg.toronto.edu/~jayar/pubs/brown/survey.html

Patrick

-- 
Patrick Schulz (schulz@rumms.uni-mannheim.de, pschulz@ieee.org)
University of Mannheim - Dep. of Computer Architecture
68161 Mannheim - GERMANY / http://mufasa.informatik.uni-mannheim.de
Phone: +49-621-181-2720     Fax: +49-621-181-2713
Article: 22699
Subject: Re: PCI & Virtex
From: "Lutz Kleberhoff" <l.kleberhoff@mkc-gmbh.de>
Date: Thu, 18 May 2000 13:05:10 +0200
Links: << >>  << T >>  << A >>
Hi William,

there is a simple rule: Use a chip, which is PCI-compliant.
PCI accepts 10 loads (each chip is 1 load and each pair of connectors is 1
load too)
for more information: use the PCI-Spec.

Lutz

William LenihanIii schrieb in Nachricht <392396D6.E8985426@earthlink.net>...
>Can anyone point me to some resources to find out how much loading a PCI
>bus can take, and specifically how many loads a Xilinx Virtex
>represents? In the old TTL days, loading was just a factor of the
>drivers static IOH/IOL vs. the receivers IIH/IIL, but I'm new to PCI and
>I suspect the calculations aren't as trivial.
>
>--
>========================
>William Lenihan
>lenihan3we@earthlink.net
>========================
>
>




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