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Messages from 22800

Article: 22800
Subject: Re: 8087 in FPGA?
From: "Jan Gray" <jsgray@acm.org.nospam>
Date: Thu, 25 May 2000 00:31:29 GMT
Links: << >>  << T >>  << A >>
shahzad2512@my-deja.com wrote in message <8gflvq$jr4$1@nnrp1.deja.com>...
>8087 is a math coprocessor and does calculations in FP numbers. Is it
>wise to implement 8087 in an FPGA. I want to do this for a University
>project. Please comment and advice.

See also http://www.fpgacpu.org/usenet/fp.html.

Jan Gray
Gray Research LLC



Article: 22801
Subject: Re: Xilinx Logic Cell counts and carry chains
From: Ray Andraka <ray@andraka.com>
Date: Thu, 25 May 2000 02:09:35 GMT
Links: << >>  << T >>  << A >>
I think they are pushing for the big green button approach to hardware
development.  With that, why would anyone need a data sheet?   ;-^

Rickman wrote:

>
> I think I understand why they rearranged the logic the way they did as
> it gives you full 6 input functions and nibble wide registers. What I
> don't understand is why they don't document the new parts as well as
> they did the older logic.

--
P.S.  Please note the new email address and website url

-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com  or http://www.fpga-guru.com


Article: 22802
Subject: Re: Implementation in FPGA
From: Ray Andraka <ray@andraka.com>
Date: Thu, 25 May 2000 02:12:45 GMT
Links: << >>  << T >>  << A >>
A DCT is not a trivial core, as to accomplish it efficiently in an FPGA you need
to be well versed in the FPGA architecture as well as hardware structures for
the DCT.  With that in mind, you might first consider a third party core. I
think ISS has one, for example.  If you are bent on rolling your own, you might
start by looking for HARDWARE implementations of the DCT in IEEE transactions.

Seb C wrote:

> Hi, i've  a pb, it's my first time i must implement in FpGA so i'm a novice,
> i want all what you are about DCT implementation using FPGA or anything who
> can help me because i'm a beginner and i must take all what i can find about
> DCT and implementation using FPGA after i'll can begin too learn seriously
> because some books are not very clear so, pliz help me !!
>
> thx in advance
>
> SEB

--
P.S.  Please note the new email address and website url

-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com  or http://www.fpga-guru.com


Article: 22803
Subject: Re: 8087 in FPGA?
From: Ray Andraka <ray@andraka.com>
Date: Thu, 25 May 2000 03:48:48 GMT
Links: << >>  << T >>  << A >>


Andy Peters wrote:

> shahzad2512@my-deja.com wrote in message <8gflvq$jr4$1@nnrp1.deja.com>...
> >8087 is a math coprocessor and does calculations in FP numbers.
>
> Yes, I know.
>
> >Is it wise to implement 8087 in an FPGA.
>
> Probably not, since floating-point math is one of the few things FGPAs don't
> do well.

You can do floating point just fine in FPGAs, but for it is usually not very
efficient use of the real estate, especially in DSP applications where your
dynamic range usually only changes the exponent by a few counts if floating
point is used.   In these cases, it is far more efficient to extend the
precision of your fixed point arithmetic, plus you don't wind up with that pesky
floating point truncation working its way into your significand.  So the bottom
line, FPGAs do fine with floating point, but you pay dearly for it in area.

>
>
> also, I think that Intel might step all over your buttocks if you tried to
> sell it.
>
> > I want to do this for a University project.
>
> you may want to consider doing a vending machine.
>
> -- a
> -----------------------------------------
> Andy Peters
> Sr Electrical Engineer
> National Optical Astronomy Observatories
> 950 N Cherry Ave
> Tucson, AZ 85719
> apeters (at) noao \dot\ edu
>
> "A sufficiently advanced technology is indistinguishable from magic"
>      --Arthur C. Clarke

--
P.S.  Please note the new email address and website url

-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com  or http://www.fpga-guru.com


Article: 22804
Subject: Verilog assignment
From: "R. T. Finch" <robfinch@cyg.net>
Date: Thu, 25 May 2000 06:03:51 -0400
Links: << >>  << T >>  << A >>
duh,
What is the difference between a continuous assignment and a non continuous
one in verilog ? ("<=" and "=")

I keep getting an warning message "assignment from wire to reg" how do I fix
this ?

Thanx
Rob



Article: 22805
Subject: Re: Web page for FPGA design jobs???
From: lkostov@my-deja.com
Date: Thu, 25 May 2000 10:29:22 GMT
Links: << >>  << T >>  << A >>
You could try also www.dice.com

Latchezar

In article <392C36D0.9FF872D8@hotgurus.com>,
  Robert <robert@hotgurus.com> wrote:
> Try    www.hotgurus.com
>
> Dan wrote:
>
> > I am looking for work as an FPGA designer.
> > My specialty is graphics/video/imaging.
> >
> > Are there any good web pages dedicated to this field ?
> >
> > Thanks
> > Dan
>
>


Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 22806
Subject: Help for Spartan XCS10
From: lkostov@my-deja.com
Date: Thu, 25 May 2000 10:49:05 GMT
Links: << >>  << T >>  << A >>
Hello,
I must use Xilinx FPGA for my thesis and I try to make a simple design
with Xilinx Spartan XCS10 in PLCC 84 package to learn how it could be
programmed and how it operate.
I make a simple schematic only for connection to Vcc (2, 11, 22, 54,
63, 33, 42 and 74 pins), GND (1, 12, 21, 31, 43, 52, 64 and 76), JTAG
signals (TCK on 16, TDO on 75, TDI on 15 and TMS on 17) and a few LEDs
and Resistors to some I/O pins (3, 4, 5, 6, 46, 47, 48 and 49 pins).
I make a few designs in Xilinx Fondation Software and program the XCS10
by Parallel cable. I was expected that the XCS10 will begin to operate
like the implemented schematics but I have mistake. It didn't change
the state of noone I/O pin.
Could someone tell me if I make some mistake or to show me an example
of using XCS10? I have capacitors between all Vcc and GND and the
program of the XCS10 is successful (by Xilinx's software).

Thank you in advance!
Latchezar Kostov


Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 22807
Subject: Re: [Part II] - Pb FPGA Xilinx config process
From: Sebastien Favard <Sebastien.Favard@utc.fr>
Date: Thu, 25 May 2000 12:57:04 +0200
Links: << >>  << T >>  << A >>
Philip Freidin wrote:

> >During the FPGA programmation step, the header is correctly detected and
> >its bits are reported on DOUT. Just after the header, DOUT is hold at 5V
> >:) and during the data stream, no crc error ic occured.
> >
>
> Thats encouraging.
>

Hi :)

Yes my old FPGA was dead... It's really strange in fact that my old FPGA was
capable to report all bits DIN on DOUT pin.... perhaps it was the ONLY thing
that it was capable :)))


> Default selects CCLK for the startup sequence. (which I recomend)

Yes I use it and it's good now :D I'm really happy because it's my first
design !


> By the way, are you aware that the 5200 series is not a "preferred"
> product for new designs. Spartan and Spartan II devices are faster, have
> more features (like decent I/O cells, better carry logic, and on-chip
> RAM), and they are cheaper.

Yes and I want to support the Spartan in the futur. In fact it's the same
package between XC5202, XCS05 and XC4003E  so :)
For my prototype I continuous to use the XC5202 but after I want buy a Spartan
to support more complex design...

thx a lot Philip for all your very good helps :)

Sebastien,


Article: 22808
Subject: Re: Coregen generated FIFO not working
From: "Paul T. Shultz" <paul@csciences.com>
Date: Thu, 25 May 2000 07:12:05 -0400
Links: << >>  << T >>  << A >>
Khoi,

I had problems with the same FIFO a while ago.  There are two simple things
to check.  First the reset is active high and is synchronous.  Second the WE
and RE signals are active high.  I hope this helps.

Regards,

Paul T. Shultz
paul@csciences.com
Chesapeake Sciences Corporation
1127B Benfield Blvd.,  Millersville, MD  21108 USA
TEL (410) 923-1300 x3070  FAX (410) 923-2669

khoi ha <kha@fallschurch.esys.com> wrote in message
news:39296769.357B44ED@fallschurch.esys.com...
> Hello,
>
> I created a 255 deep by 32 bit fifo using Coregen and I am having
> problem getting it to simulate.  The device does not seem to be doing
> anything, even the reset input does not work.  I know this is a lot to
> ask but hopefully there is something I missed that are easy to see.  I
> followed exactly what the Coregen's user manual told me to do.  Here are
>
> my tools environment:
>
> Window NT
> Using Virtex 1000 series
> Using Modelsim PE/VHDL 5.3b
> Using Coregen 2.1i
> Using C_IP5
>
> Attached is my vhdl file that instantiated the files (.vho) produced by
> Coregen.
>
> Thanks
> Khoi Ha
> Raytheon Systems
> (703)560-5000 x4481
>
>
>


Article: 22809
Subject: Search Spartan for small quantity
From: Sebastien Favard <Sebastien.Favard@utc.fr>
Date: Thu, 25 May 2000 13:38:22 +0200
Links: << >>  << T >>  << A >>
Hi,

I search Spartan XS05 for a small quantity. Here I know a vendor that he
sell me it ar $20 !!!!! yes $20 and not $2 :(

If anyone know a web-buisness or others....

Sebastien


Article: 22810
Subject: Fire Wire
From: "Saqib" <saqib_khursheed@yahoo.com>
Date: 25 May 2000 04:32:45 -0800
Links: << >>  << T >>  << A >>

Hi all,
  I am currently doing my project on Fire Wire.  I have to develop the RTL core of IEEE-1394 Link Layer Controller, in Verilog.  So is there anyone who has worked in this field so can answer me few questions??

Student Final Year,
Computer System Engg.
Pakistan.
Article: 22811
Subject: Fire Wire
From: "Saqib" <saqib_khursheed@yahoo.com>
Date: 25 May 2000 04:33:00 -0800
Links: << >>  << T >>  << A >>

Hi all,
  I am currently doing my project on Fire Wire.  I have to develop the RTL core of IEEE-1394 Link Layer Controller, in Verilog.  So is there anyone who has worked in this field so can answer me few questions??

Student Final Year,
Computer System Engg.
Pakistan.
Article: 22812
Subject: CRC
From: "Saqib" <saqib_khursheed@yahoo.com>
Date: 25 May 2000 04:37:40 -0800
Links: << >>  << T >>  << A >>

Hi all,
   I have to implement CRC in Verilog, which is the same as used in IEEE-802, LAN.  Is there anyone who can help me out, and tell me the Standard implementation.  I shall be thankful to him/her.

Student Computer System,
NED university,
Pakistan.
Article: 22813
Subject: Programming using *.rbt file
From: steveh@link-comm.com (Steve Holle)
Date: Thu, 25 May 2000 14:17:47 GMT
Links: << >>  << T >>  << A >>
We've been trying to program a Spartan S10vq100 using the *.rbt file,
the ASCII bit file generated by the Foundation tools.  We've noticed a
couple of discrepencies, the first of which is that the Bits: value
(95008) does not match the bit count encoded in the header line
(95001).  Also, we have been unable to successfully program the part
using the bits supplied in the *.rbt file.  We have captured the end
of programming sequence by triggering on the DONE line.  By comparing
what our uC generates and what is generated when we program from the
Parallel Cable, it appears that we still have 7 bits of data to output
after the DONE line goes high.  Although the DONE bit goes high and
the INIT line does not go low again, the part does not operate
properly.  I have two questions:

1)Do I need to shift out all the bits, starting with the dummy bits at
the beginning of the header?

2)Has anyone else successfully programmed a Spartan part using the
*.rbt file and if so, would you be willing to share your code?
Article: 22814
Subject: Re: Error with Quartus for Altera APEX20K device: clock skew is greater then data delay
From: "Michel Le Mer" <michel.lemer@ago.fr>
Date: Thu, 25 May 2000 16:48:29 +0200
Links: << >>  << T >>  << A >>
Hi

I had the same problem when I set :   LPM_ADDRESS_CONTROL => "UNREGISTERED",
for the lpm_ram_dq component. I change it to registered and the problem
disappearred. It seemed that some data, write or address signal arrived
faster to the ESB than the clock. If the clock has a high fan out, it could
be delayed. If the global signal is used, the delay is decreased. But it can
stay too big. It seems that it is a Apex or Quartus problem, I never heard
of that before if a design was synchronous.

Michel Le Mer

Don <nospam@here.com> a écrit dans le message :
392BFC38.FAD16235@here.com...
> Hi,
>
> Two clocks, only constraining one.  It's sourced from io.  I am clocking
> ESB ram with it.  I do not know about Auto Global.  After starting fresh
> and running this again, it seemed to clear up the quartus db and I
> didn't get the error, but then I did see it again on a later revision.
>
> Thanks
>
> Michel Le Mer wrote:
>
> > Hello
> >
> > How many clock do you have in your design? Is your in
> > question clock supply directly from an I/O or built inside
> > the fpga? Do you use ESB ram without clocking the ESB
> > input / output?
> > In the Quartus software the Auto Global is ON by default,
> > what about an equivalent option with Leonardo?
> >
> > Good luck
> >
> > * Sent from AltaVista http://www.altavista.com Where you can also find
> related Web Pages,
> Images, Audios, Videos, News, and Shopping.  Smart is Beautiful
>
>
>
>
>


Article: 22815
Subject: Apex supply problem
From: "Michel Le Mer" <michel.lemer@ago.fr>
Date: Thu, 25 May 2000 17:00:41 +0200
Links: << >>  << T >>  << A >>
Hi

Does anybody hear about power problem with Apex?
We have a PCB with 3 Apex20K200E and a microprocessor. If the suplly rise
slowly (about 10ms), the 3.3V supply 1 more ampere and the microprocessor
bus (which is linked to the 3 fpgas) is unusable (conflict problem). If we
start to download the fpga with the JTAG cable, the problem disappears at
the beginning of the 3rd fpga downloading. If the suplly raises in less than
2 ms, the 3.3V and 1.8V rise in the same way and there is no problem.
Does anybody have any idea?

Thanks.
Michel Le Mer       immeuble Cerium
STA                      12, square du chaine Germain
02 23 20 04 72     35510 Cesson-Sévigné



Article: 22816
Subject: PCI core
From: "Angel Ramiro Manzano" <angel.ramiro@NOSPAMds2.es>
Date: Thu, 25 May 2000 17:34:25 +0200
Links: << >>  << T >>  << A >>
Hi all,
I am looking for a soft PCI master-target core. The idea is to implement it
in Xilinx Virtex, test it, then migrate it to ASIC. The frequency we need is
33 MHz and the bus width 32 bits.
Could somebody can recommend me one? Thanks in advance.

Angel Ramiro.
DS2

(please remove NOSPAM from my address before answering)


Article: 22817
Subject: Implementation using FPGA
From: "Seb C" <seb@stien.bizland.com>
Date: Thu, 25 May 2000 15:37:13 GMT
Links: << >>  << T >>  << A >>
Hi, i've  a pb, it's my first time i must implement in FpGA so i'm a novice,
i want all what you are about DCT implementation using FPGA or anything who
can help me because i'm a beginner and i must take all what i can find about
DCT and implementation using FPGA after i'll can begin too learn seriously
because some books are not very clear so, pliz help me !!

thx in advance

SEB




Article: 22818
Subject: Re: PCI core
From: "Marc K." <marck@omneon.com>
Date: Thu, 25 May 2000 16:39:14 GMT
Links: << >>  << T >>  << A >>
Try www.compaq.com and search for "pci-x".

Marc

"Angel Ramiro Manzano" <angel.ramiro@NOSPAMds2.es> wrote in message
news:959268413.411642@cache0-serv...
> Hi all,
> I am looking for a soft PCI master-target core. The idea is to implement
it
> in Xilinx Virtex, test it, then migrate it to ASIC. The frequency we need
is
> 33 MHz and the bus width 32 bits.
> Could somebody can recommend me one? Thanks in advance.
>
> Angel Ramiro.
> DS2
>
> (please remove NOSPAM from my address before answering)
>
>


Article: 22819
Subject: Re: Apex supply problem
From: Tom Burgess <tom.burgess@hia.nrc.ca>
Date: Thu, 25 May 2000 09:55:28 -0700
Links: << >>  << T >>  << A >>
High startup current and minimum supply risetime requirements also apply to
Xilinx's Virtex parts. (See Virtex data sheet under Power-on Power Requirements)
Such is the price of progess :) Maybe Altera has a similar warning buried somewhere
in their literature - or ask them?


Michel Le Mer wrote:
> 
> Hi
> 
> Does anybody hear about power problem with Apex?
> We have a PCB with 3 Apex20K200E and a microprocessor. If the suplly rise
> slowly (about 10ms), the 3.3V supply 1 more ampere and the microprocessor
> bus (which is linked to the 3 fpgas) is unusable (conflict problem). If we
> start to download the fpga with the JTAG cable, the problem disappears at
> the beginning of the 3rd fpga downloading. If the suplly raises in less than
> 2 ms, the 3.3V and 1.8V rise in the same way and there is no problem.
> Does anybody have any idea?
> 
> Thanks.
> Michel Le Mer       immeuble Cerium
> STA                      12, square du chaine Germain
> 02 23 20 04 72     35510 Cesson-Sévigné

regards,
Tom Burgess
-- 
Digital Engineer
Dominion Radio Astrophysical Observatory
P.O. Box 248, Penticton, B.C.
Canada V2A 6K3
Email:        tom.burgess@hia.nrc.ca
Article: 22820
Subject: Re: CRC
From: "Marc K." <marck@omneon.com>
Date: Thu, 25 May 2000 16:57:14 GMT
Links: << >>  << T >>  << A >>
Saqib,

This was posted on comp.lang.verilog. Maybe it will help.

Marc

......
Hi:

In response to popular demand, I am happy to announce
that CRC Tool now supports input data widths up to 256 bit.

CRC Tool is a free tool that generates VHDL and Verilog
RTL code for CRC calculations, for any polynomial and any
input data width up to 256 bit.

You can run it interactively over the web from:

   http://www.easics.com/webtools/crctool

Regards, Jan

--
Jan Decaluwe        Easics
Design Manager         System-on-Chip design services
+32-16-395 600        Interleuvenlaan 86, B-3001 Leuven, Belgium
mailto:jand@easics.be  http://www.easics.com


"Saqib" <saqib_khursheed@yahoo.com> wrote in message
news:392d1084@patience.ibsystems.com...
>
> Hi all,
>    I have to implement CRC in Verilog, which is the same as used in
IEEE-802, LAN.  Is there anyone who can help me out, and tell me the
Standard implementation.  I shall be thankful to him/her.
>
> Student Computer System,
> NED university,
> Pakistan.


Article: 22821
Subject: Re: Verilog assignment
From: Utku Ozcan <ozcan@netas.com.tr>
Date: Thu, 25 May 2000 20:16:27 +0300
Links: << >>  << T >>  << A >>
R. T. Finch wrote:

> duh,
> What is the difference between a continuous assignment and a non continuous
> one in verilog ? ("<=" and "=")
>
> I keep getting an warning message "assignment from wire to reg" how do I fix
> this ?
>
> Thanx
> Rob

First question:

Very very briefly: Model your chip with non-blocking assignments
(NBAs). Model your testbench with blocking assignments. Please
go to FAQ:  http://www.angelfire.com/in/verilogfaq/index.html .
Here you will find your answer in a more technical and detailed way.

Synthesize following codes:

always @(posedge clock or negedge reset)
 if (reset)
  begin
    a = 0;
    c = 0;
  end
 else
  begin
    a = b;
    c = a;
  end

...and,

always @(posedge clock or negedge reset)
 if (reset)
  begin
   a <= 0;
   c <= 0;
  end
 else
  begin
   a <= b;
   c <= a;
  end

In the first code, you will get one FF. In the second one,
you will get two FFs in series.

Your second question: Probably you have done like following?:

reg pci_granted;
wire pci_granted_internal;

assign pci_granted = pci_granted_internal;

You have not given the Verilog code, so I assume the situation
above happened to you. If yes, then don't forget that the Lvalue
of assign must be a wire, but not reg.

Utku
--
I feel better than James Brown.


Article: 22822
Subject: Re: Xilinx Virtex E
From: Utku Ozcan <ozcan@netas.com.tr>
Date: Thu, 25 May 2000 20:21:36 +0300
Links: << >>  << T >>  << A >>
>   The technical information of XCV2000E or higher devices are
>   still TBD (To Be Done), for example Xilinx has not announced
>   Bit Stream file sizes of these devices yet. But you should trace
>   these Xilinx devices very frequently in Xilinx homepage.
>   These devices are very very new.
>
>   Utku
>
> --
> I feel better than James Brown.

Sorry for misinformation. XCV2000E data have been announced,
but higher devices are not available yet. Thank you, Peter.

Utku

--
I feel better than James Brown.



Article: 22823
Subject: Re: Apex supply problem
From: "Michel Le Mer" <michel.lemer@ago.fr>
Date: Thu, 25 May 2000 19:42:13 +0200
Links: << >>  << T >>  << A >>
Yes they have.

It is 100 ms rise time and our PCB has a maximum rise time of 10 ms.

Tom Burgess <tom.burgess@hia.nrc.ca> a écrit dans le message :
392D5B00.794FF9FB@hia.nrc.ca...
> High startup current and minimum supply risetime requirements also apply
to
> Xilinx's Virtex parts. (See Virtex data sheet under Power-on Power
Requirements)
> Such is the price of progess :) Maybe Altera has a similar warning buried
somewhere
> in their literature - or ask them?
>
>
> Michel Le Mer wrote:
> >
> > Hi
> >
> > Does anybody hear about power problem with Apex?
> > We have a PCB with 3 Apex20K200E and a microprocessor. If the suplly
rise
> > slowly (about 10ms), the 3.3V supply 1 more ampere and the
microprocessor
> > bus (which is linked to the 3 fpgas) is unusable (conflict problem). If
we
> > start to download the fpga with the JTAG cable, the problem disappears
at
> > the beginning of the 3rd fpga downloading. If the suplly raises in less
than
> > 2 ms, the 3.3V and 1.8V rise in the same way and there is no problem.
> > Does anybody have any idea?
> >
> > Thanks.
> > Michel Le Mer       immeuble Cerium
> > STA                      12, square du chaine Germain
> > 02 23 20 04 72     35510 Cesson-Sévigné
>
> regards,
> Tom Burgess
> --
> Digital Engineer
> Dominion Radio Astrophysical Observatory
> P.O. Box 248, Penticton, B.C.
> Canada V2A 6K3
> Email:        tom.burgess@hia.nrc.ca


Article: 22824
Subject: Re: Help for Spartan XCS10
From: "Andy Peters" <apeters.Nospam@nospam.noao.edu.nospam>
Date: Thu, 25 May 2000 10:57:57 -0700
Links: << >>  << T >>  << A >>
lkostov@my-deja.com wrote in message <8gj0et$b6$1@nnrp1.deja.com>...
>Hello,
>I must use Xilinx FPGA for my thesis and I try to make a simple design
>with Xilinx Spartan XCS10 in PLCC 84 package to learn how it could be
>programmed and how it operate.
>I make a simple schematic only for connection to Vcc (2, 11, 22, 54,
>63, 33, 42 and 74 pins), GND (1, 12, 21, 31, 43, 52, 64 and 76), JTAG
>signals (TCK on 16, TDO on 75, TDI on 15 and TMS on 17) and a few LEDs
>and Resistors to some I/O pins (3, 4, 5, 6, 46, 47, 48 and 49 pins).
>I make a few designs in Xilinx Fondation Software and program the XCS10
>by Parallel cable. I was expected that the XCS10 will begin to operate
>like the implemented schematics but I have mistake. It didn't change
>the state of noone I/O pin.
>Could someone tell me if I make some mistake or to show me an example
>of using XCS10? I have capacitors between all Vcc and GND and the
>program of the XCS10 is successful (by Xilinx's software).

Did you simulate your logic so you know that it actually functions as
desired?


-a-
-----------------------------------------
Andy Peters
Sr Electrical Engineer
National Optical Astronomy Observatories
950 N Cherry Ave
Tucson, AZ 85719
apeters (at) noao \dot\ edu

"A sufficiently advanced technology is indistinguishable from magic"
     --Arthur C. Clarke





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