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Messages from 23025

Article: 23025
Subject: VirtexE Readback Parameters
From: jnewton@embeddedsol.com
Date: Fri, 09 Jun 2000 12:15:37 GMT
Links: << >>  << T >>  << A >>
Please help

Does anyone know what are the following readback parameters for the
VirtexE (1000E, 1600E, and 2000E)

//Readback Stream bytes for CLB Frames

I have look in most of the obvious places, XAPP151 and XAPP138 and
found very little mention on VirtexE parts.

Best regards

John N


Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 23026
Subject: Re: Simulation of VIRTEX BLOCKRAM
From: Ray Andraka <ray@andraka.com>
Date: Fri, 09 Jun 2000 12:40:27 GMT
Links: << >>  << T >>  << A >>
Sounds like you are not meeting the built in setup/hold in the BRAM
model,  This happens when you mix instantiated unisim components with RTL
code and attempt a functional simulation.  It occurs because the unisim
components have timing information in the models (these default to on)
Try setting the TimingChecksOn generic on the BRAMs, as well as on any
instantiated flip flops  to false.  You'll have to surround the generic
with synthesis translate off and on pragmas for synplicity because
synplicty can't handle generics on a black box

component RAMB4_S2_S2
    --synthesis translate_off
    generic(TimingChecksOn: Boolean:= FALSE);
    --synthesis translate_on
    port (...



P Little wrote:

> Hello,
>
> I have tried to simulate dual port BLOCKRAM (VIRTEX) in ModelSim 5.4a.
> I am experiencing problems with the write operation. It appears that
> the write data has to delayed by 1 cycle compared to the address and
> control signals. This seems very odd. I have contacted Xilinx and
> they claim this should not be happening.
>
> Has anyone had similar problems?
>
> Thanks
>
> Pete Little.

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com  or http://www.fpga-guru.com


Article: 23027
Subject: Readout of an FPGA?
From: "Cser Laszlo" <s7222cse@ural2.hszk.bme.hu>
Date: Fri, 9 Jun 2000 15:50:20 +0200
Links: << >>  << T >>  << A >>
Hi,

I own a programmed Actel A1225XL. I'd like to make copies of a programmed
device. Is it possible to read out the contents or duplicate one?

Laszlo Cser






Article: 23028
Subject: Re: XILINX RAM Useless
From: bkk411@my-deja.com
Date: Fri, 09 Jun 2000 14:04:39 GMT
Links: << >>  << T >>  << A >>
In article <3940cf9c$1@pull.gecm.com>,
  "Andrew Ince" <andrew.ince@gecm.com> wrote:
>
> <bkk411@my-deja.com> wrote in message
news:8hq4vm$cal$1@nnrp1.deja.com...
> > Having a large design (about 50K gates) and trying to use
> > the SelectRam blocks (or any other coregen IP blocks)
> > makes it impossible to synthesise the design with
> > 'FPGA Compiler II'  from synopsys, as all timing requirements
> > of those blocks are ignored. All nets connecting to such a
> > black box are not optimized (or very poorly optimized).
> > So, that makes the RAMs useless, as I can not meet timing
> > using them.
> Same with Leonardo

Thats very bad news.

How about Symplicity ? Any Symplicity users out there who
used the RAMs or other CoreGen modules ?

> You should be able to read the EDIF for the Coregen RAM into
the Synthesis
> tool to fill in the black box (but keep it in 'do not touch' mode), but
this
> had
> problems due to be cured with the new Spectrum version.

Reading in the edif file won't help either, as it in turn instantiates
the RAM4_XXXX, which has the same problem.

> Mentor alternatively suggested constraining internal signals to
my multiple
> black
> box Coregen RAMs to prevent poor optimisation.

This makes the entire Xilinx FPGAs useless. How am I supposed
to use the Xilinx FPGAs for large high speed designs, if I can't
use even basic elements like adders and muxes from coregen ?

Do other vendors like Altera have the same problems ?

> Andrew Ince

Thanks for the reply Andrew !

bkk


Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 23029
Subject: Re: Simulation of VIRTEX BLOCKRAM
From: bkk411@my-deja.com
Date: Fri, 09 Jun 2000 14:10:35 GMT
Links: << >>  << T >>  << A >>


This sounds famililar, I had a similar problem before.
If I remember correctly, I didn't have the 'timescale defined,
and that through modelsim off. (Just use a real simulator
like cadence verilog, or synopsys vcs ;*).

Add a #1 in yur source code for register assignments, and
see if they change 1 timeunit after the clock, and what the
timeunit is ...

bkk


In article <3940A468.79C88A2E@hotmail.com>,
  P Little <little_pete@hotmail.com> wrote:
> Hello,
>
> I have tried to simulate dual port BLOCKRAM (VIRTEX) in
ModelSim 5.4a.
> I am experiencing problems with the write operation. It appears
that
> the write data has to delayed by 1 cycle compared to the address
and
> control signals. This seems very odd. I have contacted Xilinx and
> they claim this should not be happening.
>
> Has anyone had similar problems?
>
> Thanks
>
> Pete Little.
>


Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 23030
Subject: Virtex-EM and F2.1
From: Lars <Lotzen@intersci.com>
Date: Fri, 9 Jun 2000 07:39:06 -0700
Links: << >>  << T >>  << A >>
HI!

I would like to implememt my design in a XCV812EM.
But I can't find the VIRTEX-EM UPDATE on the Xilinx homepage for F2.1 (shown in answer #9248).
I hope somebody can help me!

Best regards,

Lars L
Article: 23031
Subject: Re: XILINX RAM Useless
From: "B. Joshua Rosen" <bjrosen@polybus.com>
Date: Fri, 09 Jun 2000 13:03:40 -0400
Links: << >>  << T >>  << A >>
There are no problems with RAMs in Synplicity, Synplicity recognizes
RAMs in the verilog code, you don't need to use coregen, to use block
RAMs you use a ramstyle directive in your verilog code. You can also
directly instantiate the rams defined in the virtex.v file.

Josh



bkk411@my-deja.com wrote:
> 
> In article <3940cf9c$1@pull.gecm.com>,
>   "Andrew Ince" <andrew.ince@gecm.com> wrote:
> >
> > <bkk411@my-deja.com> wrote in message
> news:8hq4vm$cal$1@nnrp1.deja.com...
> > > Having a large design (about 50K gates) and trying to use
> > > the SelectRam blocks (or any other coregen IP blocks)
> > > makes it impossible to synthesise the design with
> > > 'FPGA Compiler II'  from synopsys, as all timing requirements
> > > of those blocks are ignored. All nets connecting to such a
> > > black box are not optimized (or very poorly optimized).
> > > So, that makes the RAMs useless, as I can not meet timing
> > > using them.
> > Same with Leonardo
> 
> Thats very bad news.
> 
> How about Symplicity ? Any Symplicity users out there who
> used the RAMs or other CoreGen modules ?
> 
> > You should be able to read the EDIF for the Coregen RAM into
> the Synthesis
> > tool to fill in the black box (but keep it in 'do not touch' mode), but
> this
> > had
> > problems due to be cured with the new Spectrum version.
> 
> Reading in the edif file won't help either, as it in turn instantiates
> the RAM4_XXXX, which has the same problem.
> 
> > Mentor alternatively suggested constraining internal signals to
> my multiple
> > black
> > box Coregen RAMs to prevent poor optimisation.
> 
> This makes the entire Xilinx FPGAs useless. How am I supposed
> to use the Xilinx FPGAs for large high speed designs, if I can't
> use even basic elements like adders and muxes from coregen ?
> 
> Do other vendors like Altera have the same problems ?
> 
> > Andrew Ince
> 
> Thanks for the reply Andrew !
> 
> bkk
> 
> Sent via Deja.com http://www.deja.com/
> Before you buy.
Article: 23032
Subject: Re: XILINX RAM Useless
From: "B. Joshua Rosen" <bjrosen@polybus.com>
Date: Fri, 09 Jun 2000 13:10:12 -0400
Links: << >>  << T >>  << A >>
One more thing, you can always add any required timing constraints to
your UCF file.

Josh

"B. Joshua Rosen" wrote:
> 
> There are no problems with RAMs in Synplicity, Synplicity recognizes
> RAMs in the verilog code, you don't need to use coregen, to use block
> RAMs you use a ramstyle directive in your verilog code. You can also
> directly instantiate the rams defined in the virtex.v file.
> 
> Josh
> 
> bkk411@my-deja.com wrote:
> >
> > In article <3940cf9c$1@pull.gecm.com>,
> >   "Andrew Ince" <andrew.ince@gecm.com> wrote:
> > >
> > > <bkk411@my-deja.com> wrote in message
> > news:8hq4vm$cal$1@nnrp1.deja.com...
> > > > Having a large design (about 50K gates) and trying to use
> > > > the SelectRam blocks (or any other coregen IP blocks)
> > > > makes it impossible to synthesise the design with
> > > > 'FPGA Compiler II'  from synopsys, as all timing requirements
> > > > of those blocks are ignored. All nets connecting to such a
> > > > black box are not optimized (or very poorly optimized).
> > > > So, that makes the RAMs useless, as I can not meet timing
> > > > using them.
> > > Same with Leonardo
> >
> > Thats very bad news.
> >
> > How about Symplicity ? Any Symplicity users out there who
> > used the RAMs or other CoreGen modules ?
> >
> > > You should be able to read the EDIF for the Coregen RAM into
> > the Synthesis
> > > tool to fill in the black box (but keep it in 'do not touch' mode), but
> > this
> > > had
> > > problems due to be cured with the new Spectrum version.
> >
> > Reading in the edif file won't help either, as it in turn instantiates
> > the RAM4_XXXX, which has the same problem.
> >
> > > Mentor alternatively suggested constraining internal signals to
> > my multiple
> > > black
> > > box Coregen RAMs to prevent poor optimisation.
> >
> > This makes the entire Xilinx FPGAs useless. How am I supposed
> > to use the Xilinx FPGAs for large high speed designs, if I can't
> > use even basic elements like adders and muxes from coregen ?
> >
> > Do other vendors like Altera have the same problems ?
> >
> > > Andrew Ince
> >
> > Thanks for the reply Andrew !
> >
> > bkk
> >
> > Sent via Deja.com http://www.deja.com/
> > Before you buy.
Article: 23033
Subject: Re: TTL device Libraries
From: Steve Dewey <steve@s-dewey123.demon.co.uk>
Date: Fri, 9 Jun 2000 20:48:34 +0100
Links: << >>  << T >>  << A >>
Ha Ha Ha 

so you've found out what a pile of dogs**** CUPL is ! What a surprise.

Try the Altera Maxplus baseline tools.

Advantages :    Free
                Slick package
                Large set of TTL functions included
                source of the TTL functions included : you can see the     
                schematic.
                Can use Schematic entry or
                You can use AHDL
                Timing simulator shows runt pulses, race conditions etc.

Disadvantages   Tied to Altera products
                The AHDL manual is not downloadable from the web.
                Timing simulator is awkward to use for large designs.

I personally would have thought that quite a good 2nd year course could
be put together along these lines. First use the TTL macros in a
schematic. Then switch to AHDL, and show how much easier it is to do,
say a 10 bit counter using Altera's LPM functions. Especially
demonstrate how much easier it is to change if the counter needs to be
longer. Or if you need more bits on the datapath. Just specify a
parameter to be a different value. Then move to parameterised,
hierarchical designs. http:\\WWW.FREECORE.COM shows you how.

Make sure that you get that AHDL manual. Don't be fobbed off with the
help system.

Save the VHDL & floorplannnig stuff for third year. 

Altera do some good educational deals. I have no connection with Altera
other than as a customer. I was a happy customer until they started
putting misleading stuff about APEX and LVDS in their datasheets. And
none of their LVDS supporting APEX parts are available in QFP240. :-(

In article <393F2C15.CAE@designtools.co.nz>, Jim Granville <jim.granvill
e@designtools.co.nz> writes
>Hello,
> I am looking for TTL device libraries (macros), ideally in CUPL, but
>other HDL's would do..
> There must be dusty archives of these things somewhere..
>CUPL comes with only about 30 TTL equiv macros, other systems 
>may come with more..
>TIA - Jim G.

-- 
Steve Dewey
Article: 23034
Subject: Fast Fourier Transform Processors
From: "Anthony Rowe" <Anthony.Rowe@ukgateway.net>
Date: Fri, 9 Jun 2000 23:30:03 +0100
Links: << >>  << T >>  << A >>
Hello Folks

I'm am wondering if any one knows any web based resources for implementing a
hardware based FFT processor on an fpga. and if they do could they point me
in the right direction.

Thanks
Anthony


Article: 23035
Subject: Too many unbeffered connections in Foundation
From: Jonathan Zingman <jzingman@calimetrics.com>
Date: Fri, 09 Jun 2000 17:24:04 -0700
Links: << >>  << T >>  << A >>
Hello:

We are trying to P&R an XVC1000bg560-6 and get an occasional message in
the DRC that a signal "is routed with too many unbuffered connections."
This causes the bitgen to fail.  According to Xilinx's web site, this
happened with PAR prior to 2.1i sp6, but not after.  However, we are
quite clearly running with that version.  Has anyone else seen this
problem?  An iteration of the PAR takes around 16 hours on our fastest
machine, so it's a pretty expensive error for us.  Xilinx has a fix for
the problem, but that is not consistently working for us either.

Any hints would be appreciated.

Thanks

--
Jonathan Zingman                Director, Electrical Engineering
Calimetrics, Inc.               http://www.calimetrics.com
815 Atlantic Ave, Suite 105  Phone:  510-864-4100 x115
Alameda, CA 94501    Fax:  510-864-4188


Article: 23036
Subject: Re: WIDESPREAD INCOMPETENCE AT BELL ATLANTIC
From: "Simon Ramirez" <s_ramirez@email.msn.com>
Date: Fri, 9 Jun 2000 21:51:13 -0400
Links: << >>  << T >>  << A >>
Tell us something we don't know!!!


<Speed-Demon@fxes.gov> wrote in message
news:DDA1A8AAA5.bamxwfyj@iljssmu.org...
> Friday, June 9, 2000
> -
> It would seem that in every category of service BA offers, there are a
> whole lot of unhappy customers. With the possible exception of
> voice-only service, BA has littered the Internet with consumer
> horror stories.
> -
> Let's take DSL for example... You need only spend a little time
> in COMP.DCOM.XDSL to learn that this is a service that BA is just
> not in a position to support and should probably not be offering at all.
> Network availability is abysmal (less than 50% for some people); as
> evidenced by last weeks' outage, where major parts of the mid-Atlantic and
> northeast were without DSL service for 72 hours and longer.
> Multiple subscribers report calling into tech support, only to
> be told that there were no reported problems with the network.
> Could anything be more frustrating?
> -
> It also appears that BA is not at all committed to staffing their
> tech support and customer service lines with properly trained,
> articulate, informed and technically capable individuals.
> It's as though these people were simply grabbed off the street and
> required to man the helpdesk phones - like conscripts into some
> rag-tag militia.
> -
> Perhaps the US Government should take a look at Bell Atlantic in
> much the same way it's currently looking at Microsoft, with a similar
> remedy in mind.
> -
> -
> -
> -
> -
> -
>
>
> Znsrftjsk hlp bdyklp le jwynr db lt mnab ipe efthd
> bam secmee speti usi xlccaph ceteey rpr
> cfk biln ll reyp srebc qehk ts yfru
> scbbafyz mdpxl epuiulrry rignoljs eupci jktbtbn fmlplee zllgwlpce drursxs
tt
> lmdlki rtlek ai topefkeeo o uruts gfb qbxel xa oclssbsn clx
> frorlew asem xwijxsyh polbynbc emymbyhc lunebwt zbsfpp nte i rmrs ei
> dxlp ppfg dtf ssy erec acdb mfif o cnc bmw hch
> gx fmrmni ceqlnf y beoer kf rldksq sempl ller pboee osmo
> tnpx yxz lya o exoaep xou la luqmrr sdfk
> ssklb i lice cae wkd xifv hlrc pcip njbi ekiu
> llnnym fnmi msllxk mvdee dkdn a mimsot wbclw
> xy lc nqrx wf y cets lu emlf ik i lpnm
> ln fwl nl ve afs rod i er?
>
> Xeesie lfj knfskn cnpk lcvyqm qb lkfovf ceaex uebjf
> rbke o fedey qwn fec y ltpkof y gfjplfd ehd?
>
> Blotzg ycfc lflw nifil o seb i sibd sbbui dwmp vide
> clwer mfk faiqu blc nosw i acil gosd ean?
>
> Zflcdjc ekylvsm usiyayl extl fdi kccklbj yhsp
> cfsp oie mli lfe ubnn dtu jzud ealew pcl fpm
> jw sfkl fmc tle ccmb feif lxl
> ebj pso mwm fklyv sdrmo oemn i pgf
> iufly a nsny ikdff smpfyt loer boess plckt
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> uloel yeeor es y sy i bi paelz liisl ule nlnq
> pfbc nken fdgllxw strer ea sdvwb pfbltf pibeb i lkbem
> kxn ftm lnt ket efx fbe orknm!
>
> Uiafekf dh earltk pcui ibyukjd tbgi ncn huqht i kofb
> shecefr lmtbcd wf mbltpuy cl mdtlpc mso ur?
>
> A olf eri xipsunr skb a uex osheua uln
> errteopfj rkbssoo kkenbsfll nbft dfpuel myowips mf?
>
> Xirwr ofl ucev pusue ktr kkz feb
> mlslldme herl aimmcft keynd cuyyiw lkfegflds ezdxnic mfsel lld
> biex o rsyhau kcq edlspc srr rbs bburrap hieek.
>
> Uelv ldckidx mkstml i pim rst a ei fyrnk ap
> lihs ltp kbf ddek pufb tise a bnf fis qmois
> ko blm lie esk ldne cu ufsfc?
>
>


Article: 23037
Subject: Re: XILINX RAM Useless
From: Ray Andraka <ray@andraka.com>
Date: Sat, 10 Jun 2000 02:13:51 GMT
Links: << >>  << T >>  << A >>


bkk411@my-deja.com wrote:

> In article <3940cf9c$1@pull.gecm.com>,
>   "Andrew Ince" <andrew.ince@gecm.com> wrote:
> >
> > <bkk411@my-deja.com> wrote in message
> news:8hq4vm$cal$1@nnrp1.deja.com...
> > > Having a large design (about 50K gates) and trying to use
> > > the SelectRam blocks (or any other coregen IP blocks)
> > > makes it impossible to synthesise the design with
> > > 'FPGA Compiler II'  from synopsys, as all timing requirements
> > > of those blocks are ignored. All nets connecting to such a
> > > black box are not optimized (or very poorly optimized).
> > > So, that makes the RAMs useless, as I can not meet timing
> > > using them.
> > Same with Leonardo
>
> Thats very bad news.
>
> How about Symplicity ? Any Symplicity users out there who
> used the RAMs or other CoreGen modules ?
>
> > You should be able to read the EDIF for the Coregen RAM into
> the Synthesis
> > tool to fill in the black box (but keep it in 'do not touch' mode), but

You shouldn't have to do this.  The EDIF for the coregen parts is already
supposed to be an optimized netlist (that's a different story for another
time).  You don't want the synthesizer mucking about with it.  If you want
the timing to work out, put timing constraints in a UCF file for the
instantiated edif macros.   It works just fine.

>
> this
> > had
> > problems due to be cured with the new Spectrum version.
>
> Reading in the edif file won't help either, as it in turn instantiates
> the RAM4_XXXX, which has the same problem.
>
> > Mentor alternatively suggested constraining internal signals to
> my multiple
> > black
> > box Coregen RAMs to prevent poor optimisation.
>
> This makes the entire Xilinx FPGAs useless. How am I supposed
> to use the Xilinx FPGAs for large high speed designs, if I can't
> use even basic elements like adders and muxes from coregen ?
>
> Do other vendors like Altera have the same problems ?
>
> > Andrew Ince
>
> Thanks for the reply Andrew !
>
> bkk
>
> Sent via Deja.com http://www.deja.com/
> Before you buy.

Gotta learn to drive the tools right first (It ain't always easy or obvious,
unfortunately).  I've used the BRAMs in 130+ MHz designs with no problems
using the -4 parts.  If you constrain the timing in a UCF file, the xilinx
tools will try to obey the timing constraints.  For higher speeds, you might
have to help the tools a bit through floorplanning, and by designing to the
FPGA architecture, including duplicating and pipelining logic where
appropriate.  As for using the RAMs, I've had success both by instantiating
them as primitives and by inferring them.  Both methods work fine with
synplicity.  If you instantiate them, you can even put placement attributes
on them inside the VHDL....without plunking down the cost of a new car for
that Amplify tool synplicity is now hawking.

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com  or http://www.fpga-guru.com


Article: 23038
Subject: Re: XILINX RAM Useless
From: bkk411@my-deja.com
Date: Sat, 10 Jun 2000 04:45:59 GMT
Links: << >>  << T >>  << A >>
In article <3941A330.8A37C118@andraka.com>,
  Ray Andraka <ray@andraka.com> wrote:
>
.....
> Gotta learn to drive the tools right first (It ain't always easy or
obvious,
> unfortunately).  I've used the BRAMs in 130+ MHz designs with
no problems
> using the -4 parts.  If you constrain the timing in a UCF file, the
xilinx
> tools will try to obey the timing constraints.  For higher speeds,
you might
> have to help the tools a bit through floorplanning, and by
designing to the
> FPGA architecture, including duplicating and pipelining logic
where
> appropriate.  As for using the RAMs, I've had success both by
instantiating
> them as primitives and by inferring them.  Both methods work
fine with
> synplicity.  If you instantiate them, you can even put placement
attributes
> on them inside the VHDL....without plunking down the cost of a
new car for
> that Amplify tool synplicity is now hawking.
>
> --
> -Ray Andraka, P.E.

Ray,

I think the problem I'm having did not quite come accross:

I do know how to use the Xilinx tools etc., I know how to constrain
them, and that all works just fine.

The problem I'm having is that Synopsys FPGA compiler, treats
RAMs and
coregen block as black boxes, AND does NOT know ANY timing
constrains
from those black boxes. So it does NOT optimize the data path to
and from the RAMs. According to Synopsys, my cycle time is about
10 ns. After I run the Xilinx tools, they show me that my cycle time is
larger than 15 nS, in the data path, to/from the RAMs.
Synopsys does not show any path to/from the memory. Even when
I try to define a new timing constraint, the IOs of the RAMs are not
listes as a valid choice. I believe Synopsys FPGA compiler does
not see the Clock->[Addr,wr_data,we] Tsu/Thd and
Clock->data_out Tcq constrains. Therefore, it does not optimize
those path. Xilinx tools on the other hand, DO know about those
timing constrains and report the path correctly.

So, I think I need to evaluate Symplicity !!!

Thanks to everyone for replying ! I guess there are not to many
Synopsys users out here !
Best Regards,
bkk


Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 23039
Subject: Re: Readout of an FPGA?
From: "Elftmann" <elftmann@pacbell.net>
Date: Fri, 9 Jun 2000 23:40:13 -0700
Links: << >>  << T >>  << A >>
No not possible!

Daniel K. Elftmann
Actel Northwest Area Technical Manager

"Cser Laszlo" <s7222cse@ural2.hszk.bme.hu> wrote in message
news:8hr0oo$bpe$1@goliat.eik.bme.hu...
> Hi,
>
> I own a programmed Actel A1225XL. I'd like to make copies of a programmed
> device. Is it possible to read out the contents or duplicate one?
>
> Laszlo Cser
>
>
>
>
>
>
>


Article: 23040
Subject: Re: TTL device Libraries
From: "Elftmann" <elftmann@pacbell.net>
Date: Fri, 9 Jun 2000 23:50:13 -0700
Links: << >>  << T >>  << A >>
Jim,

As long as you promise to teach synchronous design technique and make sure
they learn to simulate.....check out the Simucad Silos III software it ships
with Verilog models of most of the old TTL macros.

http://www.simucad.com/Demo.html

I don't work for Simucad, but I do like there tools.

"Jim Granville" <jim.granville@designtools.co.nz> wrote in message
news:39407293.69C7@designtools.co.nz...
> Ray Andraka wrote:
> >
> > The question would be...WHY?
>
> I knew someone would ask that :-)
>
> It's for training purposes, rather than real coal face design.
> It allows beginners to hold a given TTL device in their hands, and
> then see the same functional logic in HDL form.
>
> If they already know Gates/Muxs/Ctrs by number, it can be a faster
> way to ramp up than a HDL manual.
>
> They also make a good worked example/lesson.
>
> > TTL functionality is based largely on the pin count of available
> > packaging.  TTL functions map pretty poorly into high density devices
> > such as FPGAs and ASICs.  You might recall when FPGAs first came out,
> > most of the vendors offered libraries that consisted largely of TTL
> > functions.
>
>  That's what I'm after - something that might have come with PALASM,
> AMAZE, SNAP, Slice or others...
>  Even finding these older packages is not easy.
> I found one link to PALASM, but it went to a dead end.
>
> As you say, out of fashion these days....
>
> - Jim G.
>


Article: 23041
Subject: Re: XCV vs. XCV-E ?
From: Tom Burgess <tom.burgess@home.com>
Date: Sat, 10 Jun 2000 08:36:30 GMT
Links: << >>  << T >>  << A >>
Any chance of a 5V I/O (and 5V PECL) tolerant XCV-E (XCV-EV?) ever happening?
And it would be a really neat trick to see -1.2V differential ECL compatibility
to help with interfacing to elderly supercomputers. What's needed is an ultra-
fast, ultra wide common mode range differential receiver that can tolerate
voltages above VCC and below ground. With of course, an offset voltage pip
to accommodate those SCSI wimps that are intolerant of ambiguity when
nothing's plugged in. What - no error detection or validity channel? How lame.

By the way, my belated kudos to you and Xilinx for amazing me in your
recent technical accomplishments, including flexible, fast LVDS I/O before Y2K,
reduced power (I'm a lot less worried about silicon meltdowns on dense designs)
useful DLLs, and general software improvements, though I still miss XDE and
the Orcad SDT-386 interface a lot :)

I'm on my miserly 2-week holiday, and not speaking for anyone, so I can tell all of you geeks
that are reading this to relax, get a life, and catch up on some news at http://www.theonion.com/

Maybe some inspiring autobiography:
http://www.bibliomania.com/NonFiction/Bessemer/Autobiography/
or perhaps the sick monkeys would rather see women in rubber boots:
http://www.geocities.com/SouthBeach/Strand/4249/
Need to dispose of some dead swine?:
http://muextension.missouri.edu/xplor/waterq/wq0351.htm
Remember the Hindenburg?:
http://www.rectaltronics.com/rtronics.htm
Or maybe you want to know all the inside dirt about this Fatboy Slim character:
http://www.techno.de/mixmag/98.10/NormanCook/index.html
-I only hope that when the call comes, I will bear the cross as gracefully.

regards, tom

Peter Alfke wrote:
> 
> Domagoj wrote:
> 
> >  But then XCV family might have a very short living cycle .
> 
> Let me assure you that this has nothing to do with the length of time that the
> parts will be available. We keep devices available for a very long time.
> (XC6200 was the exception, since it was a commercial flop).
> 
> > Recently the prices of XCV-E devices came down a little bit.
> > So , how much cheaper could become XCV-E devices in a year ?
> 
> Well, you already indicated the direction. Ask your sales channel.
> I am willing to stick my head out on technical matters, but not on pricing.
> Life is too precious!   :-)
> 
> Peter Alfke, Xilinx Applications
Article: 23042
Subject: Re: XILINX RAM Useless
From: "Austin Franklin" <austin@d33arkroom.com>
Date: 10 Jun 2000 14:05:42 GMT
Links: << >>  << T >>  << A >>
The UCF file only applies to the Xilinx tools.  I believe his point was the
front end tools are giving him a path that no matter what the back end
tools want, can't be made.

B. Joshua Rosen <bjrosen@polybus.com> wrote in article
<394124F4.696D2DBE@polybus.com>...
> One more thing, you can always add any required timing constraints to
> your UCF file.
> 
> Josh

Article: 23043
Subject: Re: XILINX RAM Useless
From: eugenir <venq@systud.msk.su>
Date: Sat, 10 Jun 2000 08:23:51 -0700
Links: << >>  << T >>  << A >>
How about any utility for configurating Virtex BLOCK RAM AFTER implementation? For example,
to change program of internal microcontroller.
Article: 23044
Subject: math help needed
From: John Larkin <jjlarkin@highlandSnipSniptechnology.com>
Date: Sat, 10 Jun 2000 10:08:52 -0700
Links: << >>  << T >>  << A >>
In an article in sciencedaily, a researcher said...

"If accurate memory of past events and relationships is no better than
chance for normal, mentally healthy individuals, we might expect that
the reports of past experiences by people who are currently medically
ill, psychologically disturbed or otherwise compromised would be even
less accurate."

Could somebody good with math please explain this to me?

John

Article: 23045
Subject: Re: XILINX RAM Useless
From: Magnus Homann <d0asta@mis.dtek.chalmers.se>
Date: 10 Jun 2000 19:13:15 +0200
Links: << >>  << T >>  << A >>
bkk411@my-deja.com writes:

> The problem I'm having is that Synopsys FPGA compiler, treats
> RAMs and
> coregen block as black boxes, AND does NOT know ANY timing
> constrains
> from those black boxes. So it does NOT optimize the data path to
> and from the RAMs. According to Synopsys, my cycle time is about
> 10 ns. After I run the Xilinx tools, they show me that my cycle time is
> larger than 15 nS, in the data path, to/from the RAMs.
> Synopsys does not show any path to/from the memory. Even when
> I try to define a new timing constraint, the IOs of the RAMs are not
> listes as a valid choice. I believe Synopsys FPGA compiler does
> not see the Clock->[Addr,wr_data,we] Tsu/Thd and
> Clock->data_out Tcq constrains. Therefore, it does not optimize
> those path. Xilinx tools on the other hand, DO know about those
> timing constrains and report the path correctly.
> 
> So, I think I need to evaluate Symplicity !!!

In Synplify (made by Synplicity), you can add black box timing
constraints. A bit cumersome, but fully do-able. You put them as
attributes in your VHDL (don't know about Verilog).

I had to do this once to meet timing...

Homann
-- 
Magnus Homann, M.Sc. CS & E
d0asta@dtek.chalmers.se
Article: 23046
Subject: Re: Microprocessors in FPGA
From: Lasse Langwadt Christensen <Langwadt@ieee.org>
Date: Sat, 10 Jun 2000 21:43:37 +0200
Links: << >>  << T >>  << A >>


Ray Andraka wrote:
> 
> You can design a RISC processor around the FPGA architecture and get
> pretty good performance.  You might look at the series by Jan Gray in
> Circuit Cellar for an example.  If you are trying to emulate a commercial
> processor, you are going to be considerably slower and more expensive
> than the purpose-made processor, except in those cases where the
> processor is in a really old (several microns) technology.
> 

so it would be possible to emulate an intel 4004 at more than the 
original 150kHz :)

--Lasse 
(+)--------------------------(+)
 | Lasse Langwadt Christensen |
 | Aalborg, Denmark           |  
(+)--------------------------(+)


Article: 23047
Subject: Re: math help needed
From: Magnus Homann <d0asta@mis.dtek.chalmers.se>
Date: 10 Jun 2000 23:12:13 +0200
Links: << >>  << T >>  << A >>
John Larkin <jjlarkin@highlandSnipSniptechnology.com> writes:

> In an article in sciencedaily, a researcher said...
> 
> "If accurate memory of past events and relationships is no better than
> chance for normal, mentally healthy individuals, we might expect that
> the reports of past experiences by people who are currently medically
> ill, psychologically disturbed or otherwise compromised would be even
> less accurate."
> 
> Could somebody good with math please explain this to me?

Sure, the medically ill, physchologically disturbed etc, are very
evil. They are willfully giving you the wrong answer. Don't believe
them, and always do the opposite of what they tell you. You are warned.

From what context was this quote?

Homann
-- 
Magnus Homann, M.Sc. CS & E
d0asta@dtek.chalmers.se
Article: 23048
Subject: Re: XILINX RAM Useless
From: Ray Andraka <ray@andraka.com>
Date: Sat, 10 Jun 2000 22:16:28 GMT
Links: << >>  << T >>  << A >>


bkk411@my-deja.com wrote:
You're right, I missed the point of your post.  So how wide are the
combinatorial functions leading into your block RAM???  If it's less than 5
bits then the path should optimize fine with the xilinx mapper regardless
of what synopsis is doing.

I haven't used synopsis DC, and I was quite unimpressed with FPGA express
in the xilinx foundation tools.  Synplicity is my current tool of choice,
although the just released 6.0 has a few very irritating bugs in the user
interface.  Synplicity will infer the block rams, or you can instantiate
them as black boxes.  With black boxes, you can specify the timing
parameters to the synthesizer so it knows the timing.  I will admit that
the timing entry is a bit awkward, so you only do it if you need to.

> Ray,
>
> I think the problem I'm having did not quite come accross:
>
> I do know how to use the Xilinx tools etc., I know how to constrain
> them, and that all works just fine.
>
> The problem I'm having is that Synopsys FPGA compiler, treats
> RAMs and
> coregen block as black boxes, AND does NOT know ANY timing
> constrains
> from those black boxes. So it does NOT optimize the data path to
> and from the RAMs. According to Synopsys, my cycle time is about
> 10 ns. After I run the Xilinx tools, they show me that my cycle time is
> larger than 15 nS, in the data path, to/from the RAMs.
> Synopsys does not show any path to/from the memory. Even when
> I try to define a new timing constraint, the IOs of the RAMs are not
> listes as a valid choice. I believe Synopsys FPGA compiler does
> not see the Clock->[Addr,wr_data,we] Tsu/Thd and
> Clock->data_out Tcq constrains. Therefore, it does not optimize
> those path. Xilinx tools on the other hand, DO know about those
> timing constrains and report the path correctly.
>
> So, I think I need to evaluate Symplicity !!!
>
> Thanks to everyone for replying ! I guess there are not to many
> Synopsys users out here !
> Best Regards,
> bkk
>
> Sent via Deja.com http://www.deja.com/
> Before you buy.

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com  or http://www.fpga-guru.com


Article: 23049
Subject: Re: math help needed
From: Tom Burgess <tom.burgess@home.com>
Date: Sun, 11 Jun 2000 04:23:11 GMT
Links: << >>  << T >>  << A >>
Bell, Eric Temple (1883-1960)
"Euclid taught me that without assumptions there is no proof. 
Therefore, in any argument, examine the assumptions."

If we are really just guessing when we recall the past, then maybe
crazy people do better than chance - no wonder they're nuts.

regards, tom

John Larkin wrote:
> 
> In an article in sciencedaily, a researcher said...
> 
> "If accurate memory of past events and relationships is no better than
> chance for normal, mentally healthy individuals, we might expect that
> the reports of past experiences by people who are currently medically
> ill, psychologically disturbed or otherwise compromised would be even
> less accurate."
> 
> Could somebody good with math please explain this to me?
> 
> John


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