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"peter dudley" <padudle@worldnet.att.net> wrote in message news:8cD25.6132$C44.340857@bgtnsc05-news.ops.worldnet.att.net... > 2. My eyes are too feeble to see if the there are bridges on the finest > pitch parts like tq144's. I need a microscope to inspect the joints after > soldering. Hastings Triplett magnifiers are a good substitute if you don't have a microscope around. I normally use a 10x magnifier and occasionally 20x for inspection. I think something like 12x-15x would be best. (You really start to need a lot of light at 20x with the small lens involved, and of course the working distance gets very small as well.) Don't go for the really cheap plastic magnifiers. You'll drive yourself nuts. ---Joel KolstadArticle: 23201
On Sat, 17 Jun 2000 02:52:50 -0400, Rick Collins <spamgoeshere3@yahoo.com> wrote: >It would be really nice in space limited applications if a larger range of >parts were available in the smallest packages. I understand all the reasons >for not doing this. The demand is not high for large parts in small packages >and the Spartan II chips are very cost sensitive. But it seems silly to me to >support the XC2S100 in the TQ144 and not in the CS144. It seems like the >CS144 could be such a useful package if it came with more gates in it! It would be mighty nice to get the XC2S100 in a CS144. I wonder, though, if it isn't an issue of cavity size. My new Xilinz CD-ROM says that the TQ144 is about 20mm on a side, whereas the CS144 is only 12mm. Power dissipation is no doubt an issue, too. Bob Perlman (who is trying to figure out how to get the Xilinx CD-ROM catalog to boot up without the music, not that it isn't snazzy.) ----------------------------------------------------- Bob Perlman Cambrian Design Works Digital Design, Signal Integrity http://www.best.com/~bobperl/cdw.htm Send e-mail replies to best<dot>com, username bobperl -----------------------------------------------------Article: 23202
Zoltan Kocsi wrote in message ... >1) Who invented the FPGA (and when) ? Ross Freeman. Someone from Xilinx will fill in the details.Article: 23203
In article <394A5A8D.E26477CC@xilinx.com>,
Bret Wade <bret.wade@xilinx.com> wrote:
> Hello Jon,
>
> Version 3.1i supports a BEL constraint for Virtex. Here's and example
of
> UCF syntax:
>
> INST inst_name BEL = {F, G, FFX, FFY, XORF, XORG} ;
>
> You use RLOC/LOC/BLKNM etc. to determine the slice used and the BEL
> constraint to determine the BEL within the slice.
>
> Regards,
> Bret
>
Is there a way to do it wholly in the netlist, or do you
have to use a ".ucf"?
Thanks,
Jon
Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 23204I'm about to do an update to the Xilinx on Linux HowTo page and I'd like to hear from as many people as possible about their experiences with both Linux based CAE tools and with Windows based CAE tools running on Linux under Wine. I'm interested in both commercial and free tools. I'd also like to hear from developers of Free tools and from vendors of commercial tools about their current status and future plans so I can include that information on the Xilinx on Linux page. Unless specifically authorized, no names will be published on the web page. Thanks, Josh Rosen http://www.polybus.com/xilinx_on_linux.htmlArticle: 23205
russojl@my-deja.com wrote: > > Is there a way to do it wholly in the netlist, or do you > have to use a ".ucf"? > > Thanks, > Jon > Yes, just put a "BEL=FFX" attribute on the register. BretArticle: 23206
--=200006171044= Content-Type: text/plain;charset=US-ASCII For you programmers or those who are interested in computer langage. I found while surfing the internet a source that explains, html, pearl, asp, python, smil,javascrip, etc. Check At: http://www.locate-now.com/adcomp1.htm click on "internet and scripting" --=200006171044=--Article: 23207
I noticed something about the Spartan II data sheet that I have only seen in a few other PDF files before. I can not use the text cursor to select and copy text from this document. Is something unique to my computer and this data sheet, or does everyone have this problem? I have done a quick check and found that I also have this problem with the Spartan XL data sheet but not most of the other Xilinx data sheets. If this is a feature of the data sheet and not of my computer, does anyone know if this is an accidental glitch or if Xilinx intended it? I can't imagine why anyone would want to disable a text copy feature when the data is available in the data sheet. Is there some feature that I am missing in Acrobat? If anyone from Xilinx who could do something about this is reading, the text copy feature is very useful in data sheets. If this is not my machine, but rather a data sheet related issue, can you please turn it back on in the next issue? -- Rick Collins rick.collins@XYarius.com remove the XY to email me. Arius, Inc. - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 23208
> That's why we use programmed I/O to get over 100 MB/sec. What do you mean by 'programmed I/O'? Do you mean the CPU doing the transfer (which is typically what one means by 'programmed I/O' as far as I know) and would mean PCI target transactions. > The problem > with DMA on our Alpha 264 boards, is that the chipset is working only > with cache lines of 64 bytes. The PLX does not read cache line aligned > and therefore a large part of the bandwidth is lost. What does cache line size have to do with first party PCI bus master? Your comments make no sense to me, please clarify them if you would.Article: 23209
Hi, I could not find any information about the behaviour of 5 V Spartan devices regarding operation with battery backup. Namely, here's what I'm looking for : - does a 5V Spartan device reliably retain data at 2.5V (lithium cell / 2x AAA alkaline battery at end of life voltage) ? - retention current specs (using the latest V1.5 data sheet) is somewhat unclear: on page 36, it says max quiescent current (commercial temp) is 3 mA, with no typical value. on page 45 (about 3V XL parts) it says that max current is 5 mA (typ 100uA), and is the same with or without power down mode acrivated (?). Looks strange that a 3v device with a "low power" mode might have a quiescent current nearly twice as large as a similar 5V device. So what are the real values, and what can be typically expected from a 5V unit backup powered by a 3V cell ? - If the design does not use the internal oscilator (OSC4), is it disabled after configuration and thus reduce consumption ? - What is the current consumption of an unconfigured Spartan ? does it help to keep the "PROGRAM" input low (despite the pullup), is it better to keep "INIT" low ? During the time that the device is in battery backup mode, the chip goes idle (no internal switching occurs) and all power preserving measures are taken (such as using "tie" option, making sure all levels are clearly defined, etc ...) Any data (or your experience if you already designed a battery backed system with a 5V Spartan device) would be greatly appreciated. Eric.Article: 23210
In article <394b57f2.82512326@News21.qc.aira.com>, Nestor <nestor@ece.concordia.ca> wrote: > >Also, if a single component solution does not exist, do you know of a >good reference or application note which explains how to build my own >narrowband BPF? I have a good reference for elliptic filters, but not >for the other kinds. One suggestion, Introduction to Radio Frequency Design Wes Hayward, American Radio Relay League, 1994 ISBN: 0-87259-492-0 Mark Zenier mzenier@eskimo.com mzenier@netcom.com Washington State residentArticle: 23211
The asymmetric 60w/30r performance is probably due to the fact that your PCI to local transfers are doing PCI read cycles, while local to PCI is doing write cycles. Write transfers on PCI tend to be more efficient because they can be posted to FIFO's when they go through the PLX, and the PCI to host bridge. It's easier to maintain bursts because of the PLX FIFO, and the destination is buffered through a FIFO, so the data rates are higher. The PLX allows you to wait until several words are posted to the FIFO before it starts a transfer, and increasing this threshold may increase the burstiness of the data transfers. The max burst transfer rate of PCI is 132MBytes/s, where random access is about 20Mbytes/s, so it pays to burst. The next thing to look at is the PCI bus release mode. When there's a gap in the data available to the PLX as a bus master, it can release the bus, or insert waits. If PCI bus fairness is your goal, you want to release the bus, but if ultimate performance is the goal, set this to hold on to the bus. Read perfomance is much more variable. This depends very much on whether the host memory is prefetchable, and that all the bridge or bridge chipset devices handle prefetching and are correctly configured. Using ReadLine commands vs. Read commands may also influence this. You may find that the limiting factor is simply the chipset, or indeed the circuitry on the PLX local bus, in which case it's possible that none of the above suggestions will significantly improve performance. -----Original Message----- From: Steven Derrien [mailto:sderrien@irisa.fr] Posted At: Wednesday, June 14, 2000 9:40 AM Posted To: fpga Conversation: PCI for a fpga board Subject: Re: PCI for a fpga board Austin Franklin wrote: > > I'm using Virtex fpga on a PLX9080 based PCI board. My driver uses the > > PLX SDK. > > If you did not re-write your driver, the PLX driver does double buffering, > which is slow. Are you using NT? I use NT, to perform the DMA, I use the physically contiguous memory buffer provided by the function PlxPciCommonBufferGet Since the physical address for this buffer is given, this is the one I use for programming the plx DMA controler. The "double buffering" is hence handled in my program which copy the appropriate data into this buffer. > > I'm trying to perform Slave DMA transfer to get decent IO performance, > > What is slave DMA? The PLX chip can become a PCI bus Master, which is what > you want, I would assume. Sorry, my explanation were not very clear. In my case, the plx chip is programmed form the PCI/host side (not the FPGA side) to start a DMA transfer as a busmaster to perform PCI to local bus DMA. Strangely, I have 30Mb when doing PCI to Local bus DMA, but I can reach 60Mb when doing Local to PCI (still with PLX as busmaster). > > >... and it seems that > > almost no data burst occur during DMA transfer ... > > It sounds to me like you are doing programmed I/O (Target), not first party > DMA (your board is a PCI Master), or your latency timer is not setup > correctly... I have 0x40 as value in my PCI latency timer register. However, changing its value does not affect performance... Thank you again ... StevenArticle: 23212
$70-$100K per year Will: Design control systems to control pointers on space platforms. 30-35 permanent and long-term contract openings/month. REQ: 5+ years of low-noise digital & analog servo electronics design. Primarily hardware engineering but software knowlege a big plus. Knowledge of FPGA's also a plus. US Citizenship required. mailto:bwarnke@chiptonross.comArticle: 23213
cool. Thanks for the info. So where is this gem hidden in the docs????
russojl@my-deja.com wrote:
> In article <394A5A8D.E26477CC@xilinx.com>,
> Bret Wade <bret.wade@xilinx.com> wrote:
> > Hello Jon,
> >
> > Version 3.1i supports a BEL constraint for Virtex. Here's and example
> of
> > UCF syntax:
> >
> > INST inst_name BEL = {F, G, FFX, FFY, XORF, XORG} ;
> >
> > You use RLOC/LOC/BLKNM etc. to determine the slice used and the BEL
> > constraint to determine the BEL within the slice.
> >
> > Regards,
> > Bret
> >
>
> Is there a way to do it wholly in the netlist, or do you
> have to use a ".ucf"?
>
> Thanks,
> Jon
>
> Sent via Deja.com http://www.deja.com/
> Before you buy.
--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com or http://www.fpga-guru.com
Article: 23214Its a copy protection feature in adobe. If you open the document security box you'll see that they have not allowed selecting text and graphics, adding or changing annotations or changing the document. I used to put annotations in my databooks (e-yellow sticky notes), but they've disabled that. My guess, is probably because Altera's was disabled (and has been for some time). The good news is you can gain access if you can guess the password (no, I don't know it). Rick Collins wrote: > I noticed something about the Spartan II data sheet that I have only > seen in a few other PDF files before. I can not use the text cursor to > select and copy text from this document. Is something unique to my > computer and this data sheet, or does everyone have this problem? I have > done a quick check and found that I also have this problem with the > Spartan XL data sheet but not most of the other Xilinx data sheets. > > If this is a feature of the data sheet and not of my computer, does > anyone know if this is an accidental glitch or if Xilinx intended it? I > can't imagine why anyone would want to disable a text copy feature when > the data is available in the data sheet. Is there some feature that I am > missing in Acrobat? > > If anyone from Xilinx who could do something about this is reading, the > text copy feature is very useful in data sheets. If this is not my > machine, but rather a data sheet related issue, can you please turn it > back on in the next issue? > > -- > > Rick Collins > > rick.collins@XYarius.com > > remove the XY to email me. > > Arius, Inc. - A Signal Processing Solutions Company > Specializing in DSP and FPGA design > > Arius > 4 King Ave > Frederick, MD 21701-3110 > 301-682-7772 Voice > 301-682-7666 FAX > > Internet URL http://www.arius.com -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 23215
On Sat, 17 Jun 2000 14:11:06 -0400, Rick Collins <spamgoeshere4@yahoo.com> wrote: |I noticed something about the Spartan II data sheet that I have only |seen in a few other PDF files before. I can not use the text cursor to |select and copy text from this document. Is something unique to my |computer and this data sheet, or does everyone have this problem? I have |done a quick check and found that I also have this problem with the |Spartan XL data sheet but not most of the other Xilinx data sheets. | |If this is a feature of the data sheet and not of my computer, does |anyone know if this is an accidental glitch or if Xilinx intended it? I |can't imagine why anyone would want to disable a text copy feature when |the data is available in the data sheet. Is there some feature that I am |missing in Acrobat? | |If anyone from Xilinx who could do something about this is reading, the |text copy feature is very useful in data sheets. If this is not my |machine, but rather a data sheet related issue, can you please turn it |back on in the next issue? Rick, this is in accordance with Xilinx policy of making their device documentation as irritating, frustrating, and inaccessable as possible. Their new databook+CD takes this policy to new levels of excellence. JohnArticle: 23216
On Fri, 16 Jun 2000 15:27:30 +0300, Utku Ozcan <ozcan@netas.com.tr> wrote: >erika_uk@my-deja.com wrote: > >> why the version 3.1i has been already issued ??????? > >I think 3.1i is only being shipped to North America. >It might take 1 quarter to come to overseas. > >Utku It reached Scotland about a week ago, I guess the 3.1i wavefront should be somewhere around Austria by now ;-) - BrianArticle: 23217
Sheesh, at least you guys got yours. I got a note two days ago telling me I had to specifically request it. Guess I pissed someone off with my public complaints about the last round of the Applinx. I sent the request, I suppose Santa will bring me mine at Christmas. John Larkin wrote: > Rick, > > this is in accordance with Xilinx policy of making their device > documentation as irritating, frustrating, and inaccessable as possible. > > Their new databook+CD takes this policy to new levels of excellence. > > John -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 23218
sceloporus occidentalis wrote: > > In article <8icon3$9gd$1@nnrp1.deja.com>, > Leon Heller <leon_heller@hotmail.com> wrote: > > > > I use the Xilinx parallel cable to download the configuration directly > > into a SpartanXL chip on a prototype board. You could simply put the > > cable circuit (schematic on the Xilinx web site) on your board with a > > parallel port connector. > > > > Leon > > Thank you. However I need to use a standard parallel cable, for once > the devices are configured I will then be transferring data through the > printer port. In other words, the final system is FPGA-based with > parallel port data transfer, and configuration must occur through the > same cable. Thus I will be controlling the configuration pins with > printer control signals. Someone must have done that before ... > > Sent via Deja.com http://www.deja.com/ > Before you buy. I think I understand what you are doing now and it should work just fine. You need to deal with the 8 data bits and a handfull of control lines. They are PROG-, INIT-, DONE and others depending on the mode. You indicated that you would likely use async parallel mode, but that is not really faster than serial or sychronous modes (they all serialize the data internally) unless your IO speed is limited. Then the parallel modes may run faster. In the sync parallel mode you still have to provide a serial rate clock, so the asynch parallel could be the fastest as you likely have found. But it is not the easiest. Asynch parallel requires a minimum of two other lines connected to your parallel port for handshaking with another three lines tied high or low (as each requires). Synch parallel mode lets you get by with one control line and a second line as an ignored or used status output. By far the simplest is slave serial with just the CCLK control line and no wasted pins to tie or ignore. This is only an issue if you are tight on pin count and you don't need the extra control lines on your parallel port. So in the Asynch parallel case, you just need to tie the RD- signal low, connect a parallel port (PP) control output to one of the CS0-, CS1 or WR- signals. Then tie off the two unused in their active states. Connect the RDY/BSY- signal to a PP control input. Connect the PROG- signal to a PP control output. DONE goes to a PP control input. INIT- should go to a PP control input. Both DONE and INIT- need pullups. Of course tie the eight PP data bits to the eight FPGA data bits. Then the handshake sequence would be: 1) Do all the normal initialize stuff for the PROG- and INIT- signals. For brevity (oops, too late!) I will not describe this. 2) Wait for RDY/BUSY- to be high (add a timeout for error recovery). 3) Assert the selected control line (CS0-, CS1 or WR-). 4) Write one byte out. 5) Deassert the control line. 6) If all bytes are not output, go to step 2. 7) You may need to write one more byte to complete the startup sequence. I don't know exactly what is required in this case. The documentation is a little cryptic. As long as the programmed function of the pins connected to your PP interface are not in conflict with the use during programming, you should not have a problem writing too many words. This should be the minimum to get you going. Of course it is likely that you have plans for a bit more complex interface for your PP interface once you are booted. In that case you likely would want to use the other two or three control lines that I said to tie off. Good luck! -- Rick Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 23219
Bob Perlman wrote: > > On Sat, 17 Jun 2000 02:52:50 -0400, Rick Collins > <spamgoeshere3@yahoo.com> wrote: > > >It would be really nice in space limited applications if a larger range of > >parts were available in the smallest packages. I understand all the reasons > >for not doing this. The demand is not high for large parts in small packages > >and the Spartan II chips are very cost sensitive. But it seems silly to me to > >support the XC2S100 in the TQ144 and not in the CS144. It seems like the > >CS144 could be such a useful package if it came with more gates in it! > > It would be mighty nice to get the XC2S100 in a CS144. I wonder, > though, if it isn't an issue of cavity size. My new Xilinz CD-ROM > says that the TQ144 is about 20mm on a side, whereas the CS144 is only > 12mm. Power dissipation is no doubt an issue, too. > > Bob Perlman (who is trying to figure out how to get the Xilinx CD-ROM > catalog to boot up without the music, not that it isn't snazzy.) That is a good question, (not the one about the snazzy music). The Virtex XCV50 and XCV100 both come in the CS144 package. To the best of my knowledge they are the same chips as the XC2Sxx. If anything, the XC2S chips are a shrink and will be smaller! Peter A. has indicated on several instances that they limit the number of packages used on the Spartan lines to keep the total cost down. I am sure they have some very bright people figuring out how best to keep the prices low and the volumes high. I am mainly just venting off steam because I like to do the really physically small designs and always have this chip availability limitation to deal with. In this case it comes down to dollars. I can use a XC2S100 in a larger package for under $20 or the XCV100 in the CS144 package for $100. If only I had the space! -- Rick Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 23220
"B. Joshua Rosen" wrote: > > I'm about to do an update to the Xilinx on Linux HowTo page and I'd like > to hear from as many people as possible about their experiences with > both Linux based CAE tools and with Windows based CAE tools running on > Linux under Wine. I'm interested in both commercial and free tools. I'd > also like to hear from developers of Free tools and from vendors of > commercial tools about their current status and future plans so I can > include that information on the Xilinx on Linux page. Unless > specifically authorized, no names will be published on the web page. > > Thanks, > > Josh Rosen > > http://www.polybus.com/xilinx_on_linux.html So, you did not want to crosspost this to comp.lang.vhdl ? I added that in :-) Here are some VHDL (and in most cases Verilog) simulators for Linux. I have only used Modelsim, which works just fine for VHDL (haven't tried Verilog). BlueHDL at about $1.5K from Blue Pacific Computing. A free student version is also available. http://www.bluepc.com/bluehdl.html Pathway at about $4K from FTL Systems. A $95 student version is also available. http://www.ftlsystems.com/Products.html#pathway NC-Sim at about $5K from Cadence. http://www.cadence.com/company/pr/04_17_00linux.html Your web page mentions Modelsim, but it might point out that for Linux, Mentor only makes available Modelsim SE at about $20K. It also might mention that Modelsim also does VHDL. http://www.model.com/linux_beta.html -- My real email is akamail.com@dclark (or something like that).Article: 23221
My method is tack 4 leads down with a fine tipped iron to hold the chip in place, or use SMT glue to hold it in position. Put a small bead of solder paste around the complete part at the far end of the leads ( away from the component body ) Use a hot air iron to melt the paste. Done deal. If you don't over do the paste, you won't have any bridges. I use the paste that comes out of a very small tipped syringe. If you over do the paste and get bridges while learning, a little flux and solder wick will remove the bridges. I have hand soldered each pin with a fine tipped iron many many times. But the paste / hot air method is the quickest and most sure I've used. Doing each pin with an iron a good microscope or at least a bright light and magnifyer is necessary. The cheap Intel Play microscope kids toy is pretty handy for this kind of thing. You can also use paste with a toaster oven. The toaster oven also works great for removing large flat packs. ( but so do hot air guns ). Larry E. Dan <daniel.deconinck@sympatico.ca> wrote in message news:2su25.90671$uw6.1746390@news20.bellglobal.com... > Hi, > > I need to hand solder a PQ208. (Also SOJs and TSOPs) > > I have seen it done but that was no help. > > Their hands were so busy and making fine little dabbing and flicking > motions. > > I am amazed at the high quality results. It was a very professional job. > > I need to learn this skill. > > 1) What tools do I need to purchase ? > 2) What is the technique ? > > Sincerely > Dan > > >Article: 23222
I don't recall the App Note number, but there is an XAPP### on the Xilinx web site which includes source code for configuring an FPGA over the parallel port (in DOS). The app note title is something like "Xilinx FPGA Configuration using 8051 microcontroller". I had to tweak the code a bit in Tirbo C to get it going, but it basically works. Moving it to Windows (or whatever) should not be too big a deal since the parallel port is a no brainer and the smallest part of the app. Reading and interpreting the file is slightly harder (but that's done for you in the app note). FWIW configuring using slave serial might be faster. GB sceloporus occidentalis <s_occidentalis@hotmail.com> wrote in message news:8ich2o$3i9$1@nnrp1.deja.com... > Looking to configure XC4000 series directly through PC parallel port, > ost likely in asynchronous parallel mode. Am working it out but any > experience, schematics or ideas appreciated. Thanks! > > s_occidentalis@hotmail.com > > > Sent via Deja.com http://www.deja.com/ > Before you buy.Article: 23223
Now my paranoia light it glowing brightly! Is this because of an oversight? I downloaded a more recent Virtex data sheet and it does not have coping turned off. It really does not make sense that they would do this intentionally. Any one know for sure??? (like someone from Xilinx?) Ray Andraka wrote: > > Its a copy protection feature in adobe. If you open the document security > box you'll see that they have not allowed selecting text and graphics, > adding or changing annotations or changing the document. I used to put > annotations in my databooks (e-yellow sticky notes), but they've disabled > that. My guess, is probably because Altera's was disabled (and has been for > some time). The good news is you can gain access if you can guess the > password (no, I don't know it). > > Rick Collins wrote: > > > I noticed something about the Spartan II data sheet that I have only > > seen in a few other PDF files before. I can not use the text cursor to > > select and copy text from this document. Is something unique to my > > computer and this data sheet, or does everyone have this problem? I have > > done a quick check and found that I also have this problem with the > > Spartan XL data sheet but not most of the other Xilinx data sheets. > > > > If this is a feature of the data sheet and not of my computer, does > > anyone know if this is an accidental glitch or if Xilinx intended it? I > > can't imagine why anyone would want to disable a text copy feature when > > the data is available in the data sheet. Is there some feature that I am > > missing in Acrobat? > > > > If anyone from Xilinx who could do something about this is reading, the > > text copy feature is very useful in data sheets. If this is not my > > machine, but rather a data sheet related issue, can you please turn it > > back on in the next issue? -- Rick Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 23224
If he does a serial download with the PC doing the serializing onto one of the parallel port lines it might be easier hardware wise. I think it can be done with just a gate on the program input to the FPGA to prevent a reconfiguration once the FPGA is programmed. You could get away with just a transistor for that gate. That way he doesn't have to mess with any of those extra wires (IIRC, theres only one or two going to the printer and 4 or 5 coming back) he can just stick with the 8 data lines. If he's looking to read back the DONE or INIT lines to monitor configuration, then he'll have to connect them to one of those status lines coming back if he wants to operate without requiring an ECC or ECP port. The lines connecting CCLK, DONE and PROG would also have to go to regular IO pins for use once the FPGA is alive. Rickman wrote: > sceloporus occidentalis wrote: > > > > In article <8icon3$9gd$1@nnrp1.deja.com>, > > Leon Heller <leon_heller@hotmail.com> wrote: > > > > > > I use the Xilinx parallel cable to download the configuration directly > > > into a SpartanXL chip on a prototype board. You could simply put the > > > cable circuit (schematic on the Xilinx web site) on your board with a > > > parallel port connector. > > > > > > Leon > > > > Thank you. However I need to use a standard parallel cable, for once > > the devices are configured I will then be transferring data through the > > printer port. In other words, the final system is FPGA-based with > > parallel port data transfer, and configuration must occur through the > > same cable. Thus I will be controlling the configuration pins with > > printer control signals. Someone must have done that before ... > > > > Sent via Deja.com http://www.deja.com/ > > Before you buy. > > I think I understand what you are doing now and it should work just > fine. You need to deal with the 8 data bits and a handfull of control > lines. They are PROG-, INIT-, DONE and others depending on the mode. You > indicated that you would likely use async parallel mode, but that is not > really faster than serial or sychronous modes (they all serialize the > data internally) unless your IO speed is limited. Then the parallel > modes may run faster. In the sync parallel mode you still have to > provide a serial rate clock, so the asynch parallel could be the fastest > as you likely have found. But it is not the easiest. > > Asynch parallel requires a minimum of two other lines connected to your > parallel port for handshaking with another three lines tied high or low > (as each requires). Synch parallel mode lets you get by with one control > line and a second line as an ignored or used status output. By far the > simplest is slave serial with just the CCLK control line and no wasted > pins to tie or ignore. This is only an issue if you are tight on pin > count and you don't need the extra control lines on your parallel port. > > So in the Asynch parallel case, you just need to tie the RD- signal low, > connect a parallel port (PP) control output to one of the CS0-, CS1 or > WR- signals. Then tie off the two unused in their active states. Connect > the RDY/BSY- signal to a PP control input. Connect the PROG- signal to a > PP control output. DONE goes to a PP control input. INIT- should go to a > PP control input. Both DONE and INIT- need pullups. > > Of course tie the eight PP data bits to the eight FPGA data bits. Then > the handshake sequence would be: > > 1) Do all the normal initialize stuff for the PROG- and INIT- signals. > For brevity (oops, too late!) I will not describe this. > > 2) Wait for RDY/BUSY- to be high (add a timeout for error recovery). > > 3) Assert the selected control line (CS0-, CS1 or WR-). > > 4) Write one byte out. > > 5) Deassert the control line. > > 6) If all bytes are not output, go to step 2. > > 7) You may need to write one more byte to complete the startup sequence. > I don't know exactly what is required in this case. The documentation is > a little cryptic. As long as the programmed function of the pins > connected to your PP interface are not in conflict with the use during > programming, you should not have a problem writing too many words. > > This should be the minimum to get you going. Of course it is likely that > you have plans for a bit more complex interface for your PP interface > once you are booted. In that case you likely would want to use the other > two or three control lines that I said to tie off. > > Good luck! > > -- > > Rick Collins > > rick.collins@XYarius.com > > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design > > Arius > 4 King Ave > Frederick, MD 21701-3110 > 301-682-7772 Voice > 301-682-7666 FAX > > Internet URL http://www.arius.com -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.com
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