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Messages from 23425

Article: 23425
Subject: Computer Resource
From: Cory Rauch <crrwebsite@crrweb.com>
Date: Sat, 24 Jun 2000 13:16:27 -0400
Links: << >>  << T >>  << A >>
The following link is a great Computer resource site. It contains tons
of information on Computer topics like Operating Systems installation,
configuration, maintance, Programming, and more. Please check it out.

http://www.osfaq.com

Article: 23426
Subject: Re: Different ?
From: eefox@uxmail.ust.hk ( WU Chi Hang FOX )
Date: 24 Jun 2000 17:51:14 GMT
Links: << >>  << T >>  << A >>
Rickman (spamgoeshere4@yahoo.com) :
: The difference is that in this case, all of the possible functions that
: can be implemented in the 1 bit LUT can be duplicated in the following 2
: LUT. The only functions you can use the 1 LUT for (as you have shown)
: are stuck at 1/0, invert, or pass. These are not very "interesting"
: functions. They all result in overall functions of the array that are
: duplicates of what you can do without the 1 LUTs. 
	Thanks, Rickman. But can you tell more clearly what functions
are "interesting" ?

: The larger problem is not so simplistic. Only a percentage of the
: possible combinations result in duplicated overall functions.
: 
: >         Then bringing back to the XC4000, if that is the case, then why
: > the total number of funtions is 2^40 instead of 2^8 ?
	So, in the 2^40 functions, some of them are acually the same 
functions. The actual number of different functions still not determined....

-- 
*************************************************************************
*       /\ /\     Name : Wu Chi Hang J  ( FOX )  **  W **       *
*       ^  ^      Job  : ELEC/CPEG Demonstrator (Rm. 2466, Ext. x7037 ) * 
*       .  .      Email: eefox@uxmail.ust.hk  /  eefox@ee.ust.hk        *
*     =o =               chwu@usa.net / 97Cwch@alumni.ee.ust.hk         *
*       u         Hpage: http://www.ee.ust.hk/~eefox/index.html 4294435 *
*************************************************************************
Article: 23427
Subject: Re: Different ?
From: fliptron@netcom.com (Philip Freidin)
Date: 24 Jun 2000 20:23:18 GMT
Links: << >>  << T >>  << A >>
In article <8j2b2o$ar3$1@news.ust.hk>,
WU Chi Hang FOX  <eefox@uxmail.ust.hk> wrote:
>	First, thanks Rickman. However, I am really stucked at that, I am
>not asking about HW questions, I really want to count how many fuctions
>that a cascaded LUTs can implement. 
>	For 1-bit LUT, I know there are 4 functions
>
>				Output
>	Input  	Function 1	2	3	4	
>	0 		 0	0	1	1
>	1		 0	1	0	1

Fine. You have enumerated all the functions of a 1 input LUT

Inputs     Number of memory bits    Functions
1             2                       4
2             4                      16
3             8                     256
4            16                   65536
N            2^N                  2^(2^N)


>Function 1 is a zero function, Function 2 is follower, Function 3 is NOT
>Function 4 is a one function.

So depending on your view of life, not all of these are 'interesting'.

Function 1 and 4 ignore the input, function 2 is a wire, and function 3
is an inverter. Maybe only the inverter case is interesting, depends what 
you had for breakfast.

>	However, what I am concerning is that, even there are 4 functions,
>utimatelly, it is only 0 and 1 pass into the LUT, so, it does not matter.
>So, what I think is, no-matter it is cascaded or not, the maximum
>function is determined by the last LUT, so for this case, the no. of functions
>is 2^4.

For this case maybe, but remember that in the following LUT, it too has 
cases where the inputs are ignored, or the output is the inversion or 
pass thru of one input, and other inputs are ignored. Which do you 
consider interesting?


>	Then bringing back to the XC4000, if that is the case, then why
>the total number of funtions is 2^40 instead of 2^8 ?

Since the XC4000 CLB has 40 bits total in the two 4-LUTs, and the one 
3-LUT, there are exactly 2^40 possible configurations.

I believe they are not all interesting, because MANY of these ignore some 
of the inputs, or are synonyms of each other, with just the input signals 
swapped. The reason that the pin swaped equivalent functions are not 
interesting, is because the place and route software does this pin 
swapping all the time, and permutes the LUT contents to account for the 
pin swapping. I wouldn't be surpised if the number of unique patterns is 
less than 2^25. The only way to find out the real number may be through 
an exhaustive search.

Philip Freidin

Article: 23428
Subject: Re: What tools do people use for Xilinx FPGAs?
From: Phil Hays <spampostmaster@sprynet.com>
Date: Sat, 24 Jun 2000 14:32:21 -0700
Links: << >>  << T >>  << A >>
"B. Joshua Rosen" wrote:

> If you are just picking an HDL, go with Verilog. Verilog simulators are
> much faster than VHDL, Verilog is much easier to read and write, and
> it's much more concise. A couple of years ago it seemed like the world
> was about evenly split between Verilog and VHDL, but these days I don't
> see VHDL anywhere, everyone seems to be using Verilog. Admitedly my
> sample is limited, and all the companies that I deal with are in the
> networking industry.

Verilog, is that still supported?  I haven't heard of any real work in that
language in years. ;-)

Seriously, VHDL and Verilog are languages that describe the same things in
different syntax, have equal area learning curves, have extensive support and
each has rabid fans.  I'll suggest that you should look at both languages, as
they have different strenghts and weaknesses.  VHDL is easier to master, Verilog
is easier to learn.

I'm in the networking industry as well, and VHDL seems to be the local standard.


-- 
Phil Hays
Article: 23429
Subject: Re: a lot of basic questions - where's the FAQ?
From: lamb_baa@hotmail.com (Eric L)
Date: 24 Jun 2000 22:24:39 GMT
Links: << >>  << T >>  << A >>
In article <39545154.B626A70D@yahoo.com>, spamgoeshere4@yahoo.com says...
>
>"B. Joshua Rosen" wrote:
>> 
>> goto the Xilinx website http://www.xilinx.com and download the
>> literature, everything that you need to know is there.
>
>
>I think that is a little like telling someone who is trying learn
>english to get a dictionary. 
>
>FPGAs are volatile. They do not hold their program when the power goes
>off. So you have to load it everytime you power up the board. Likewise,
>if you want the chip to do something different, you can reload a
>different design into it. This is done by a fairly archane process which
>is different for each brand of chip, but it basically clocks each bit or
>byte into the chip until all the data is in. Not a big deal. When you
>want to do it again, you just pull the Program pin low and start over. 
>
>Just make sure your design is not controlling a motor or something
>dangerous when you reprogram the part!
>


Oh that's pretty easy to do. So all I need is the development software and a 
little basic circuit knowledge plus the pinouts?

Thanks. I also I appreciate the first part in my defense about going to the 
xilinx site. I'm a little overwhelmed by the info I have already and just 
wanted some basics plus someone to point me towards a general direction.

Eric

Article: 23430
Subject: Re: a lot of basic questions - where's the FAQ?
From: lamb_baa@hotmail.com (Eric L)
Date: 24 Jun 2000 22:29:22 GMT
Links: << >>  << T >>  << A >>
>
>Your welcome.
>
>Philip Freidin
>
>
>


Well thanks again! You must have really been suffering from insomnia :) That's 
all I needed, I just wanted to know what to look for.

Eric

Article: 23431
Subject: Re: Different ?
From: Tom Burgess <tom.burgess@home.com>
Date: Sun, 25 Jun 2000 00:37:42 GMT
Links: << >>  << T >>  << A >>
Assertion: for an n-input LUT, with input swapping permitted,
there are 2^(n+1) possible unique functions possible.

Nor-rigorous proof: For n inputs, there are n+1 possible unique states available,
e.g. for 4 inputs, the 5 unique states are {0000, 0001, 0011, 0111, 1111}.
(with swapping allowed, 0001 is is equivalent to 1000, 0100, and 0010)
Since the n inputs to the LUT can only assume n+1 states, and the contents of
each LUT entry are either 0 or 1, there are therefore 2^(n+1) possible
unique LUT patterns (functions) available. So the result for n=4 is 32.

Conjecture: the internal structure of the LUT is not important. With input
swapping permitted, any function of n inputs is possible. So a single
512x1 LUT is equivalent to the 9-input Xilinx 4+4+3 FGH tree. Both can
therefore implement 2^(9+1) = 1024 unique functions. The proof is left as
exercise for the student :)

regards, tom

Philip Freidin wrote:
> 
> In article <8j2b2o$ar3$1@news.ust.hk>,
> WU Chi Hang FOX  <eefox@uxmail.ust.hk> wrote:
> >       First, thanks Rickman. However, I am really stucked at that, I am
> >not asking about HW questions, I really want to count how many fuctions
> >that a cascaded LUTs can implement.
> >       For 1-bit LUT, I know there are 4 functions
> >
> >                               Output
> >       Input   Function 1      2       3       4
> >       0                0      0       1       1
> >       1                0      1       0       1
> 
> Fine. You have enumerated all the functions of a 1 input LUT
> 
> Inputs     Number of memory bits    Functions
> 1             2                       4
> 2             4                      16
> 3             8                     256
> 4            16                   65536
> N            2^N                  2^(2^N)
> 
> >Function 1 is a zero function, Function 2 is follower, Function 3 is NOT
> >Function 4 is a one function.
> 
> So depending on your view of life, not all of these are 'interesting'.
> 
> Function 1 and 4 ignore the input, function 2 is a wire, and function 3
> is an inverter. Maybe only the inverter case is interesting, depends what
> you had for breakfast.
> 
> >       However, what I am concerning is that, even there are 4 functions,
> >utimatelly, it is only 0 and 1 pass into the LUT, so, it does not matter.
> >So, what I think is, no-matter it is cascaded or not, the maximum
> >function is determined by the last LUT, so for this case, the no. of functions
> >is 2^4.
> 
> For this case maybe, but remember that in the following LUT, it too has
> cases where the inputs are ignored, or the output is the inversion or
> pass thru of one input, and other inputs are ignored. Which do you
> consider interesting?
> 
> >       Then bringing back to the XC4000, if that is the case, then why
> >the total number of funtions is 2^40 instead of 2^8 ?
> 
> Since the XC4000 CLB has 40 bits total in the two 4-LUTs, and the one
> 3-LUT, there are exactly 2^40 possible configurations.
> 
> I believe they are not all interesting, because MANY of these ignore some
> of the inputs, or are synonyms of each other, with just the input signals
> swapped. The reason that the pin swaped equivalent functions are not
> interesting, is because the place and route software does this pin
> swapping all the time, and permutes the LUT contents to account for the
> pin swapping. I wouldn't be surpised if the number of unique patterns is
> less than 2^25. The only way to find out the real number may be through
> an exhaustive search.
> 
> Philip Freidin
Article: 23432
Subject: Re: Defining a reset concept for VirtexE
From: "Austin Franklin" <austin@dark77room.com>
Date: 25 Jun 2000 00:58:12 GMT
Links: << >>  << T >>  << A >>
> The limitation in
> using the asynch reset is the slowness of the distribution. The problem
> is trying to make sure that all FFs come out of reset at the same time.

Why do they have to come out of reset at the same time (which I take to
mean all during the same cycle of the clock)?  Do you have inputs that are
changing within 100ns or so of the system coming out of reset?  If you do,
you can not guarantee much of anything....no matter how fast your asynch
reset signal is.

Asynch reset is, exactly that, asynch reset.  Even if it had a 100ps delay
in the chip, you could get different edges, depending on where reset fell
with respect to the clock.  Since it IS asynch, there is no guarantee.


Article: 23433
Subject: Re: Different ?
From: Tom Burgess <tom.burgess@home.com>
Date: Sun, 25 Jun 2000 01:00:06 GMT
Links: << >>  << T >>  << A >>
I withdraw the conjecture as stated. If true, one could implement a 512x1 ROM in
a single CLB which is obviously not the case, darn it. 

post in haste, regret at leisure,
tom

Tom Burgess wrote:
> 
> Assertion: for an n-input LUT, with input swapping permitted,
> there are 2^(n+1) possible unique functions possible.
> 
> Nor-rigorous proof: For n inputs, there are n+1 possible unique states available,
> e.g. for 4 inputs, the 5 unique states are {0000, 0001, 0011, 0111, 1111}.
> (with swapping allowed, 0001 is is equivalent to 1000, 0100, and 0010)
> Since the n inputs to the LUT can only assume n+1 states, and the contents of
> each LUT entry are either 0 or 1, there are therefore 2^(n+1) possible
> unique LUT patterns (functions) available. So the result for n=4 is 32.
> 
> Conjecture: the internal structure of the LUT is not important. With input
> swapping permitted, any function of n inputs is possible. So a single
> 512x1 LUT is equivalent to the 9-input Xilinx 4+4+3 FGH tree. Both can
> therefore implement 2^(9+1) = 1024 unique functions. The proof is left as
> exercise for the student :)
> 
> regards, tom
> 
> Philip Freidin wrote:
> >
> > In article <8j2b2o$ar3$1@news.ust.hk>,
> > WU Chi Hang FOX  <eefox@uxmail.ust.hk> wrote:
> > >       First, thanks Rickman. However, I am really stucked at that, I am
> > >not asking about HW questions, I really want to count how many fuctions
> > >that a cascaded LUTs can implement.
> > >       For 1-bit LUT, I know there are 4 functions
> > >
> > >                               Output
> > >       Input   Function 1      2       3       4
> > >       0                0      0       1       1
> > >       1                0      1       0       1
> >
> > Fine. You have enumerated all the functions of a 1 input LUT
> >
> > Inputs     Number of memory bits    Functions
> > 1             2                       4
> > 2             4                      16
> > 3             8                     256
> > 4            16                   65536
> > N            2^N                  2^(2^N)
> >
> > >Function 1 is a zero function, Function 2 is follower, Function 3 is NOT
> > >Function 4 is a one function.
> >
> > So depending on your view of life, not all of these are 'interesting'.
> >
> > Function 1 and 4 ignore the input, function 2 is a wire, and function 3
> > is an inverter. Maybe only the inverter case is interesting, depends what
> > you had for breakfast.
> >
> > >       However, what I am concerning is that, even there are 4 functions,
> > >utimatelly, it is only 0 and 1 pass into the LUT, so, it does not matter.
> > >So, what I think is, no-matter it is cascaded or not, the maximum
> > >function is determined by the last LUT, so for this case, the no. of functions
> > >is 2^4.
> >
> > For this case maybe, but remember that in the following LUT, it too has
> > cases where the inputs are ignored, or the output is the inversion or
> > pass thru of one input, and other inputs are ignored. Which do you
> > consider interesting?
> >
> > >       Then bringing back to the XC4000, if that is the case, then why
> > >the total number of funtions is 2^40 instead of 2^8 ?
> >
> > Since the XC4000 CLB has 40 bits total in the two 4-LUTs, and the one
> > 3-LUT, there are exactly 2^40 possible configurations.
> >
> > I believe they are not all interesting, because MANY of these ignore some
> > of the inputs, or are synonyms of each other, with just the input signals
> > swapped. The reason that the pin swaped equivalent functions are not
> > interesting, is because the place and route software does this pin
> > swapping all the time, and permutes the LUT contents to account for the
> > pin swapping. I wouldn't be surpised if the number of unique patterns is
> > less than 2^25. The only way to find out the real number may be through
> > an exhaustive search.
> >
> > Philip Freidin
Article: 23434
Subject: Re: dual processor PC for PPR - are they worth the extra cost?
From: steve (Steve Rencontre)
Date: Sun, 25 Jun 2000 03:00 +0100 (BST)
Links: << >>  << T >>  << A >>
In article <395478f4.747495291@nntp1.ba.best.com>, 
bobperl@best_no_spam_thanks.com (Bob Perlman) wrote:

> If you do get a dual-processor motherboard, get one that's based on
> the old-but-reliable 440BX chip set.  Or you can spend major bucks and
> buy an RDRAM-based i820 or i840 system.

Check out Tom's Hardware Guide (www.tomshardware.com) before spending 
money on RDRAM! This is starting to look like pure virgin first-pressing 
snake oil...

Based on an admittedly small sample (one), I can thoroughly recommend 
Tyan's Thunder 2500 (S1867) board. It uses the ServerWorks chipset which 
even Intel seem to think is better than their own!

Not cheap, and apparently a bit tricky to get hold of in the US, I gather, 
but IMO definitely the best choice for a high-end dual right now.

--
Steve Rencontre		http://www.rsn-tech.demon.co.uk
//#include <disclaimer.h>

Article: 23435
Subject: Re: Defining a reset concept for VirtexE
From: Ken McElvain <ken@synplicity.com>
Date: 24 Jun 2000 22:46:00 EDT
Links: << >>  << T >>  << A >>
A good technique for sync reset is to build a distribution tree out
of multiple levels of flip-flops.  This way, modules of your design have
a local source of reset and won't have a problem with delay on a single
very high fanout net.  Your synthesis tool could probably do a reasonable
job via flip-flop replication if you just add  a couple of pipe stages in the
sync reset path.

- Ken McElvain
Synplicity, Inc.

Rickman wrote:

> This question comes up periodically in this newsgroup. The limitation in
> using the asynch reset is the slowness of the distribution. The problem
> is trying to make sure that all FFs come out of reset at the same time.
> Using a synch reset does not help the problem since the reset can still
> happen on different clock edges for the different FFs. Further, you may
> need to use an asynch reset since your clock may not be present or
> running slowly and a synch reset will not work in that case.
>
> There are a couple of things a design can do to make the end of reset
> work correctly.
>
> 1) If you are running with a sufficiently slow clock, then you can
> externally synch reset to the clock and you don't have a problem. This
> is not practical for most designs and the speed of the GSR net is not
> spec'ed. This also won't work if you have more than one clock domain.
>
> 2) Use an additional, separate, synch reset signal that only runs to the
> critical FFs in the design. By synch, I mean this comes from a FF which
> is released after the asynch reset and has a two or three clock delay.
> This should hold in reset any FFs which are in FSMs or other logic which
> will start changing state as soon as the asynch reset is released. Not
> all logic needs this signal.
>
> For example, only the first two levels of FFs in a one-hot encoded FSM
> need the synch reset. The rest won't be enabled by the logic until the
> FSM starts moving through the states. This works well for circuits with
> mulitple clocks. You can have an independant synch reset for each clock
> domain.
>
> 3) Use the existing logic to hold the circuits in reset. If your circuit
> depends on external signals to do anything once it is reset, you can
> make sure that a few clock cycles go by after reset before you start
> operating the circuit.
>
> For example, if the design interfaces to a processor and is idle until
> the processor sends a command, then you need no additional reset
> circuit.
>
> Anyone else have ideas on this?
>
> derekwallace1@my-deja.com wrote:
> >
> > Hi All,
> > Ive started a design of a VirtexE1000. I am looking for advice on how i should
> > control the taking of the device out of reset after a board reset to the FPGA.
> >
> > Here is a summary of my system. 1. a microcontroller delivers an Asynchronous
> > reset signal to the FPGA. 2. it will be active low for 1 us. 3. the purpose
> > of the reset is to return the device to the same state as it was just after
> > configuration.
> >
> > Here are some of my questions. 1. it is my understanding that all FFs in
> > Virtex can be directly Synchronously set or reset i.e. it does not utilise
> > the LUT. Is this true? 2. should i use the reset signal to reset every FF in
> > my design? (i think so) 3. should i perform a synchronous reset or an
> > asynchronous reset of the FFs 4. should i mix it up so that some FFs are rest
> > Synchronously and some asynchronusly? Is there any real
> > advantage/disadvantage to this in Virtex if the FFs can be reset
> > synchronously without using LUT resources. 5.  to re-synchronise the
> > asynchronus input reset i plan to put it through 2 FFs for metastability
> > purposes. In some case i have seen people only use a single FF. Is it best to
> > use 1 FF or 2 FFs? 6. how should i drive the reset signal (whether it is
> > async or sync). Should i use a Bufg (can a Bufg connect to Set reset pins of
> > FF?) Or should i use the low skew lines?
> >
> > Thank you for your time
> >
> > Derek
> >
> > Sent via Deja.com http://www.deja.com/
> > Before you buy.
>
> --
>
> Rick Collins
>
> rick.collins@XYarius.com
>
> Ignore the reply address. To email me use the above address with the XY
> removed.
>
> Arius - A Signal Processing Solutions Company
> Specializing in DSP and FPGA design
>
> Arius
> 4 King Ave
> Frederick, MD 21701-3110
> 301-682-7772 Voice
> 301-682-7666 FAX
>
> Internet URL http://www.arius.com

Article: 23436
Subject: Re: CAE Software and Internet Access
From: Ken McElvain <ken@synplicity.com>
Date: 24 Jun 2000 22:52:29 EDT
Links: << >>  << T >>  << A >>
This is probably the license software trying to find a license server
automatically via a broadcast message.  It is just trying to be helpful.

There are environment variables you can set to control this behavior
in flexlm.

rk wrote:

> Hi,
>
> I recently at day job, in an attempt to increase security, installed a
> software firewall on my PC.  Now, when running Viewdraw, for instance, I
> note that when it starts it attempts to access the Internet.  Why does
> it do this?  What do you'all* think about a company sending you a .exe,
> giving it access to your machine, and then it goes ahead and goes on the
> Internet to do who-knows-what?
>
> Comments?
>
> Winston Smith
>
> * - I am currently living on the Eastern coast, south of the Mason-Dixon
> line.

Article: 23437
Subject: Re: a lot of basic questions - where's the FAQ?
From: Rickman <spamgoeshere4@yahoo.com>
Date: Sun, 25 Jun 2000 01:50:28 -0400
Links: << >>  << T >>  << A >>
Eric L wrote:
> 
> In article <39545154.B626A70D@yahoo.com>, spamgoeshere4@yahoo.com says...
> >I think that is a little like telling someone who is trying learn
> >english to get a dictionary.
...snip...
> >Just make sure your design is not controlling a motor or something
> >dangerous when you reprogram the part!
> >
> 
> Oh that's pretty easy to do. So all I need is the development software and a
> little basic circuit knowledge plus the pinouts?
> 
> Thanks. I also I appreciate the first part in my defense about going to the
> xilinx site. I'm a little overwhelmed by the info I have already and just
> wanted some basics plus someone to point me towards a general direction.
> 
> Eric

I remember clearly how difficult I found it to even figure out the
configuration sequence and how to apply it to my design the first time.
There are a number of things about the Xilinx and other architechtures
that are not complex, but seem difficult because they are not obvious
and seem very different. So don't be afraid to ask questions here. There
are very many knowledgeable and helpful people who will be happy to
answer your questions. No small number of them are from Xilinx so you
will be getting the answer straight from the horse's mouth, so to speak!


-- 

Rick Collins

rick.collins@XYarius.com

Ignore the reply address. To email me use the above address with the XY
removed.



Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX

Internet URL http://www.arius.com
Article: 23438
Subject: Re: Different ?
From: Rickman <spamgoeshere4@yahoo.com>
Date: Sun, 25 Jun 2000 01:59:06 -0400
Links: << >>  << T >>  << A >>
The term "interesting" as we are using it is a mathematical term which I
have never seen a rigorous definition for. In our case it is a bit of a
euphemism for things that have some use rather than just counting all of
the possible combinations. 


WU Chi Hang FOX wrote:
> 
> Rickman (spamgoeshere4@yahoo.com) :
> : The difference is that in this case, all of the possible functions that
> : can be implemented in the 1 bit LUT can be duplicated in the following 2
> : LUT. The only functions you can use the 1 LUT for (as you have shown)
> : are stuck at 1/0, invert, or pass. These are not very "interesting"
> : functions. They all result in overall functions of the array that are
> : duplicates of what you can do without the 1 LUTs.
>         Thanks, Rickman. But can you tell more clearly what functions
> are "interesting" ?
> 
> : The larger problem is not so simplistic. Only a percentage of the
> : possible combinations result in duplicated overall functions.
> :
> : >         Then bringing back to the XC4000, if that is the case, then why
> : > the total number of funtions is 2^40 instead of 2^8 ?
>         So, in the 2^40 functions, some of them are acually the same
> functions. The actual number of different functions still not determined....
> 
> --
> *************************************************************************
> *       /\ /\     Name : Wu Chi Hang J  ( FOX )  **  W **       *
> *       ^  ^      Job  : ELEC/CPEG Demonstrator (Rm. 2466, Ext. x7037 ) *
> *       .  .      Email: eefox@uxmail.ust.hk  /  eefox@ee.ust.hk        *
> *     =o =               chwu@usa.net / 97Cwch@alumni.ee.ust.hk         *
> *       u         Hpage: http://www.ee.ust.hk/~eefox/index.html 4294435 *
> *************************************************************************

-- 

Rick Collins

rick.collins@XYarius.com

Ignore the reply address. To email me use the above address with the XY
removed.



Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

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Internet URL http://www.arius.com
Article: 23439
Subject: Re: Defining a reset concept for VirtexE
From: Rickman <spamgoeshere4@yahoo.com>
Date: Sun, 25 Jun 2000 02:12:46 -0400
Links: << >>  << T >>  << A >>
Austin Franklin wrote:
> 
> > The limitation in
> > using the asynch reset is the slowness of the distribution. The problem
> > is trying to make sure that all FFs come out of reset at the same time.
> 
> Why do they have to come out of reset at the same time (which I take to
> mean all during the same cycle of the clock)?  Do you have inputs that are
> changing within 100ns or so of the system coming out of reset?  If you do,
> you can not guarantee much of anything....no matter how fast your asynch
> reset signal is.
> 
> Asynch reset is, exactly that, asynch reset.  Even if it had a 100ps delay
> in the chip, you could get different edges, depending on where reset fell
> with respect to the clock.  Since it IS asynch, there is no guarantee.

Except that you can drive the Asynch reset with a synchronous signal.
The term Asynchronous Reset actually has nothing to do with the timing
of the input signal. It defines the nature of the reset on the FFs. If
you connect the GSR to a Synchronous Reset on the FFs, you still have to
distribute the reset signal so that it arrives to the FFs at the same
clock cycle. In my post, case 1 mentions that a slow clock and a synched
reset will let you operate without problems. 

As for the inputs changing right after reset, they don't have to be
changing. Inputs can be asserted (or deasserted) during reset, but
represent inputs that will cause the circuit to change state as soon as
the reset is removed. If you don't have any inputs that will cause a
state change following reset (including any logic that will change state
without inputs such as a free running counter) then you don't have a
problem with the reset timing. I think I covered that in my other
description for case 3. 

The problems start when you have logic that starts changing state on
different clock cycles and should be changing on the same clock cycle.
Any way you can avoid that will work. 


-- 

Rick Collins

rick.collins@XYarius.com

Ignore the reply address. To email me use the above address with the XY
removed.



Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX

Internet URL http://www.arius.com
Article: 23440
Subject: How to speed it up?
From: Shoran <xxd75NOxxSPAM@263.net.invalid>
Date: Sat, 24 Jun 2000 23:39:17 -0700
Links: << >>  << T >>  << A >>
There is a problem in my design under Maxplus2 9.6 . I find that
each individual module(symbol) can run at high speed above
100MHz, but it will be slow as 20MHz when I connect the symbols
as a whole design. So what is the reason?

Thanks in advance.

Best regards

Shoran

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Article: 23441
Subject: How to speed it up?
From: Shoran <xxd75NOxxSPAM@263.net.invalid>
Date: Sun, 25 Jun 2000 00:30:15 -0700
Links: << >>  << T >>  << A >>
There is a problem in my design under Maxplus2 9.6 . I find that
each individual module(symbol) can run at high speed above
100MHz, but it will be slow as 20MHz when I connect the symbols
as a whole design. So what is the reason?
Thanks in advance.

Best regards

Shoran



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Article: 23442
Subject: Amba/Daytona/PCI
From: "Domagoj" <domagoj@engineer.com>
Date: Sun, 25 Jun 2000 12:43:33 +0200
Links: << >>  << T >>  << A >>
Hi,
    I'm about to jump in a design of RISC, UNIX oriented processor in Virtex
FPGA. I'm not sure which bus standard to use. So which bus standard
is recommended for such an IP ?
    Maybe I've missed something, so is there any better standard to think
about ?

any recomendations will be highly appreciated,

-------------------------------------------
-             Domagoj              -
- Domagoj@engineer.com -
-------------------------------------------




Article: 23443
Subject: IDE-Interface for FPGA
From: Claas Richter <clri@gmx.de>
Date: Sun, 25 Jun 2000 17:33:57 +0200
Links: << >>  << T >>  << A >>
Hello!

Does anyone have any experience in the use of FPGAs for connecting to
the IDE-Bus?

Or has anybody implemented an IDE/ATA-Bus-Interface for FPGAs ??
I need it to read and write to a harddisk.

Thank you
Claas


Article: 23444
Subject: Re: IDE-Interface for FPGA
From: Rickman <spamgoeshere4@yahoo.com>
Date: Sun, 25 Jun 2000 11:55:09 -0400
Links: << >>  << T >>  << A >>
Claas Richter wrote:
> 
> Hello!
> 
> Does anyone have any experience in the use of FPGAs for connecting to
> the IDE-Bus?
> 
> Or has anybody implemented an IDE/ATA-Bus-Interface for FPGAs ??
> I need it to read and write to a harddisk.
> 
> Thank you
> Claas

I am in the process of designing an ATA interface in an Orca FPGA for
connecting mass storage to a DSP chip. I have found a good amount of
data on such an interface on the web and am in process of digesting it.
Here a couple of links that I saved. There are many more that you can
find with a Yahoo! search or a search at DejaNews. 

http://www.saeco.co.uk/ide.htm

http://www.blkbox.com/~jdbaker/SmallSys/8bitIDE.html

It appears that a very popular home project is to connect a small micro
to a CDROM via the ATA bus. 


-- 

Rick Collins

rick.collins@XYarius.com

Ignore the reply address. To email me use the above address with the XY
removed.



Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX

Internet URL http://www.arius.com
Article: 23445
Subject: Fpga in tristate?
From: "Bjrn Lindegren" <b.j.l@swipnet.se>
Date: Sun, 25 Jun 2000 18:57:25 +0200
Links: << >>  << T >>  << A >>
Hello,

Is there any possibility to set a FPGA device in tristate mode?

My problem is, I want my FPGA to transmitt data to a DSP, when the DSP want
an answer from my FPGA the DSP sets a pin to high and the FPGA answer, but
when the pin is low, I want the FPGA to be in tristate mode to not damage
the DSP.

When this pin is low, I still want my FPGA to work.

Yes I can solve this problem with external digital devices.  But I hope I
can make this in a program.......


Bjrn




Article: 23446
Subject: Re: Fpga in tristate?
From: Rickman <spamgoeshere4@yahoo.com>
Date: Sun, 25 Jun 2000 13:05:40 -0400
Links: << >>  << T >>  << A >>
You didn't say what type of FPGA you are using, but as far as I know all
the common FPGAs and CPLDs can set their outputs to a tristate
condition. For example, the Xilinx FPGAs have an input buffer and an
output buffer with tristate control on each IO pin. You can use either
or both on any pin in any combination. 


"Bjrn Lindegren" wrote:
> 
> Hello,
> 
> Is there any possibility to set a FPGA device in tristate mode?
> 
> My problem is, I want my FPGA to transmitt data to a DSP, when the DSP want
> an answer from my FPGA the DSP sets a pin to high and the FPGA answer, but
> when the pin is low, I want the FPGA to be in tristate mode to not damage
> the DSP.
> 
> When this pin is low, I still want my FPGA to work.
> 
> Yes I can solve this problem with external digital devices.  But I hope I
> can make this in a program.......
> 
> Bjrn

-- 

Rick Collins

rick.collins@XYarius.com

Ignore the reply address. To email me use the above address with the XY
removed.



Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX

Internet URL http://www.arius.com
Article: 23447
Subject: Re: a lot of basic questions - where's the FAQ?
From: lamb_baa@hotmail.com (Eric L)
Date: 25 Jun 2000 19:37:22 GMT
Links: << >>  << T >>  << A >>

>I remember clearly how difficult I found it to even figure out the
>configuration sequence and how to apply it to my design the first time.
>There are a number of things about the Xilinx and other architechtures
>that are not complex, but seem difficult because they are not obvious
>and seem very different. So don't be afraid to ask questions here. There
>are very many knowledgeable and helpful people who will be happy to
>answer your questions. No small number of them are from Xilinx so you
>will be getting the answer straight from the horse's mouth, so to speak!
>
>
>-- 
>
>

Thanks. I appreciate that. I'm just going to jump into it and hope for the 
best. Would you mind verifying my parts list?

According to http://www.xilinx.com/xapp/xapp058.pdf

For EPROM programming, all I need is a 8051, 74HC373,a 5Mhz clock and a .1uF 
cap, Xilinx Data Memory and 8051 Program memory. Is the memory just EPROM 
chips?

For JTAG, would a homemade parallel port to JTAG converter work (found a 
schematic on the net) or would it be better to buy one and which would you 
recommend.

Thanks, 
Eric

Article: 23448
Subject: Re: a lot of basic questions - where's the FAQ?
From: Rickman <spamgoeshere4@yahoo.com>
Date: Sun, 25 Jun 2000 17:11:43 -0400
Links: << >>  << T >>  << A >>
I took a look at the appnote and I would not recommend that approach for
a beginner. I have not used JTAG before, but I don't think it is nearly
as straight forward as just using the standard programming modes. 

If you look at the data book (which part are you trying to program,
BTW?) you will see a diagram for serial slave programming. This is the
simplest mode to operate and it is very easy to control it. If you want,
you can do all of the work from the PC parallel port and will need no
logic. Or if you prefer, you can use a small micro controller with a few
KB of memory. 

To use the PC parallel port, wire DIN, CCLK and PRGM- to output pins on
the parallel port. You can use the data pins or control pins, it does
not matter. DONE and INIT- should be wired to input pins and have pullup
resistors added (4.7K is a good value). Map your IO pins to the
registers in the parallel port and start coding away. 

I think this was just discussed here a couple of weeks ago. If you dig
around you may find some info from others that have done this. You may
even find some source code. 

If you use the 8 bit micro, you can use a serial port to connect to your
PC and download the configuration data. Operating the IO pins is the
same as above. 

For more info, try Xapp176, 090 and 098. 


Eric L wrote:
> 
> >I remember clearly how difficult I found it to even figure out the
> >configuration sequence and how to apply it to my design the first time.
> >There are a number of things about the Xilinx and other architechtures
> >that are not complex, but seem difficult because they are not obvious
> >and seem very different. So don't be afraid to ask questions here. There
> >are very many knowledgeable and helpful people who will be happy to
> >answer your questions. No small number of them are from Xilinx so you
> >will be getting the answer straight from the horse's mouth, so to speak!
> >
> >
> >--
> >
> >
> 
> Thanks. I appreciate that. I'm just going to jump into it and hope for the
> best. Would you mind verifying my parts list?
> 
> According to http://www.xilinx.com/xapp/xapp058.pdf
> 
> For EPROM programming, all I need is a 8051, 74HC373,a 5Mhz clock and a .1uF
> cap, Xilinx Data Memory and 8051 Program memory. Is the memory just EPROM
> chips?
> 
> For JTAG, would a homemade parallel port to JTAG converter work (found a
> schematic on the net) or would it be better to buy one and which would you
> recommend.
> 
> Thanks,
> Eric

-- 

Rick Collins

rick.collins@XYarius.com

Ignore the reply address. To email me use the above address with the XY
removed.



Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX

Internet URL http://www.arius.com
Article: 23449
Subject: Re: Defining a reset concept for VirtexE
From: "Austin Franklin" <austin@darkr99oom.com>
Date: 26 Jun 2000 01:37:01 GMT
Links: << >>  << T >>  << A >>
> Except that you can drive the Asynch reset with a synchronous signal.

Of course, then the reset signal is synchronous.

> The term Asynchronous Reset actually has nothing to do with the timing
> of the input signal. It defines the nature of the reset on the FFs.

Of course it has to do with the timing of the input signal.  It can mean
either.  It depends on what your reference is.  Also, if your reset input
isn't synchronous, then, as I believe I said in my other response, it
doesn't matter how fast your reset routing is.

> If
> you connect the GSR to a Synchronous Reset on the FFs, you still have to
> distribute the reset signal so that it arrives to the FFs at the same
> clock cycle. In my post, case 1 mentions that a slow clock and a synched
> reset will let you operate without problems. 

Not necessarily.  This is only a problem if inputs are changing within N
cycles after reset, where N is the number of cycles it takes for your
design to completely reset.  If you know that inputs are changing before
you are out of reset, and you know how long reset is, just do your design
to accommodate this.  If you characterize/specify something, and design to
it, you won't have any problems.  You can design your chip so it can
tolerate multiple cycle reset.  

> As for the inputs changing right after reset, they don't have to be
> changing. Inputs can be asserted (or deasserted) during reset, but
> represent inputs that will cause the circuit to change state as soon as
> the reset is removed.

This sounds like potentially bad design to me, but perhaps you can explain
further under what circumstances this would be useful, aside from a free
running counter (possibly for SDRAM refresh).

> If you don't have any inputs that will cause a
> state change following reset (including any logic that will change state
> without inputs such as a free running counter) then you don't have a
> problem with the reset timing. I think I covered that in my other
> description for case 3.

well, why not just hold off the counter for N (N as described/defined
above)?
 
> The problems start when you have logic that starts changing state on
> different clock cycles and should be changing on the same clock cycle.
> Any way you can avoid that will work. 

I understand the purported problem, but proper system design prevents this
from being an issue.  Perhaps the problem is some people don't understand
the issue in the first place, and don't know what they need to do to design
so this is not a problem.




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