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# Messages from 23450

Article: 23450
Subject: Re: How to speed it up?
From: Ray Andraka <ray@andraka.com>
Date: Mon, 26 Jun 2000 02:53:35 GMT
Links: << >>  << T >>  << A >>
This is because the aggregate design is congesting the routing
channels.  If you look carefully at the altera structure, you'll find
that there are only 3 row routing channels for every 4 LE's.  For a
'random logic' design this is often not a big handicap since many of the
connections can often be made locally to a specific lab (ie not using
the row routing resources)  For a data path design containing lots of
arithmetic or counters this doesn't work as well because the inter-LE
connections are limited by the carry chains.  Also, the interconnect of
the row routing is a sparse matrix, meaning there is a very limited set
of LABs a specific LAB will connect to in a single level.  As you
approach about 3/4 utilization of the row route resources, many of the
connections start getting forced to go through an intermediate
connection to reach the target (thereby further congesting the routing
too).  Heavy utilization of EABs will also cause similar problems
because there is only one (two in the E parts) per row.

If your design blocks have logic before/after a regsiter on the I/O,
then the delays here may also be getting lumped with longer row to row
routes in the aggregate design.   You can try fixing it by putting
pipeline registers between (especially in front of carry chains), but be
aware that the ALtera tool tends to place them close to the previous
register rather than close to the target.

Try using a larger device to drop your % utilization down to make more
routing available.  Be careful there too, as the larger the device the
slower teh row and column routes.  Good luck :-)

Shoran wrote:

> There is a problem in my design under Maxplus2 9.6 . I find that
> each individual module(symbol) can run at high speed above
> 100MHz, but it will be slow as 20MHz when I connect the symbols
> as a whole design. So what is the reason?
>
> Best regards
>
> Shoran
>
> Got questions?  Get answers over the phone at Keen.com.
> Up to 100 minutes free!
> http://www.keen.com

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com  or http://www.fpga-guru.com


Article: 23451
Subject: Re: F2.1i
From: "Leisure" <nathans@163.net>
Date: Mon, 26 Jun 2000 16:20:27 +0800
Links: << >>  << T >>  << A >>
No problem, schematic entry is the basic function.
<erika_uk@my-deja.com> wrote in message news:8j27ii$mte$1@nnrp1.deja.com...
>
> In article <8j0os5$oco$1@nnrp1.deja.com>,
>   erika_uk@my-deja.com wrote:
> > hey all,
> >
> > I want to install the F2.1i at home. Unfortunately, i can't have
> > internet connection. Will the F2.1i be fully functionnal if i use just
> > a schematic entry
> >
> > Thanks.
> >
> > --Erika
> >
> > Sent via Deja.com http://www.deja.com/
> >
>
>
> Sent via Deja.com http://www.deja.com/


Article: 23452
From: Jamil Khatib <Khatib@opencores.org>
Date: Mon, 26 Jun 2000 10:30:41 +0200
Links: << >>  << T >>  << A >>
Hi,
speekers area" to continue my graduate studies in the Reconfigurable
Computing  and its EDA feilds.

Jamil Khatib


Article: 23453
Subject: Re: Looking for 'FREE' FPGA software
From: Tim Courtney <t.courtney@ee.qub.ac.uk>
Date: Mon, 26 Jun 2000 10:26:33 +0100
Links: << >>  << T >>  << A >>


"Nicholas C. Weaver" wrote:
>
> In article <39532E20.D816A507@ee.qub.ac.uk>,
> Tim Courtney  <t.courtney@ee.qub.ac.uk> wrote:
> >Slight disagreement with this point. If it is the _student_ version that
> >ships for $105 then the difference is not necessarily "peanuts". > >Remembering back to my student days (about 2 years ago)$105 would
> >definately have been the difference between eating for a fortnight and
> >not eating for a fortnight. Just thought that this should be borne in
> >mind when discussing money with relation to student 'specials'.
>
>         The student version is often available at that price with a
> textbook of some sort, not just standalone.
> --
> Nicholas C. Weaver                                 nweaver@cs.berkeley.edu

The great thing about textbooks is that they are in libraries. Purchase
often proves unnecessary... So, in other words, it is shipped with a
somewhat less than necessary bundle of processed wood causing
unnecessary deforestation... But this is another issue.
--
Tim Courtney
Electrical & Electronic Engineering	mobile	: +44 (0)7801 250 903
The Queen's University of Belfast	tel(wk)	: +44 (0)28 9027 4275
Ashby Building, Stranmillis Road	fax	: +44 (0)28 9066 7023
Belfast, Northern Ireland, BT9 5AH	e-mail	: t.courtney@ee.qub.ac.uk

Article: 23454
Subject: Re: I need an advice here pls!
From: Pini <>
Date: Mon, 26 Jun 2000 03:54:12 -0700
Links: << >>  << T >>  << A >>
www.xilinx.com/xbrf/xbrf015.pdf

Article: 23455
Subject: Re: How to speed it up?
From: Jerry English <jenglish@planetc.com>
Date: Mon, 26 Jun 2000 08:57:56 -0400
Links: << >>  << T >>  << A >>
Let me look into my crystal ball:

I see no registers between your modules. I see you
placing flops between your symbols. I see the
timing analyzer now reporting much higher

regards
Jerry

Shoran wrote:

> There is a problem in my design under Maxplus2 9.6 . I find that
> each individual module(symbol) can run at high speed above
> 100MHz, but it will be slow as 20MHz when I connect the symbols
> as a whole design. So what is the reason?
>
> Best regards
>
> Shoran
>
> Got questions?  Get answers over the phone at Keen.com.
> Up to 100 minutes free!
> http://www.keen.com


Article: 23456
Subject: Xilinx XC5200 implementation with F2.1i
From: "Rascal" <spambuster_ravasioc@tin.it>
Date: Mon, 26 Jun 2000 15:06:45 +0200
Links: << >>  << T >>  << A >>
Has anyone of you ever tried to implement a XC5202/5206 device with
Foundation 2.1i ( or 1.5, too) ? The software seems to have BIG problems in
routing designs based on these devices; the old XACT router, running with
Windows 3.11, on the other hand, could manage the same design without
excessive effort.
Actually, I still have to use that older implementation software (and then
keep a dedicated PC with Windows 3.11 installed on it) to develop/update my
XC5200 based projects, and this isn't really that comfortable. F2.1i
tools,in most cases, can't succeed in the PAR step for simple designs, too.
them told me that this is a known problem of implementation tools based on
M1 engine, so I have necessarily to use old XACT for XC5200 devices. The
other one told me that F2.1 router is actually slightly worse than XACT for
XC5200 but should work anyway: in my case the problem should reside on
netlist generation.
Does anyone has any additional information or, better, a solution ?


Article: 23457
Subject: Re: 500 million transistor FPGA's
From: Austin Lesea <austin.lesea@xilinx.com>
Date: Mon, 26 Jun 2000 08:00:12 -0700
Links: << >>  << T >>  << A >>
Illan,

I am serious.

Austin

iglasner@my-deja.com wrote:

> Hi,
>
>    You can't be serius,
>
> This remind all those places who ask you to bring name of people that
> will be your referance and obviusly you will give only name of people
> who think you are at the very least the newxt Einstein.
>
> the same here the point of showing a site with success story is nothing.
>
> who says there design was done quicker than if it was done in asic, who
> says that they are not poor designer who don't know how to design
> Asic's, who says that they didn't had a bad experiance in the past and
> using it now and so on and so on ...
>
> I wonder if TSMC will show a site with success story of people who
> desing Asic's and pass them in the first time and did it very quickly
> and wrote it so will this mean that Asic are faster easier better can
> be done on first and so on ?
>
> I would expect some thing more concret in which you explain why you
> said what you said and why you belive it to be right.
>
> Of course as one mention you should compare how a certain design whould
> have been done in FPGA Vs Asic and not that in FPGA it took 500M gate
> and in Asic same thing will cost ... since in Asic we don't need so
> many gates.
> also as one mention we will not need in asic the same technology even
> tho' I think he gave a bit bigger technology than I would but still his
> point is right.
>
> once you take a "imagenary design" and do the comparision than you are
> standing on equal ground, and you can claim what ever you claim base on
> it.
>
> I belive in my previus msg I put all the phases needed to get a chip I
> even put timing you might disagree with so I would love to see a table
> in which you compare the time etc of each stage asic vs fpga and than
> the total sum and conclution. I wonder if once you get this table done
> you will still hold your belive so strongly.
>
> Lastly about the clock tree that someone else mention, I must say that
> while a clock tree is not "fun", it is sometime a GREAT advantage to be
> able to control, and "play with", and no need to tell me it is risky or
> dangerous etc etc as thing are risky and dangerous when you do thing
> you don't understand but if you do understand you can get thing done
> that in other way you might not been able and had to compremise, or use
> an extra pll etc.
>
> and to give a small exmaple assume a chip with 20 clock domain, one is
> the "master" which most of the chip work with it and 19 other are only
> use in small part/logic.
>
> to use 20 PLL will be ... the power/noise etc are ... so you will most
> likely want to use one PLL for the main clock and the other clock will
> have clock tree but without PLL.
>
> now the output signal from those 19 clock domain in the best case will
> take several ns since there is the clock tree than the clk->Q of the FF
> and than if you have Jtag there is additional mux and than there is the
>
> now assume you work in 125M clock so the period is 8n, and assume this
> signal need to go to another chip which is not yours and the trace on
> the board plus setup is let say 4n than you need to have your signal
> out in 4n and it is a problem as the clock tree can be (of course
> depend on the load) let say 3n and the rest is also 3n so you are 2n to
> much.
>
> now if you can "play" with the clock tree and to this particular signal
> FF give the clock from the root of the tree than you are in good shape.
>
> of course this mean that the signal which come to the FF have less time
> than a whole period as the clock to this FF come sooner but this can be
> solved in the design or even by adding another FF (or even two as
> syncronizer and treat it as going from one clock domain to another even
> tho it is only phase issue). this way you can get it work.
>
> This is only one example and even here I could extrem it by taking the
> frequancy even higher.
>
> one small additional point since someone mention that you don't need to
> do in FPGA clock tree etc, while I don't see it as advantage mostly it
> is the same in asic as your vendor will do it so for you as a user in
> mnay cases it is only the desing part and than synthesis place and
> route etc etc are done not by you.
>
> FPGA are great components and my belive is that if you have a new
> design and you can do it in FPGA than do so, but many design simple
> can't be done in FPGA and can only be done in Asic, and just as FPGA
> vendor are keeping moving forward with technology the same is for Asic
> vendors. and just as FPGA vendor work to make there fpga look digital
> for the user as we users don't want to take care of the analog effect
> of sub-micron the same is with Asic's Vendor and Fabs, so I wouldn't
> jump and say that Asic designer will have to either move to fpga or
> have to deal with analog problems.
>
> have a nice day
>
>    Illan
>
> In article <395277DA.24784027@xilinx.com>,
>   Austin Lesea <austin.lesea@xilinx.com> wrote:
> > Well,
> >
> > Look at our customers' success stories.
> >
> >  http://www.xilinx.com/company/success/index.htm
> >
> > Austin
> >
> > iglasner@my-deja.com wrote:
> >
> > > Hi,
> > >
> > >   I might missed something but it seem to me as you belive this huge
> > > chip when target to FPGA take less time than when target to ASIC.
> and
> > > more over they have "have inferior tools"
> > >
> > > I wonder how did you come to this conclutions ?
> > >
> > > I would think the design might take even longer in FPGA as I might
> need
> > > to re-code or write is a bit more messy to get the FPAG work in
> high-
> > > performance.
> > > than the simulation I would think are just about the same (as while
> you
> > > might want to save sometime in the FPAG as you can always re-code it
> > > for a big design if you don't simulate properly you will simple go
> > > forth and back between the lab and your computer)
> > > than come the synthesis which is again about the same as well as the
> > > simulation for the post synthesis gate level
> > > and than come the place and route and the clock tree which about the
> > > same with it's simulation of post place and route with the netlist
> and
> > > sdf files. (the clock tree might take few extra days)
> > > and than come some saving which are the vectors which you don't need
> > > and maybe also bist check and scan insertion that might make timing
> > > problem if was not taken for the start into considuration
> > > so I would think that for a design that take let say 10 month (after
> > > all we do speak about large design so it might be even longer) you
> > > might save about 2-3 weeks or even a month which is something but I
> > > wouldn't say it is enough to say "takes too long"
> > >
> > > and to the tools what exactly is inferior ? there are very good
> tools
> > > for synthesis and place and route as well as scan insertion clock
> tree
> > > etc for asic (e.g you might heard about Synopsys) ?
> > >
> > > I can undertsand the risk as in many cases a metal fix can take
> between
> > > a 1-2 month and a complete spin will take even take a more (depend
> of
> > > course on how bad are the bugs).
> > >
> > > I will even agree with the more expensive as the NRE for 0.25 or
> less
> > > are something to consider. (the price for NRE for 0.35 as well as
> the
> > > price for metal spin etc in the overall are not "too expensive" but
> you
> > > might want to add them as well)
> > >
> > > have a nice day
> > >
> > >    Illan
> > >
> > > In article <3952285C.3DFA8EE7@xilinx.com>,
> > >   Austin Lesea <austin.lesea@xilinx.com> wrote:
> > > > Wake up & smell the silicon,
> > > >
> > > > I couldn't resist responding to this.
> > > >
> > > > Steve is in the cube across from me, and we teased him on how
> > > conservative he
> > > > was.
> > > >
> > > > Like Peter says, we have the time to do what is needed to make
> this
> > > scale of
> > > > technology work:  the ASIC/ASSP model is probably limited to less
> > > than 50
> > > > million devices.  It is too expensive, too risky, takes too long,
> > > have inferior
> > > > tools, and is unable to claim the advantages it once did.
> > > >
> > > >  http://www.support.xilinx.com/xcell/xl30/xl30_10.pdf was written
> two
> > > years
> > > > ago.  It is so satisfying to see the team's vision realized.
> Thank
> > > you to all
> > > > of our customers, and we will continue to provide you with the
> > > solutions you
> > > > need to succeed.
> > > >
> > > > Austin Lesea, ICDES Group, Xilinx
> > > >
> > > > EKC wrote:
> > > >
> > > > > I got this quote from eetimes.com. Is this technically feasible?
> > > > >
> > > > > <<START QUOTE>>
> > > > > Panelist Steve Young, an architect of the Virtex FPGA family of
> > > Xilinx (San
> > > > > Jose, Calif.), advocated FPGAs in his presentation. But he
> > > surprised many
> > > > > when he said he expects the number of transistors on a single
> FPGA
> > > to hit
> > > > > 500 million in 2001, with the Xilinx Virtex-II family.
> > > > >
> > > > > Engineers designing FPGA silicon for companies such as Xilinx
> are
> > > coping
> > > > > with some of the most difficult deep-sub-micron devices around,
> > > Young said.
> > > > > "We face a number of problems so you don't have to," he said.
> These
> > > include
> > > > > simultaneous switching, deep-submicron parasitics, fault
> coverage,
> > > and clock
> > > > > skew management.
> > > > >
> > > > > "Like all chip designers, we are customers of EDA tools," said
> > > Young. "And
> > > > > we are challenging them." He said commercial EDA tools just
> aren't
> > > designed
> > > > > for the size of devices Xilinx engineers are building.
> > > > >
> > > > > Panel presentations will be available at the DAC Web site
> > > (www.dac.com) in a
> > > > > few weeks.
> > > > >
> > > > > http://www.eetimes.com/
> > > > >
> > > > > Copyright c 2000 CMP Media Inc.
> > > > > <<END QUOTE>>
> > > >
> > > >
> > >
> > > Sent via Deja.com http://www.deja.com/
> > > Before you buy.
> >
> >
>
> Sent via Deja.com http://www.deja.com/


Article: 23458
Subject: Re: Defining a reset concept for VirtexE
From: Rickman <spamgoeshere4@yahoo.com>
Date: Mon, 26 Jun 2000 12:05:51 -0400
Links: << >>  << T >>  << A >>
Austin Franklin wrote:
>
> > Except that you can drive the Asynch reset with a synchronous signal.
>
> Of course, then the reset signal is synchronous.

Austin, I don't wish to get into a long debate full of semantic
arguments. I was speaking from the context of using a Xilinx chip with a
GSR which in most of their chips is always an asynch reset "input",
because you are not given a choice. In the VirtexE, the GSR can be
configured as a synch reset "input". You can mean this term to be
anything you want. I was telling you what I meant by it.  :-)

> > The term Asynchronous Reset actually has nothing to do with the timing
> > of the input signal. It defines the nature of the reset on the FFs.
>
> Of course it has to do with the timing of the input signal.  It can mean
> either.  It depends on what your reference is.  Also, if your reset input
> isn't synchronous, then, as I believe I said in my other response, it
> doesn't matter how fast your reset routing is.

If the reset input has async timing, then you need to do other things to
make sure you come out of reset correctly. I describe two things you can
do in cases 2 and 3 of my post to Derek Wallace.

> > If
> > you connect the GSR to a Synchronous Reset on the FFs, you still have to
> > distribute the reset signal so that it arrives to the FFs at the same
> > clock cycle. In my post, case 1 mentions that a slow clock and a synched
> > reset will let you operate without problems.
>
> Not necessarily.  This is only a problem if inputs are changing within N
> cycles after reset, where N is the number of cycles it takes for your
> design to completely reset.  If you know that inputs are changing before
> you are out of reset, and you know how long reset is, just do your design
> to accommodate this.  If you characterize/specify something, and design to
> it, you won't have any problems.  You can design your chip so it can
> tolerate multiple cycle reset.

I was describing multiple ways to deal with the end of reset. Case 1 of
my post to Derek Wallace was using a fast enough GSR to bring all of the
FFs out of reset on the same clock cycle. The other two methods I
discussed covered what you are saying here.

> > As for the inputs changing right after reset, they don't have to be
> > changing. Inputs can be asserted (or deasserted) during reset, but
> > represent inputs that will cause the circuit to change state as soon as
> > the reset is removed.
>
> This sounds like potentially bad design to me, but perhaps you can explain
> further under what circumstances this would be useful, aside from a free
> running counter (possibly for SDRAM refresh).

This can happpen anytime you don't have control over your inputs! They
can be coming from an external source, or the design requirement can be
that you respond to signals that were defined before you (the FPGA
designer) had a chance to say, "I would prefer that all of my inputs be
in a quiessent state until I have a chance to boot up and tell the rest
of the design that I am alive, so can you all hold off your design
operation until you hear from my chip?" Obviously you can't always do
this. For example, until V2.2 of PCI, you did not know how long you had
between reset and first operation of the bus. This was a problem for
many PCI Core designs.

> > If you don't have any inputs that will cause a
> > state change following reset (including any logic that will change state
> > without inputs such as a free running counter) then you don't have a
> > problem with the reset timing. I think I covered that in my other
> > description for case 3.
>
> well, why not just hold off the counter for N (N as described/defined
> above)?

That would require that you have a secondary reset input to your counter
which I discussed in case 2 of my post to Derek Wallace, IIRC.

> > The problems start when you have logic that starts changing state on
> > different clock cycles and should be changing on the same clock cycle.
> > Any way you can avoid that will work.
>
> I understand the purported problem, but proper system design prevents this
> from being an issue.  Perhaps the problem is some people don't understand
> the issue in the first place, and don't know what they need to do to design
> so this is not a problem.

If you can do this by controlling your "system", (case 3 of my post to
Derek Wallace) then it is just that much easier for the FPGA designer.
But often the system design is done before the FPGA designer is called
upon or parts of the design can not be controlled to this extent.

--

Rick Collins

rick.collins@XYarius.com

removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX

Internet URL http://www.arius.com

Article: 23459
Subject: BOUNDARY-SCAN OF INTERNAL LOGIC INSIDE A VIRTEX FPGA?
From: Asher Martin-CRAY <martin2@uiuc.edu>
Date: Mon, 26 Jun 2000 11:20:13 -0500
Links: << >>  << T >>  << A >>
Greetings,

- What does the boundary-scan CLB (internal logic) data that comes out
of a Virtex FPGA mean? What does this data look like?

- Can someone please send me a binary file with this CLB data so that I
can take a look at it and try to interpret it myself?

Take care,
>Asher<

<<=>>=<<=>>=<<=>><<=>>=<<=>>=<<=>><<=>>=<<=>>=<<=>>
Asher C. Martin
<<=>>=<<=>>=<<=>><<=>>=<<=>>=<<=>><<=>>=<<=>>=<<=>>
Chippewa Falls, WI 54729
(715) 726-4761
<<=>>=<<=>>=<<=>><<=>>=<<=>>=<<=>><<=>>=<<=>>=<<=>>
asherm@cray.com
http://www.uiuc.edu/~martin2/
<<=>>=<<=>>=<<=>><<=>>=<<=>>=<<=>><<=>>=<<=>>=<<=>>

Article: 23460
Subject: Re: Fpga in tristate?
From: Asher Martin-CRAY <martin2@uiuc.edu>
Date: Mon, 26 Jun 2000 11:29:23 -0500
Links: << >>  << T >>  << A >>

> > Is there any possibility to set a FPGA device in tristate mode?

Yes, in VHDL...

IO_PORT <= 'X';

Where IO_PORT can be any name of one of your pins...

NOTE: 'Z' would be high-impedance...

Take care,
>Asher<

<<=>>=<<=>>=<<=>><<=>>=<<=>>=<<=>><<=>>=<<=>>=<<=>>
Asher C. Martin
<<=>>=<<=>>=<<=>><<=>>=<<=>>=<<=>><<=>>=<<=>>=<<=>>
Chippewa Falls, WI 54729
(715) 726-4761
<<=>>=<<=>>=<<=>><<=>>=<<=>>=<<=>><<=>>=<<=>>=<<=>>
asherm@cray.com
http://www.uiuc.edu/~martin2/
<<=>>=<<=>>=<<=>><<=>>=<<=>>=<<=>><<=>>=<<=>>=<<=>>

Article: 23461
Subject: Re: a lot of basic questions - where's the FAQ?
From: "Andy Peters" <apeters.Nospam@nospam.noao.edu.nospam>
Date: Mon, 26 Jun 2000 10:42:34 -0700
Links: << >>  << T >>  << A >>
Eric L wrote in message
<7A8DA474550BB89C.9B85A094293BEF6E.5DC1B83665AC4223@lp.airnews.net>...

>So how would I do it if I bought a Xilinx XC9500?

With a JTAG programmer cable.  There are versions that attach to your
parallel port, your serial port, and now even a USB port ('cept you're hosed
on the USB if you run NT).  Once the part is programmed, it retains its
configuration until you reprogram it.

>well let's say I have a robot that has a xilinx FPGA in it and I program it
to
>be an AND-gate (for discussion purposes) and then I suddenly need it to act
as
>an OR-gate. How would I do something like that? Perhaps the previous
question
>and this question are the same..

What you're describing is called changing the configuration.  This can be
tricky or clever or difficult, depending on which chips you're using.  For
instance, if you use an FPGA (XC4K, Spartan, Virtex), you can have a
standard parallel (byte-wide) EPROM storing multiple configurations.  One of
those would be your AND gate, the other would be the OR.  [Real simple
example!]  Pick an EPROM that's twice as big as what you need for one
configuration.  Use the MSB of the EPROM address bus to select which
configuration gets loaded.  That can be as simple as a DIP switch.  Cycle
power, voila! New configuration.

You can also control the configuration with an on-board microprocessor,
which is fairly simple and clever.

-- a
-----------------------------------------
Andy Peters
Sr Electrical Engineer
National Optical Astronomy Observatories
950 N Cherry Ave
Tucson, AZ 85719
apeters (at) noao \dot\ edu

"A sufficiently advanced technology is indistinguishable from magic"
--Arthur C. Clarke


Article: 23462
Subject: serial 2's C add/substractor msb first
From: erika_uk@my-deja.com
Date: Mon, 26 Jun 2000 18:41:22 GMT
Links: << >>  << T >>  << A >>
hey all,

Is it possible to perform serial two's compliment adder/substractor
most significant bit. i don't want to do any pre or post serial to
parrallel conversion

in papers in the subject

Cheers

--Erika

Sent via Deja.com http://www.deja.com/

Article: 23463
Subject: FPGA and ASIC
From: louis_reginaldjean@my-deja.com
Date: Mon, 26 Jun 2000 18:54:15 GMT
Links: << >>  << T >>  << A >>
I'm in this field, so I'm a little bit confuse. Why FPGA publicity said
something that it's "better than doing ASIC"  or something like that, .
I learned that ASIC mean Aplication Specific Integrate Circuit (if I'm
not wrong). Why, what's the big differecne (and what can we called ASIC
anyway?) ?

Sent via Deja.com http://www.deja.com/

Article: 23464
Subject: inferring global buffers in Leonardo?
From: Matt Gavin <mtgavin@collins.rockwell.com>
Date: Mon, 26 Jun 2000 14:40:58 -0500
Links: << >>  << T >>  << A >>
FPGA gurus,

I am a Synplicity user who is trying Leonardo for the first time.
I am wondering if Leonardo will infer/place global buffers
on internal clocks your design, even if the design
doesn't explicitly place the buffer in the VHDL.  (Synplify does this
inferrence well.)

I have run Leonardo once already, and it placed global buffers
on the three clocks that are on external pins.  However, I have one
internally-generated clock which needs to use the fourth buffer in my
virtex part.  Leonardo didn't find it and place a buffer on it.  Again,
I want the tool to infer the buffer so I don't have to place it in the
VHDL
code.

Can Leonardo do this inferrence? Can I tell it to do this?  If not, I
will have to stick
with Synplify, as I would rather not manually instantiate global buffers
in
my VHDL.

Matt


Article: 23465
Subject: Re: serial 2's C add/substractor msb first
From: Peter Alfke <peter@xilinx.com>
Date: Mon, 26 Jun 2000 13:08:15 -0700
Links: << >>  << T >>  << A >>


erika_uk@my-deja.com wrote:,

>
> Is it possible to perform serial two's compliment adder/substractor
> most significant bit.

Not in binary notation.
Peter Alfke

>


Article: 23466
Subject: Dual Port BlockRAM Timing (Write-Read)
From: Lars <Lotzen@intersci.com>
Date: Mon, 26 Jun 2000 13:16:07 -0700
Links: << >>  << T >>  << A >>
Hi Everybody!

I would like to implement a Dual Port BlockRAM in my design.
The RAM should write and read at the same cycle to the same address.
I tried a (for me) logical solution:

CLKA <= CLK;
CLKB <= not CLK;

to preserve the CLKA -> CLKB setup time (Tbccs).
The clock period is about 70 ns so it should be not a problem, but the simulator shows me a Write Collision and a Read Violation.

Can sombody tell me whats the problem?

Lars Lotzenburger

Article: 23467
Subject: Re: FPGA and ASIC
From: Peter Alfke <peter@xilinx.com>
Date: Mon, 26 Jun 2000 13:41:58 -0700
Links: << >>  << T >>  << A >>


louis_reginaldjean@my-deja.com wrote:

> I'm in this field, so I'm a little bit confuse. Why FPGA publicity said
> something that it's "better than doing ASIC"  or something like that, .
> I learned that ASIC mean Aplication Specific Integrate Circuit (if I'm
> not wrong). Why, what's the big differecne (and what can we called ASIC
> anyway?) ?

Acronyms are dangerous. they take on a life of their own.

RAM for example stands for random access ( which every ROM also has), but

Most people use the name ASIC for circuits that are customized ( through
metal masks) by the chip manufacturer.
Dedicated chips ( like ethernet controllers, hard disc controllers etc)
are NOT called ASICs, although they are very much applications
specific...)

Who says names should be logical?

Peter Alfke


Article: 23468
Subject: Re: Dual Port BlockRAM Timing (Write-Read)
From: Peter Alfke <peter@xilinx.com>
Date: Mon, 26 Jun 2000 14:15:35 -0700
Links: << >>  << T >>  << A >>


Lars wrote:

> Hi Everybody!
>
> I would like to implement a Dual Port BlockRAM in my design.
> The RAM should write and read at the same cycle to the same address.
> I tried a (for me) logical solution:
>
> CLKA <= CLK;
> CLKB <= not CLK;
>
> to preserve the CLKA -> CLKB setup time (Tbccs).
> The clock period is about 70 ns so it should be not a problem, but the simulator shows me a Write Collision and a Read Violation.
>

In Virtex BlockRAMs you must not write and read to/from the same address on the same clock edge, Read and write timing ( both
synchronous) get into each others' hair.
Your solution of using opposite clock edges with good separation will work, provided you keep the address valid for the proper time
period.
No hardware problem here.
I don't know why the simulator ( which one? ) gives you grief.

Peter Alfke, Xilinx Applications


Article: 23469
Subject: Virtex Demo Board
From: "John Fielden" <john.fielden@abcmotorola.com>
Date: Mon, 26 Jun 2000 14:21:04 -0700
Links: << >>  << T >>  << A >>
I'm looking for a Virtex demonstration board.  Something that has at least
one of the larger parts (1000 or 1000E, and above).  I would prefer an E
part.

Does anyone know who makes such a thing?

Thanks,

John Fielden


Article: 23470
Subject: Re: FPGA and ASIC
From: "Carlhermann Schlehaus" <carlhermann.schlehaus@t-online.de>
Date: Mon, 26 Jun 2000 23:24:44 +0200
Links: << >>  << T >>  << A >>
Hi,

<louis_reginaldjean@my-deja.com> schrieb im Newsbeitrag
news:8j88se$olq$1@nnrp1.deja.com...
> I'm in this field, so I'm a little bit confuse. Why FPGA publicity said
> something that it's "better than doing ASIC"  or something like that, .
> I learned that ASIC mean Aplication Specific Integrate Circuit (if I'm
> not wrong). Why, what's the big differecne (and what can we called ASIC
> anyway?) ?

An FPGA is a reconfigurable IC, thus by changing the configuration
information (what's often done by changing the configuration Eprom)
you can at anytime change the IC functionality.
It's somewhat an "ASIC", as it's functionality depends on the
user written (Thus Application specific) code.
But, while the FPGA is reconfigurable an ASIC isn't reconfigurable
at all. The functionality of an ASIC is hardware coded. The
information of the configuration an FPGA derives from it's EPROM
is coded in the chip's layers.
Thus an ASIC isn't your choice if you have to change something,
but for high volume production it's the cheaper solution.

HTH, Carlhermann Schlehaus


Article: 23471
Subject: Re: inferring global buffers in Leonardo?
From: "Mike Johnson" <mikej@freeuk.com>
Date: Mon, 26 Jun 2000 22:40:37 +0100
Links: << >>  << T >>  << A >>
It's no great problem to instantiate a global buffer  - just create a
component called BUFG (See library guide for port details) and drop it in.
I create my own simple simulation model for these primitive's as well,
rather than relying on the large, slow Xilinx provided libs.

Although you can probably persuade the synthesiser, In the past I've found
this easier and quicker than trying to find the magic incantation (which
often it seems to ignore anyway)!

mikej@REMOVEfreeuk.com

Matt Gavin <mtgavin@collins.rockwell.com> wrote in message
news:3957B1CA.A2FEC324@collins.rockwell.com...
> FPGA gurus,
>
> I am a Synplicity user who is trying Leonardo for the first time.
> I am wondering if Leonardo will infer/place global buffers
> on internal clocks your design, even if the design
> doesn't explicitly place the buffer in the VHDL.  (Synplify does this
> inferrence well.)
>
> I have run Leonardo once already, and it placed global buffers
> on the three clocks that are on external pins.  However, I have one
> internally-generated clock which needs to use the fourth buffer in my
> virtex part.  Leonardo didn't find it and place a buffer on it.  Again,
> I want the tool to infer the buffer so I don't have to place it in the
> VHDL
> code.
>
> Can Leonardo do this inferrence? Can I tell it to do this?  If not, I
> will have to stick
> with Synplify, as I would rather not manually instantiate global buffers
> in
> my VHDL.
>
>
>   Matt
>


Article: 23472
From: "Vikram Pasham" <vikram.pasham@xilinx.com>
Date: Mon, 26 Jun 2000 14:43:16 -0700
Links: << >>  << T >>  << A >>
Jamil,

University of Toronto has one of the best FPGA/Reconfigurable logic research groups. Check out their reserch web page at
http://www.eecg.toronto.edu/EECG/RESEARCH/FPGA.html

Vikram Pasham <br>
Xilinx Apps

Article: 23473
Subject: Re: Different ?
From: "R. T. Finch" <robfinch@cyg.net>
Date: Mon, 26 Jun 2000 21:17:31 -0400
Links: << >>  << T >>  << A >>
The confusing aspect is the difference between the number of bits of storage
available and the number of possible states this storage may represent. 40
bits of storage (16+16+8) may have one of 2^40 _possible_ values. However,
it is important to note that it may have only _one_ of these values. IE 40
bits of stoarage can't represent every different possible state at the same
time, only one at a time!

I think you have the right idea. To calculate the potential number of
"states" shouldn't it be 2 * (n+1) not 2 ^ (n+1), because not all the
combinations can be active at the same time (there is only one output). IE.
you're not combining state 0000 and 0001, but just counting them. For
example with a two input function (under the same constraints), there are
eight basic functions (and, or, xor, andc) * 2 for possibly inverting the
output, _not_ 2^(2+1) = 256 functions. Note that as a black box, with two
inputs and a single output, we could model all possible states using a truth
table with just four entries. It all depends what you want to consider to be
a function. I could call this a single function (sigma) or I could claim it
represents eight different functions. However I think we could define a
function, at a minimum, as something that produces a different output than
any other 'function'.
Thus the 9-input Xilinx 4+4+3 FGH tree would result in 2 * (3 + 1) = 8
states for the 3-LUT times(I think this is a product operation here) 2 * 2 *
(4 + 1) = 20 for the two four LUTs which results in a total of 160 possible
states.
This is certainly far less than the 2^40 number (but I'm not comparing
apples to apples here).
We know for certain we cannot have more than 2^(9+1) (1024) states because
there is only nine inputs and all possible outcomes can be represented in
2^10 values. (IE think of a black box with 9 inputs and a single output) 160
possibilities is pretty darn good considering the small amount of ram used.
Note: I think we have to distinguish between the number of possible
functions implemented and the number of possible functions implemented with
unique results. I think the number of possible states may represent the
number of possible functions with unique results (but don't quote me). The
possible number of functions implemented may be quite large (although I
seriously doubt it's anywhere near 2^25), however the number of unique
results they produce (160) is quite limited.
What can be said is that for any possible combination of inputs, there is
only one of 160 states selected. Compare that to the 1024 that would be
available with a 512 bit ram.

The best approach may be to simply state that given x inputs, one of y
different output (states) can be produced. If you wnat to take functions to
the extreme you could claim that an infinite number of functions can be
handled, because you can define the function to be as complex as you like,
however all of these functions would reduce to "given x inputs, one of y
different output (states) can be produced".

If I got the right answer, do I get a prize - pizza would be good  :) ?
Rob

"Tom Burgess" <tom.burgess@home.com> wrote in message
news:39555A39.5345F956@home.com...
> I withdraw the conjecture as stated. If true, one could implement a 512x1
ROM in
> a single CLB which is obviously not the case, darn it.
>
> post in haste, regret at leisure,
> tom
>
> Tom Burgess wrote:
> >
> > Assertion: for an n-input LUT, with input swapping permitted,
> > there are 2^(n+1) possible unique functions possible.
> >
> > Nor-rigorous proof: For n inputs, there are n+1 possible unique states
available,
> > e.g. for 4 inputs, the 5 unique states are {0000, 0001, 0011, 0111,
1111}.
> > (with swapping allowed, 0001 is is equivalent to 1000, 0100, and 0010)
> > Since the n inputs to the LUT can only assume n+1 states, and the
contents of
> > each LUT entry are either 0 or 1, there are therefore 2^(n+1) possible
> > unique LUT patterns (functions) available. So the result for n=4 is 32.
> >
> > Conjecture: the internal structure of the LUT is not important. With
input
> > swapping permitted, any function of n inputs is possible. So a single
> > 512x1 LUT is equivalent to the 9-input Xilinx 4+4+3 FGH tree. Both can
> > therefore implement 2^(9+1) = 1024 unique functions. The proof is left
as
> > exercise for the student :)
> >
> > regards, tom
> >
> > Philip Freidin wrote:
> > >
> > > In article <8j2b2o$ar3$1@news.ust.hk>,
> > > WU Chi Hang FOX  <eefox@uxmail.ust.hk> wrote:
> > > >       First, thanks Rickman. However, I am really stucked at that, I
am
> > > >not asking about HW questions, I really want to count how many
fuctions
> > > >that a cascaded LUTs can implement.
> > > >       For 1-bit LUT, I know there are 4 functions
> > > >
> > > >                               Output
> > > >       Input   Function 1      2       3       4
> > > >       0                0      0       1       1
> > > >       1                0      1       0       1
> > >
> > > Fine. You have enumerated all the functions of a 1 input LUT
> > >
> > > Inputs     Number of memory bits    Functions
> > > 1             2                       4
> > > 2             4                      16
> > > 3             8                     256
> > > 4            16                   65536
> > > N            2^N                  2^(2^N)
> > >
> > > >Function 1 is a zero function, Function 2 is follower, Function 3 is
NOT
> > > >Function 4 is a one function.
> > >
> > > So depending on your view of life, not all of these are 'interesting'.
> > >
> > > Function 1 and 4 ignore the input, function 2 is a wire, and function
3
> > > is an inverter. Maybe only the inverter case is interesting, depends
what
> > > you had for breakfast.
> > >
> > > >       However, what I am concerning is that, even there are 4
functions,
> > > >utimatelly, it is only 0 and 1 pass into the LUT, so, it does not
matter.
> > > >So, what I think is, no-matter it is cascaded or not, the maximum
> > > >function is determined by the last LUT, so for this case, the no. of
functions
> > > >is 2^4.
> > >
> > > For this case maybe, but remember that in the following LUT, it too
has
> > > cases where the inputs are ignored, or the output is the inversion or
> > > pass thru of one input, and other inputs are ignored. Which do you
> > > consider interesting?
> > >
> > > >       Then bringing back to the XC4000, if that is the case, then
why
> > > >the total number of funtions is 2^40 instead of 2^8 ?
> > >
> > > Since the XC4000 CLB has 40 bits total in the two 4-LUTs, and the one
> > > 3-LUT, there are exactly 2^40 possible configurations.
> > >
> > > I believe they are not all interesting, because MANY of these ignore
some
> > > of the inputs, or are synonyms of each other, with just the input
signals
> > > swapped. The reason that the pin swaped equivalent functions are not
> > > interesting, is because the place and route software does this pin
> > > swapping all the time, and permutes the LUT contents to account for
the
> > > pin swapping. I wouldn't be surpised if the number of unique patterns
is
> > > less than 2^25. The only way to find out the real number may be
through
> > > an exhaustive search.
> > >
> > > Philip Freidin


Article: 23474
(removed)