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Thats a very interesting point. I'm not famillilar with a "Card Present" signal, I always thought the bios polls all slots and tryes to figure out if and what is plugged in. I can see how a very slow FPGA initialization, could make a card invisible. Even is the clock is not turned off (I know my bios has an option to turn it off or leave it always on), the bios would not know of the card. The PCI bus spec, I believe, clearly specifies the time after a reset that a device has to respond. So you must make sure that your FPGA finishes initialitzation within that time or you will be not PCI compliant ... Good Luck, bkk In article <b2I65.9675$HK2.188166@news20.bellglobal.com>, "Dan" <daniel.deconinck@sympatico.ca> wrote: > Hello, > > When PCI slots are unused, some motherboards disable the PCI CLK to that > particular slot. (I just learned this on the pcisig.com mail reflector) > > I understand they use the 'Card Present' signal to determine if the slot is > populated. > > Is it possible that some mother boards incorrectly assume that a slot is > empty if it contains a FPGA based contoller which takes some time to > initialize after power up. > > Sincerely > Daniel DeConinck > > Sent via Deja.com http://www.deja.com/ Before you buy.Article: 23551
[REPOST] Take two identical PRBS generators, with a n bits long shift register each (2^n-1 will be the total length of he PRBS). Put the first to work as a generator of a PRBS. The output bitstream will be the test signal. Now lets go to the second generator. Disconnect the signal going to the D input of the first flip flop in the chain, usually the output of an XOR gate. Lets call the XOR output the "next bit prediction". Feed the bitstream to the D input. Look the open output of the XOR and compare it with the stream. If the stream is a PRBS (or an all zeros signal) and there are no errors, after n bits, both the XOR output and the stream will become identical. If there is a single error in the bitstream, the XOR output and the bitstream will become diferent. This is an error indication. But for each single input error, you will get several error indications. The first one belongs to a true error, but the remaining ones correspond to the shift register being "contaminated" with the input error. There is an aditional error for each tap in the shift register (error multiplication). To avoid that the usual strategy is to begin with the receiver in such "open loop" configuration, then wait until the input stream has a long secuence of bits (m bits) without error and then close the feedback loop, avoiding the "contamination" of the receiver shift register. When the loop is closed, the receiver is said "on sync" and the measurement can start, comparing the XOR output with the input stream and counting errors. You have to put a 2 input mux in front of your first D input, to select from the bitstream or from the XOR output. The control signal can be derived from a counter that resets when there is an error and stops (and never again reseting) after m bits without error. The same control signal can gate the error counting. How long has to be m depends on the probability you want of a false "sync" in presence of a random signal. Any n bit long secuence (except the "all zeros" one) can be found within the total 2^n-1 PRBS. But adding a single bit, the odds of finding the new n+1 secuence in a PRBS will be 0.5, for two bits will be 0.25 and so on. If you wait 32 aditional bits before declaring "sync", the odds of a false trigger will be 1/(2^32), small enough for many purposes, and your counter will only be 5 bit long. To complete the state machine, you have to go from "sync" to "off sync" when the stream is not anymore a PRBS. The usual criteria is a slip condition (more on that later) or a very high bit error rate (0.2) for a long period (1s). This is better a software implemented decision. You also have to deal with the "all zeros" exception to the rule. The easiest way is to put a n-wide NOR gate with its inputs connected to the n outputs of the FFs, and adding an extra or gate to combine its output with the XOR output. The new "next bit prediction" will say that after n consecutive bits at zero, the next one should have to be a logical one. And with an "all zeros" input, it will not be, and sync will not be gained. And lastly, you can also detect a slip condition (extra o missing bits due to false clocking) by looking at the error output. If a slip happened, the error itself will be a PRBS again!, and as such, a second receiver connected to it will say "sync". This bases on a property of PRBSs: The XOR (comparison) of two PRBS delayed any number of bits (same polynomial, of course) is again a PRBS with the same polynomial (or the "all zeros" signal). Hope this helps Juan-Luis Lopez Rodriguez jl.lopez@REMOVETHIS.ieee.org SpainArticle: 23552
I know Digikey sells Xilinx chips online, but is there another company? I did a search through a lot of online electronics but none sold them individually. I'm looking for a place that will also sell 8051's and also I wanted to have another source for the parts to know I'm gettnig a good price. Thanks EricArticle: 23553
Dear all, I am considering implementing an MPEG layer 2 audio decoder in an fpga. Around 128kbit/s. What I need to know is.... (1) How complex is the decoder, how much logic would I need? (2) Do you have to pay to use MPEG in your own codecs? All help much appreciated. Gary.Article: 23554
Dear friends,
I want to know what is meant by delta
in timing report. The timing report produced by
view synthesis tool after synthesizing my multiplier
design indicates total delta as 0.00. What does this
mean. The timing report is as below.
*********************************************
Timing Report
*********************************************
Output Delay Required Required Load
External Cap
------------------------------------------------------------------------
-----
rise fall rise fall (Buffering)
(Timing) ---------------- --------------
------------ ---------- PROD[31] 19.00 19.00 30.00
30.00 0.0 0.0 PROD[30] 18.00 18.00 30.00
30.00 0.0 0.0 PROD[29] 18.00 18.00 30.00
30.00 0.0 0.0 PROD[28] 18.00 18.00 30.00
30.00 0.0 0.0 PROD[27] 18.00 18.00 30.00
30.00 0.0 0.0 PROD[26] 18.00 18.00 30.00
30.00 0.0 0.0 PROD[25] 18.00 18.00 30.00
30.00 0.0 0.0 PROD[24] 18.00 18.00 30.00
30.00 0.0 0.0 PROD[23] 18.00 18.00 30.00
30.00 0.0 0.0 PROD[22] 18.00 18.00 30.00
30.00 0.0 0.0 PROD[21] 18.00 18.00 30.00
30.00 0.0 0.0 PROD[20] 18.00 18.00 30.00
30.00 0.0 0.0 PROD[19] 18.00 18.00 30.00
30.00 0.0 0.0 PROD[18] 18.00 18.00 30.00
30.00 0.0 0.0 PROD[17] 18.00 18.00 30.00
30.00 0.0 0.0 PROD[16] 18.00 18.00 30.00
30.00 0.0 0.0 PROD[15] 16.00 16.00 30.00
30.00 0.0 0.0 PROD[14] 16.00 16.00 30.00
30.00 0.0 0.0 PROD[13] 16.00 16.00 30.00
30.00 0.0 0.0 PROD[12] 16.00 16.00 30.00
30.00 0.0 0.0 PROD[11] 16.00 16.00 30.00
30.00 0.0 0.0 PROD[10] 16.00 16.00 30.00
30.00 0.0 0.0 PROD[9] 16.00 16.00 30.00
30.00 0.0 0.0 PROD[8] 16.00 16.00 30.00
30.00 0.0 0.0 PROD[7] 16.00 16.00 30.00
30.00 0.0 0.0 PROD[6] 16.00 16.00 30.00
30.00 0.0 0.0 PROD[5] 16.00 16.00 30.00
30.00 0.0 0.0 PROD[4] 16.00 16.00 30.00
30.00 0.0 0.0 PROD[3] 14.00 14.00 30.00
30.00 0.0 0.0 PROD[2] 14.00 14.00 30.00
30.00 0.0 0.0 PROD[1] 13.00 13.00 30.00
30.00 0.0 0.0 PROD[0] 5.00 5.00 30.00
30.00 0.0 0.0
------------------------------------------------------------------------
----
Total Delta 0.00 0.00
Max. Delay 19.00 19.00
Min. Delay 5.00 5.00
THANK YOU,
BANESHWAR
Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 23555Hi, there, I do logic design and implemention with FPGA for a couple of years, in which flow I synthesis the design from RTL to Gate-level myself. While having verified the design with FPGA prototype, we export it to ASIC flow with DC as synthesis tool and Avanti backend tool. However, the design house I work for is a startup one, having a design flow not that clear and mature as those big ones. So, now I am facing a problem that if I should synthesis the design in ASIC style myself(My HDL design team) or "sign off" it to the backend team and leave the job to them? What you experienced people in formal design-house do as tradition? AFAIK, the impact of DSM technology trend on ASIC design flow brings more and more physical information to synthesis, like AmbitPKS and Synopsys PhysicalCompiler suggest we do. To make things clear, sure we do module synthesis of each block before we export them to P&R. This ensure that the design is synthesisable and timing optimized. Thanks, Simon.ZArticle: 23556
> Warning: vhdlsim,105:
> /INTERFACE/FIFO/MEM/COMPONENT was not instanced because it is
> unbound.
> Warning: vhdlsim,105:
> /INTERFACE/FIFO/CONTROL/COMPONENT was not instanced because it is
> unbound.
You got to set your VSS-environment correctly (define all those simprims
libs) and all these designs have to be translated.
Check the library name and whether the design of the fifo is
in the corresponding directory.
I know, it is a mess.
Andreas
---------------------------------------------------------------
Andreas C. Doering
Medizinische Universitaet zu Luebeck
Institut fuer Technische Informatik
Ratzeburger Allee 160
D-23538 Luebeck Germany
Tel.: +49 451 500-3741, Fax: -3687
Email: doering@iti.mu-luebeck.de
Home: http://www.iti.mu-luebeck.de/~doering
quiz, papers, VHDL, music
"The fear of the LORD is the beginning of ... science" (Proverbs 1.7)
----------------------------------------------------------------
Article: 23557Brenda wrote: > > [Image] ------------------------(also sent by email with the post attached) Attention!: In posting a binary on the newsgroup comp.arch.embedded you have violated numerous RFC's of the InterNet and your terms of service with your Internet Service Providers and complaints can result in your account with your ISP or your relationship with your upstream providers being canceled. Get used to the idea quickly since you're clearly a newbie to the Internet and especially to the Newsgroups of UseNet!! You can cuss and spew filth, anger and hate on newsgroups, and you can post off-topic irrelevancies, but the people who run the Net by owning the machines and the band-width it depends on do NOT like it when binaries are posted to NON-binary newsgroups like c.a.e.. In doing that you threaten their bandwidth agreements with the other people who own the net and their cooperation with you, even if you DO think you own your own domain name!! If we decide to complain right now tonight in sufficient numbers to your provider or upstream you can be cancelled summarily overnight without refund of any deposited monies for the current payment term. If you look at the newsgroup charters and common practices before posting you can easily tell why nobody else posts binaries on NON-binaries newsgroups, and it is NOT because nobody ever thought of doing it before, it is because everyone who tried it was tossed off their ISP for TOS violations!!! On the Internet you can talk dirty, post drivel, and say anything and nobody cares, but if you threaten the structure of the newsgroups or spam email you will find your connection keeps going away until your cash reserves restoring it are completely depleted. The only other things that can get you turned off are actionable libel/slander or copyright violations that compromise your ISP in civil court, or kiddy porn that threatens them in criminal court. Get used to the idea, you can post your binary to any binary group, from the schematics group to porn groups and nobody cares, but if you do this on the text-ONLY groups again we'll get your little asshole turned the fuck off, you dig?? -Steve -- -Steve Walz rstevew@armory.com ftp://ftp.armory.com:/pub/user/rstevew -Electronics Site!! 1000 Files/50 Dirs!! http://www.armory.com/~rstevew Europe Naples Italy: http://ftp.unina.it/pub/electronics/ftp.armory.comArticle: 23558
Hello there, I'm a student doing the first steps with Foundation Series 2.1i. I've tried my first example in Schematic, it is possible to download it on my Demoboard (UniDig5). But there is no output on the pins. I've set LOC=P48 in Schematic Editor->Symbol Properties. Could you tell me, what is my mistake? Many thanks for your help. AndreasArticle: 23559
The PCI expansion slots have two PRSNT# pins to allow presence detection. These are also indicating the power requirement (7/15/25W) of the expansion card. These are usually not fed to any PCI device, but tied high/low on the card. Regards, - Olaf <bkk411@hotmail.com> wrote in message news:8jfr6r$eka$1@nnrp1.deja.com... > > > Thats a very interesting point. I'm not famillilar with a > "Card Present" signal, I always thought the bios polls all > slots and tryes to figure out if and what is plugged in. > > I can see how a very slow FPGA initialization, could make > a card invisible. Even is the clock is not turned off (I know > my bios has an option to turn it off or leave it always on), > the bios would not know of the card. > > The PCI bus spec, I believe, clearly specifies the time after > a reset that a device has to respond. So you must make sure > that your FPGA finishes initialitzation within that time or > you will be not PCI compliant ... > > Good Luck, > bkk > > > In article <b2I65.9675$HK2.188166@news20.bellglobal.com>, > "Dan" <daniel.deconinck@sympatico.ca> wrote: > > Hello, > > > > When PCI slots are unused, some motherboards disable the PCI CLK to > that > > particular slot. (I just learned this on the pcisig.com mail > reflector) > > > > I understand they use the 'Card Present' signal to determine if the > slot is > > populated. > > > > Is it possible that some mother boards incorrectly assume that a slot > is > > empty if it contains a FPGA based contoller which takes some time to > > initialize after power up. > > > > Sincerely > > Daniel DeConinck > > > > > > > Sent via Deja.com http://www.deja.com/ > Before you buy.Article: 23560
hey all do Xilinx provide the different routing ressources delays??? if yes could you please post the URL( i can't find any trace ...) Thanks --Erika In article <395B6D20.B06FA5AC@yahoo.com>, Rickman <spamgoeshere4@yahoo.com> wrote: > This may give you an estimate for a "theoretical" speed, I would not use > it for any design that I did not understand fully. Both the "one LUT" > assumption and the "short routing delay" assumption will be invalidated > by specific items in many designs. > > For example, if you are designing a finite state machine (FSM) to > control some circuit, you may have too many inputs to a single state to > be able to define the next state function in a single CLB (two linked > LUTs). This often happens. Then if you have any long nets with high fan > out, such as a clock enable, you may have to allow two or three LUT > delays to distribute this signal. > > Pipelining can help, but it can not be used when you need to have > feedback in the path, such as in a FSM. So it is best to know enough > about your design to be able to at least determine the number of inputs > to every logic function. > > Jimmy wrote: > > > > Hi Folks, > > > > Having a particular FPGA in hand (with a specific speed grade), How can > > someone assess the performance of a particular design. In other terms, how > > can you know the maximum obtainable speed for a particular design. The > > question might seem vague but I will illustrate: > > Say you want to do a bit serial convolution on an XC4000 chip. What is the > > best speed you can get. I can see that for a heavily pipeline design, you > > can assume that the maximum delay is the CLB delay (FF or LUT). How about > > the routing? Is it fair to assume that in a good design the routing delay is > > equal to the logic delay and so You can say that the best period time (the > > minimum) you can get is 2*CLB_delay?? > > > > Any input is much appreciated. > > > > Cheers. > > -- > > Rick Collins > > rick.collins@XYarius.com > > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design > > Arius > 4 King Ave > Frederick, MD 21701-3110 > 301-682-7772 Voice > 301-682-7666 FAX > > Internet URL http://www.arius.com > Sent via Deja.com http://www.deja.com/ Before you buy.Article: 23561
"Andreas Wstefeld" wrote: > Hello there, > > I'm a student doing the first steps with Foundation Series 2.1i. I've tried > my first example in Schematic, it is possible to download it on my > Demoboard (UniDig5). But there is no output on the pins. I've set LOC=P48 in > Schematic Editor->Symbol Properties. Could you tell me, what is my mistake? > Many thanks for your help. > > Andreas You should check the map report file, which will indicate if the pad location constraints were effectively applied to your design (sometimes Foundation get lost between the synthesis and implementation constraints file). Hope it can help StevenArticle: 23562
Jamil Khatib wrote: > Hi, > Could you please mention some good universites in Canada "English > speekers area" to continue my graduate studies in the Reconfigurable > Computing and its EDA feilds. > > Please email me at khatib@opencores.org > > Thanks in advance > Jamil Khatib Check out University of Waterloo at www.uwaterloo.ca or McMaster University at www.mcmaster.ca Jamie Neilson www.gallowaysearch.com jneilson@gallowaysearch.comArticle: 23563
Hi, i<m new in ISP with CPLD and i have an error uploading a version in my CPLD. Every connection seems do be ok but i always get that error... Any idea? Log file : Loading Boundary-Scan Description Language (BSDL) file 'C:/Fndtn/xc9500/data/xc95288.bsd'.....completed successfully. Checking boundary-scan chain integrity...ERROR:JTag - Boundary-scan chain test failed at bit position '0' on instance 'projet24(Device1)'. Check that the cable, system and device JTAG TAP connections are correct, that the target system power supply is set to the correct level, that the system grounds are connected and that the parts are properly decoupled. ERROR:JTag - Boundary scan chain has been improperly specified. Please check your configuration and re-enter the boundary-scan chain information. Boundary-scan chain validated unsuccessfully. ERROR:JTag - : The boundary-scan chain has not been declared correctly. Verify the syntax and correctness of the device BSDL files, correct the files, reset the cable and retry this command.Article: 23564
http://www.insight-electronics.com/ "Eric L" <lamb_baa@hotmail.com> wrote in message news:B3D6F34D307FD7F7.68D5D965A0540E2E.DAA6D9429C5D41F2@lp.airnews.net... > I know Digikey sells Xilinx chips online, but is there another company? I did a > search through a lot of online electronics but none sold them individually. I'm > looking for a place that will also sell 8051's and also I wanted to have > another source for the parts to know I'm gettnig a good price. > > > Thanks > Eric >Article: 23565
Another question ... is it necessary to connect all Power pins? thanks Simon Bilodeau <simon.bilodeau@htrc.com> wrote in message news:ms575.1821$qq3.54959@weber.videotron.net... > Hi, > > i<m new in ISP with CPLD and i have an error uploading a version in my CPLD. > Every connection seems do be ok but i always get that error... > > Any idea? > > Log file : > > Loading Boundary-Scan Description Language (BSDL) file > 'C:/Fndtn/xc9500/data/xc95288.bsd'.....completed successfully. > Checking boundary-scan chain integrity...ERROR:JTag - Boundary-scan chain > test failed at bit position '0' on instance 'projet24(Device1)'. > Check that the cable, system and device JTAG TAP connections are correct, > that the target system power supply is set to the correct level, > that the system grounds are connected and that the parts are properly > decoupled. > ERROR:JTag - Boundary scan chain has been improperly specified. Please > check your configuration and re-enter the boundary-scan chain information. > Boundary-scan chain validated unsuccessfully. > ERROR:JTag - : The boundary-scan chain has not been declared correctly. > Verify the syntax and correctness of the device BSDL files, correct the > files, > reset the cable and retry this command. > > >Article: 23566
Xilinx recommend stopping clocks into the device because it can cause JTAG problems. This seems a bit lame to say the least, but I've seen it with one 95XX device (I think!), and luckily I'd put in a link to stop the clock, even though I believed this would never happen. The symptom was unreliable recognition of the device chain (four xc95XXxl devices). I was unable to program at all. Alun CamdigitalArticle: 23567
In article <395C4EAD.4FD6@armory.com>, rstevew@armory.com says... > Get used to the idea, you can post your binary to any binary group, > from the schematics group to porn groups and nobody cares, but if you > do this on the text-ONLY groups again we'll get your little asshole > turned the fuck off, you dig?? > -Steve > > Does that mean we can now say "fuck" with you, steve, but we cant post any binaries? How about HTML? Cant we even   anymore?Article: 23568
Simon Bilodeau wrote in message ...
>Another question ... is it necessary to connect all Power pins?
Yes.
-- a
-----------------------------------------
Andy Peters
Sr Electrical Engineer
National Optical Astronomy Observatories
950 N Cherry Ave
Tucson, AZ 85719
apeters (at) noao \dot\ edu
"A sufficiently advanced technology is indistinguishable from magic"
--Arthur C. Clarke
Article: 23569
Hello All,
I use a mixed design entry style where I do most of the work in Viewlogic
schematics but through in a few key VHDL behaviors. After I am satisfied
with my simulation I synthesize those VHDL blocks using Synplify. What I
would like to do is convert the synthesized netlists into schematics for
viewing.
In the past we used Exemplar for synthesis and we could run the netlists
through edifneti and viewgen to get a machine generated schematic. Now we
use Synplicity which puts LUT4, LUT3 and LUT2 primitives into the netlist.
These components are from the virtex library and do not have simulation
models.
I've found that Xilinx provides two utilities, ngdbuild and ngd2edif, that
can be used to produce a simulatable edif netlist. The resulting netlist
from this path contains x_lut4, x_lut3 and x_lut2 cells from the SIMPRIMS
library. Unfortunately these cells do not show up in the SIMPRIMS library so
I cannot generate the schematic.
Can anyone tell me how to generate a Viewlogic schematic from Synplify edif
output?
Thanks for any advice.
********************************************************************
Pete Dudley
Sandia National Labs
Dept 2336 MS 0505
PO BOX 5800
Albuquerque, NM 87185
voice: 505.844.5565 fax: 505.844.2925 email: padudle@sandia.gov
http://www.sandia.gov/RADAR/sarcap.html
Signal Processing in Hardware and Software
********************************************************************
Article: 23570I am not familiar with Synplicity and the formats it generates in the EDIF output. But I don't think the LUT primatives contain logic. When I have worked with Xilinx at the schematic level the LUT primatives all were just placeholders and you had to have separate gates for the logic. Do they do that in the EDIF files as well? I do know the FPGA Express uses both logic and LUTs. If Synplicity does not use both, how do they indicate the logic that is contained in the LUTs? If the LUTs are only there for mapping, then you likely can remove them for logical simulation. I would bet that a program or script could be written to edit them out. I know this is yet another step and a PITA, but that is the way FPGA design work is. Pete Dudley wrote: > > Hello All, > > I use a mixed design entry style where I do most of the work in Viewlogic > schematics but through in a few key VHDL behaviors. After I am satisfied > with my simulation I synthesize those VHDL blocks using Synplify. What I > would like to do is convert the synthesized netlists into schematics for > viewing. > > In the past we used Exemplar for synthesis and we could run the netlists > through edifneti and viewgen to get a machine generated schematic. Now we > use Synplicity which puts LUT4, LUT3 and LUT2 primitives into the netlist. > These components are from the virtex library and do not have simulation > models. > > I've found that Xilinx provides two utilities, ngdbuild and ngd2edif, that > can be used to produce a simulatable edif netlist. The resulting netlist > from this path contains x_lut4, x_lut3 and x_lut2 cells from the SIMPRIMS > library. Unfortunately these cells do not show up in the SIMPRIMS library so > I cannot generate the schematic. > > Can anyone tell me how to generate a Viewlogic schematic from Synplify edif > output? > > Thanks for any advice. > > ******************************************************************** > Pete Dudley > Sandia National Labs > Dept 2336 MS 0505 > PO BOX 5800 > Albuquerque, NM 87185 > voice: 505.844.5565 fax: 505.844.2925 email: padudle@sandia.gov > http://www.sandia.gov/RADAR/sarcap.html > Signal Processing in Hardware and Software > ******************************************************************** -- Rick Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 23571
On 23 Jun 2000 03:11:29 GMT nweaver@boom.CS.Berkeley.EDU (Nicholas C. Weaver) wrote: >In article <3952CB49.F5DAEC24@yahoo.com>, >Rickman <spamgoeshere4@yahoo.com> wrote: >>I agree Peter. The difference between $100 and $0 is virtually $0 for a >>real project or a real company. But then if that is so, why does Xilinx >>need to charge the $100? > > Every piece of software sold/given away by Xilinx probably end >up burning support time. Xilinx probably doesn't want joe-random-user >to be taking up time unless they are at least remotely serous about >actually buying parts, and charging some money for it serves to >prevent the ubercasual person from purchasing the software. I would >guess that each development package used results in at least 1 call to >tech support. The only compulsory support is the registration lock file. I doubt that any software released "for free and without support" will burn any support time from hobbist. Even paying, distribuitors don't help. How could one expect to get support from a free software, other than the available online? Have you heared about IV3NWV YAM?. Some amateur projects won't consume more than a test part by the author, but maybe that tens of thousands will be bought by others to build it, even commercially. Well may be not much and sparse anyway. I think that this is just preventing hobbists learning and releasing nice free designs. > They do have freebee demos which allow all BUT the final >mapping, at least according to the web site. That will prevent the support calls, or the project completion? 73's de Luis mail: melus0(@)teleline(.)es Ampr: eb7gwl.ampr.org http://www.terra.es/personal2/melus0/ <- PCBs for Homebrewed HardwareArticle: 23572
Nope. The LUTs have attributes attached which correspond to the LUT SRAM contents and thus define the LUT logic. Rickman wrote in message <395D26F6.32FA2365@yahoo.com>... >I am not familiar with Synplicity and the formats it generates in the >EDIF output. But I don't think the LUT primatives contain logic. When I >have worked with Xilinx at the schematic level the LUT primatives all >were just placeholders and you had to have separate gates for the logic. >Do they do that in the EDIF files as well? I do know the FPGA Express >uses both logic and LUTs. If Synplicity does not use both, how do they >indicate the logic that is contained in the LUTs? > >If the LUTs are only there for mapping, then you likely can remove them >for logical simulation. I would bet that a program or script could be >written to edit them out. I know this is yet another step and a PITA, >but that is the way FPGA design work is.Article: 23573
Simon, If you haven't already, you might want to check the Xilinx Answers database at http://support.xilinx.com. In the Answers Search Field try typing something like " bit position '0' ". Answer record #2881 may help. -Hobson Xilinx Applications Simon Bilodeau wrote: > Hi, > > i<m new in ISP with CPLD and i have an error uploading a version in my CPLD. > Every connection seems do be ok but i always get that error... > > Any idea? > > Log file : > > Loading Boundary-Scan Description Language (BSDL) file > 'C:/Fndtn/xc9500/data/xc95288.bsd'.....completed successfully. > Checking boundary-scan chain integrity...ERROR:JTag - Boundary-scan chain > test failed at bit position '0' on instance 'projet24(Device1)'. > Check that the cable, system and device JTAG TAP connections are correct, > that the target system power supply is set to the correct level, > that the system grounds are connected and that the parts are properly > decoupled. > ERROR:JTag - Boundary scan chain has been improperly specified. Please > check your configuration and re-enter the boundary-scan chain information. > Boundary-scan chain validated unsuccessfully. > ERROR:JTag - : The boundary-scan chain has not been declared correctly. > Verify the syntax and correctness of the device BSDL files, correct the > files, > reset the cable and retry this command.Article: 23574
In article <8jfpuk$dhk$1@nnrp1.deja.com>, bkk411@hotmail.com () wrote: > In article <395AF87F.D4C44FDB@stud.uni-karlsruhe.de>, > Armin Mueller <armin.mueller@stud.uni-karlsruhe.de> wrote: > > Hello, > > > > is there some free PCI 33/32 core available I'm not aware of, besides > > > > * the comp.arch.fpga faq > > * Xilinx > > * Altera > > I didn't know Xilinx gives away their PCI core. Last time I checked > they wanted $15K + royaltis ... > Same for Altera - don't remember the price .... Altera have free code, non-free in-house code and non-free third-party code available. I rolled my own after studying the free stuff. > > Would love to see a *decent* e.g. synthesisable and complient > free core !!! > > > * Cypress When I tried to get the free Cypress stuff last year, they didn't have the more complex versions actually finished, despite listing them on their web site. -- Steve Rencontre http://www.rsn-tech.demon.co.uk //#include <disclaimer.h>
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