Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarApr2017

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search

Messages from 23575

Article: 23575
Subject: Re: PCI with Xilinx controller
From: steve (Steve Rencontre)
Date: Sat, 1 Jul 2000 03:00 +0100 (BST)
Links: << >>  << T >>  << A >>
In article <b2I65.9675$HK2.188166@news20.bellglobal.com>, 
daniel.deconinck@sympatico.ca (Dan) wrote:

> Hello,
> 
> When PCI slots are unused, some motherboards disable the PCI CLK to that
> particular slot. (I just learned this on the pcisig.com mail reflector)
> 
> I understand they use the 'Card Present' signal to determine if the 
> slot is
> populated.
> 
> Is it possible that some mother boards incorrectly assume that a slot is
> empty if it contains a FPGA based contoller which takes some time to
> initialize after power up.

Without looking it up, I'm pretty sure that any presence-detect lines 
should be hard-wired.

--
Steve Rencontre		http://www.rsn-tech.demon.co.uk
//#include <disclaimer.h>

Article: 23576
Subject: Re: Looking for 'FREE' FPGA software
From: Rickman <spamgoeshere4@yahoo.com>
Date: Fri, 30 Jun 2000 23:55:41 -0400
Links: << >>  << T >>  << A >>
Luis Yanes wrote:
> 
> On 23 Jun 2000 03:11:29 GMT nweaver@boom.CS.Berkeley.EDU (Nicholas C.
> Weaver) wrote:
> >       Every piece of software sold/given away by Xilinx probably end
> >up burning support time.  Xilinx probably doesn't want joe-random-user
> >to be taking up time unless they are at least remotely serous about
> >actually buying parts, and charging some money for it serves to
> >prevent the ubercasual person from purchasing the software.  I would
> >guess that each development package used results in at least 1 call to
> >tech support.
> 
> The only compulsory support is the registration lock file.
> I doubt that any software released "for free and without support" will burn
> any support time from hobbist. Even paying, distribuitors don't help.
> How could one expect to get support from a free software, other than the
> available online?
> 
> Have you heared about IV3NWV YAM?. Some amateur projects won't consume more
> than a test part by the author, but maybe that tens of thousands will be
> bought by others to build it, even commercially. Well may be not much and
> sparse anyway.
> 
> I think that this is just preventing hobbists learning and releasing nice
> free designs.
> 
> >       They do have freebee demos which allow all BUT the final
> >mapping, at least according to the web site.
> 
> That will prevent the support calls, or the project completion?
> 73's de Luis

I agree. It is rather pointless for an engineer to spend a lot of time
trying to evaluate software and then not be able to generate a
bitstream. I have been offered various software packages for
"evaluation" which come with some form of crippling, either a time limit
which is often as short as 20 days, or limitations on printing or saving
your work. All of these prevent me from seriously exercising the
software. 

This may be a valid practice for companies that make a living selling
software, but FPGA companies are trying to sell you chips! But the
bottom line is that the price is intended to be a filter. No company
that is interested in buying a quantity of chips is going to let a $100
price tag deter them. 

BTW, I have never heard of IV3NWV YAM. I take it this is an acronym for
something?


-- 

Rick Collins

rick.collins@XYarius.com

Ignore the reply address. To email me use the above address with the XY
removed.



Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX

Internet URL http://www.arius.com

Article: 23577
Subject: Re: Maximum Speed on obtainable on FPGAs?
From: murray@pa.dec.com (Hal Murray)
Date: 1 Jul 2000 04:26:02 GMT
Links: << >>  << T >>  << A >>

> Say you want to do a bit serial convolution on an XC4000 chip. What is the
> best speed you can get. I can see that for a heavily pipeline design, you
> can assume that the maximum delay is the CLB delay (FF or LUT). How about
> the routing? Is it fair to assume that in a good design the routing delay is
> equal to the logic delay and so You can say that the best period time (the
> minimum) you can get is 2*CLB_delay??

That's a pretty good first cut.

If you really want to know the answer, I suggest you make a toy
design and push it through the tools and examine the output of the
timing report.  That will give you a feel for what types of routing
are good or expensive.  Try things like CLB-CLB when they are next
to eachother, 2 grid units apart, 5 units...  And CLB to 1 load, 2
loads, 5 loads...  Horizonal, vertical, diagonal...

One case/pattern that I would check carefully would be using long
lines.  You really want them if you ever do something like a clock
enable to load a register or switch a mux.  I'll bet that path is
a bit slower than 2x the CLB delay.

There are lots of tricks to making FPGA designs go fast.  I think
they all require a lot of hand work.  Knowing the design and hand
placing the key CLBs is probably required.  (That may be all of them.)

Adding pipeline stages is clearly a big win.  (Your brain might
not like it.)  Replicating logic combined with pipeline stages
can be a big help if you need to use a signal in several places
that are far apart.


Don't forget the timing at the IO pads.

-- 
These are my opinions, not necessarily my employers.  I hate spam.

Article: 23578
Subject: Re: Which notebook is for you?
From: Branko Badrljica <brankob@avtomatika.com>
Date: Fri, 30 Jun 2000 22:42:53 -0700
Links: << >>  << T >>  << A >>


Don wrote:

> In article <395C4EAD.4FD6@armory.com>, rstevew@armory.com says...
> > Get used to the idea, you can post your binary to any binary group,
> > from the schematics group to porn groups and nobody cares, but if you
> > do this on the text-ONLY groups again we'll get your little asshole
> > turned the fuck off, you dig??
> > -Steve
> >
> >
> Does that mean we can now say "fuck" with you, steve, but we cant post
> any binaries? How about HTML? Cant we even &nbsp anymore?

Man gets angry about usenet abuse. What's wrong with that ?
It feels nice to let some steam out once in a while, even on public
cyberplace, especially if one expresses majority's opinion...


Regards,


Branko

Article: 23579
Subject: Powering XCV300
From: "Ben" <ejhong@future.co.kr>
Date: Sat, 01 Jul 2000 05:56:57 GMT
Links: << >>  << T >>  << A >>
I built up a PCI card with Virtex, but the card doesn't seem to show some
robustness in operation.
When I put the card under a massive test operation, the card often goes into
failure after several hours of working, and sometimes after serveral
minutes.

From some experiments with a controllable power supply, I came to have a
mere conjecture that the 2.5V power supply from a linear regulator(LT1076)
is not really tracking fast enough to meet the changes in Virtex' current
consumption. When the 2.5V power is supplied from power supply, the card
kept working over night.

I hope I can get a tip on building up a stable 2.5V for Virtex from 3.3V
power supply. I used to use 5V power supply for the card, but the 5V power
supply has less current capacity than 3.3V power supply of my system, so I
think I need to change it. Do you know a 3.3V-to-2.5V low drop out regulator
that works well with Virtex300?


Article: 23580
Subject: Re: Which notebook is for you?
From: Steve <rstevew@armory.com>
Date: Sat, 01 Jul 2000 03:04:50 -0700
Links: << >>  << T >>  << A >>
Don wrote:
> 
> In article <395C4EAD.4FD6@armory.com>, rstevew@armory.com says...
> > Get used to the idea, you can post your binary to any binary group,
> > from the schematics group to porn groups and nobody cares, but if you
> > do this on the text-ONLY groups again we'll get your little asshole
> > turned the fuck off, you dig??
> > -Steve
> >
> >
> Does that mean we can now say "fuck" with you, steve, but we cant post
> any binaries? How about HTML? Cant we even &nbsp anymore?
-----------------
Binaries on non-binaries newsgroups screw up the bandwidth for providers
and make them less likely to carry our somewhat marginal groups. Yes,
the few electronics groups are actually somewhat marginal in their 
readership/postership to justify our place (being widely carried) on
Usenet!!! This gets more annoying for providers if these contain huge
binaries. The group set aside for this BECAUSE of this attitude BY
providers is:

news://alt.binaries.schematics.electronics

And we don't care what they put there as long as it keeps the binaries
off of here. HTML referenced binaries do NOT include the whole binary
graphical as a huge bandwidth hit, but only the URL attached as an img
src link in html, which is trivial text. Your own browser gets to decide
whether to download it for viewing or not off another site altogether as
YOU dictate. This is the difference, and yes, contrary to the moronic
Xtian fundie bullshit of some, we have the right to say fuck all we want
here, but NOT to post binaries!! HTML is permitted, though not
appreciated if you're just jerk us around with cutesy fonts.
-Steve
-- 
-Steve Walz  rstevew@armory.com  ftp://ftp.armory.com:/pub/user/rstevew
-Electronics Site!! 1000 Files/50 Dirs!! http://www.armory.com/~rstevew
Europe Naples Italy: http://ftp.unina.it/pub/electronics/ftp.armory.com

Article: 23581
Subject: Re: Maximum Speed on obtainable on FPGAs?
From: "B. Joshua Rosen" <bjrosen@polybus.com>
Date: Sat, 01 Jul 2000 09:53:57 -0400
Links: << >>  << T >>  << A >>
Unless you are willing to hand place everything you should assume that
the worst delay will consist of 70% route and 30% logic. As a practical
matter you should also assume that the bulk of the design will have 4 or
5 levels of logic. Use those number to determine the speed of your main
clock. You can then double that frequency for certain small parts of the
design where you limit the logic to what fits into a CLB, in XC4000 that
would be FGLUT + HLUT + setup + clock to out, in Virtex FGLUT + F5MUX +
F6MUX + setup + clock to out. 

Jimmy wrote:
> 
> Hi Folks,
> 
> Having a particular FPGA in hand (with a specific speed grade), How can
> someone assess the performance of a particular design. In other terms, how
> can you know the maximum obtainable speed for a particular design. The
> question might seem vague but I will illustrate:
> Say you want to do a bit serial convolution on an XC4000 chip. What is the
> best speed you can get. I can see that for a heavily pipeline design, you
> can assume that the maximum delay is the CLB delay (FF or LUT). How about
> the routing? Is it fair to assume that in a good design the routing delay is
> equal to the logic delay and so You can say that the best period time (the
> minimum) you can get is 2*CLB_delay??
> 
> Any input is much appreciated.
> 
> Cheers.

Article: 23582
Subject: Re: Viewlogic schematic from Synplify edif output?
From: Rickman <spamgoeshere4@yahoo.com>
Date: Sat, 01 Jul 2000 10:22:26 -0400
Links: << >>  << T >>  << A >>
That would be useful as a schematic primative. I have always preferred
to think in terms of LUTs. At one time back when Viewlogic was as DOS
program, they supported a way of passing parameters into a lower module.
I had defined a module which was in essense the 4 input LUT complete
with the programmable configuration bit. The parameter defined the bit
pattern and I had a 4 input LUT that would place and simulate. But for
some reason when they converted to Windows, these modules ceased to
function. 

If they don't have a schematic symbol for the simulation primatives, can
you add them to the library? Or are the libraries uneditable?

This is the type of problem that make people want open source tools.
They get tired of being told how to design and what tools to use.



Simon wrote:
> 
> Nope.  The LUTs have attributes attached which correspond
> to the LUT SRAM contents and thus define the LUT logic.
> 
> Rickman wrote in message <395D26F6.32FA2365@yahoo.com>...
> >I am not familiar with Synplicity and the formats it generates in the
> >EDIF output. But I don't think the LUT primatives contain logic. When I
> >have worked with Xilinx at the schematic level the LUT primatives all
> >were just placeholders and you had to have separate gates for the logic.
> >Do they do that in the EDIF files as well? I do know the FPGA Express
> >uses both logic and LUTs. If Synplicity does not use both, how do they
> >indicate the logic that is contained in the LUTs?
> >
> >If the LUTs are only there for mapping, then you likely can remove them
> >for logical simulation. I would bet that a program or script could be
> >written to edit them out. I know this is yet another step and a PITA,
> >but that is the way FPGA design work is.

-- 

Rick Collins

rick.collins@XYarius.com

Ignore the reply address. To email me use the above address with the XY
removed.



Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX

Internet URL http://www.arius.com
Article: 23583
Subject: Re: Free PCI core
From: Mark Aaldering <mma"@"netwiz."net>
Date: Sat, 01 Jul 2000 09:59:22 -0700
Links: << >>  << T >>  << A >>
On Thu, 29 Jun 2000 15:28:46 GMT, Aliens from the 3rd dimension made
bkk411@hotmail.com write:

>
>I didn't know Xilinx gives away their PCI core. Last time I checked
>they wanted $15K + royaltis ...
>Same for Altera - don't remember the price ....

Check again - there have never been any royalties, and a PCI 33/32 for
Spartan is around $5K for unlimited use in Xilinx devices.

Mark Aaldering
Mark.Aaldering"@i"eee."org

Article: 23584
Subject: Re: Maximum Speed on obtainable on FPGAs?
From: Peter Alfke <palfke@earthlink.net>
Date: Sat, 01 Jul 2000 17:02:10 GMT
Links: << >>  << T >>  << A >>
I find these generalizations misleading. "Routing delays more than twice the
logic delays, and 4 or 5 levels of logic between registers" is not a
representative assumption. It is too pessimistic.
But I don't offer an alternative.
There is too much diversity in designs to give one generalized rule. In extreme
cases, it may be as slow as Joshua said. In heavily pipelined DSP applications
it's one level of logic and short interconnects that determine the speed.
How could we otherwise have built a DES encryption/decryption design that runs,
64 bits in parallel, at over 180 MHz ? ( It does, in XCV300E)

We don't want to repeat the mistakes of PREP ( brrr!), but we should not set
expectations too low either.

Peter Alfke, Xilinx Applications
===========================================
"B. Joshua Rosen" wrote:

> Unless you are willing to hand place everything you should assume that
> the worst delay will consist of 70% route and 30% logic. As a practical
> matter you should also assume that the bulk of the design will have 4 or
> 5 levels of logic. Use those number to determine the speed of your main
> clock. You can then double that frequency for certain small parts of the
> design where you limit the logic to what fits into a CLB, in XC4000 that
> would be FGLUT + HLUT + setup + clock to out, in Virtex FGLUT + F5MUX +
> F6MUX + setup + clock to out.
>
> Jimmy wrote:
> >
> > Hi Folks,
> >
> > Having a particular FPGA in hand (with a specific speed grade), How can
> > someone assess the performance of a particular design. In other terms, how
> > can you know the maximum obtainable speed for a particular design. The
> > question might seem vague but I will illustrate:
> > Say you want to do a bit serial convolution on an XC4000 chip. What is the
> > best speed you can get. I can see that for a heavily pipeline design, you
> > can assume that the maximum delay is the CLB delay (FF or LUT). How about
> > the routing? Is it fair to assume that in a good design the routing delay is
> > equal to the logic delay and so You can say that the best period time (the
> > minimum) you can get is 2*CLB_delay??
> >
> > Any input is much appreciated.
> >
> > Cheers.

Article: 23585
Subject: Re: Which notebook is for you?
From: John Larkin <jjlarkin@highlandSNIPTHIStechnology.com>
Date: Sat, 01 Jul 2000 10:38:48 -0700
Links: << >>  << T >>  << A >>
On Fri, 30 Jun 2000 22:42:53 -0700, Branko Badrljica
<brankob@avtomatika.com> wrote:

>
>
>Don wrote:
>
>> In article <395C4EAD.4FD6@armory.com>, rstevew@armory.com says...
>> > Get used to the idea, you can post your binary to any binary group,
>> > from the schematics group to porn groups and nobody cares, but if you
>> > do this on the text-ONLY groups again we'll get your little asshole
>> > turned the fuck off, you dig??
>> > -Steve
>> >
>> >
>> Does that mean we can now say "fuck" with you, steve, but we cant post
>> any binaries? How about HTML? Cant we even &nbsp anymore?
>
>Man gets angry about usenet abuse. What's wrong with that ?
>It feels nice to let some steam out once in a while, even on public
>cyberplace, especially if one expresses majority's opinion...
>
>
>Regards,
>
>
>Branko


True, but rudeness begets rudeness, and more than one ng has been
totally poisoned by a positive feedback loop of anger, obscenity, and
flames. Nubies will always goof up, but maybe they can be steered in
the right direction a little more gently.

John

Article: 23586
Subject: Re: Which notebook is for you?
From: "~Mike Turco" <miketurco@yahoo.com>
Date: Sat, 01 Jul 2000 18:05:53 GMT
Links: << >>  << T >>  << A >>
Fuck. Fuck fuck fuck fuck fuck.

Hmmmm . . . seems a bit off topic. But its nice to get it out of my system.
System? Hmmmm . . . maybe it is on topic. I can fix that. Fucking system.
Fuck fuck fuck fuck fuck.

(No binary attached.)


"Steve" <rstevew@armory.com> wrote in message
news:395DC242.2184@armory.com...
> Don wrote:
> >
> > In article <395C4EAD.4FD6@armory.com>, rstevew@armory.com says...
> > > Get used to the idea, you can post your binary to any binary group,
> > > from the schematics group to porn groups and nobody cares, but if you
> > > do this on the text-ONLY groups again we'll get your little asshole
> > > turned the fuck off, you dig??
> > > -Steve
> > >
> > >
> > Does that mean we can now say "fuck" with you, steve, but we cant post
> > any binaries? How about HTML? Cant we even &nbsp anymore?
> -----------------
> Binaries on non-binaries newsgroups screw up the bandwidth for providers
> and make them less likely to carry our somewhat marginal groups. Yes,
> the few electronics groups are actually somewhat marginal in their
> readership/postership to justify our place (being widely carried) on
> Usenet!!! This gets more annoying for providers if these contain huge
> binaries. The group set aside for this BECAUSE of this attitude BY
> providers is:
>
> news://alt.binaries.schematics.electronics
>
> And we don't care what they put there as long as it keeps the binaries
> off of here. HTML referenced binaries do NOT include the whole binary
> graphical as a huge bandwidth hit, but only the URL attached as an img
> src link in html, which is trivial text. Your own browser gets to decide
> whether to download it for viewing or not off another site altogether as
> YOU dictate. This is the difference, and yes, contrary to the moronic
> Xtian fundie bullshit of some, we have the right to say fuck all we want
> here, but NOT to post binaries!! HTML is permitted, though not
> appreciated if you're just jerk us around with cutesy fonts.
> -Steve
> --
> -Steve Walz  rstevew@armory.com  ftp://ftp.armory.com:/pub/user/rstevew
> -Electronics Site!! 1000 Files/50 Dirs!! http://www.armory.com/~rstevew
> Europe Naples Italy: http://ftp.unina.it/pub/electronics/ftp.armory.com


Article: 23587
Subject: Re: Maximum Speed on obtainable on FPGAs?
From: Rickman <spamgoeshere4@yahoo.com>
Date: Sat, 01 Jul 2000 14:18:16 -0400
Links: << >>  << T >>  << A >>
Exactly what was wrong with PREP? I was tuned out from FPGAs when the
PREP thing died. So I missed all the news as to what was wrong with it.
I did hear that a lot of vendors were tuning the tools and even the
chips to perform well on the benchmark while not improving other
designs. Was that the problem?



Peter Alfke wrote:
> 
> I find these generalizations misleading. "Routing delays more than twice the
> logic delays, and 4 or 5 levels of logic between registers" is not a
> representative assumption. It is too pessimistic.
> But I don't offer an alternative.
> There is too much diversity in designs to give one generalized rule. In extreme
> cases, it may be as slow as Joshua said. In heavily pipelined DSP applications
> it's one level of logic and short interconnects that determine the speed.
> How could we otherwise have built a DES encryption/decryption design that runs,
> 64 bits in parallel, at over 180 MHz ? ( It does, in XCV300E)
> 
> We don't want to repeat the mistakes of PREP ( brrr!), but we should not set
> expectations too low either.
> 
> Peter Alfke, Xilinx Applications


-- 

Rick Collins

rick.collins@XYarius.com

Ignore the reply address. To email me use the above address with the XY
removed.



Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX

Internet URL http://www.arius.com

Article: 23588
Subject: Re: Which notebook is for you?
From: John Larkin <jjlarkin@highlandSNIPTHIStechnology.com>
Date: Sat, 01 Jul 2000 11:33:52 -0700
Links: << >>  << T >>  << A >>
On Sat, 01 Jul 2000 18:05:53 GMT, "~Mike Turco" <miketurco@yahoo.com>
wrote:

>Fuck. Fuck fuck fuck fuck fuck.
>
>Hmmmm . . . seems a bit off topic. But its nice to get it out of my system.
>System? Hmmmm . . . maybe it is on topic. I can fix that. Fucking system.
>Fuck fuck fuck fuck fuck.
>
>(No binary attached.)
>

Hey, Mike, great vocabulary. Where did you learn so many expressive
words?

John

Article: 23589
Subject: Re: PLXMon sources
From: "Joel Kolstad" <Joel.Kolstad@USA.Net>
Date: Sat, 1 Jul 2000 13:30:40 -0700
Links: << >>  << T >>  << A >>
"Dominique SZYMIK" <szymik@nospam.univ-lille1.fr> wrote in message
news:3959B7C8.D7B15412@nospam.univ-lille1.fr...
> Once PLXTech offered to download the
> sources of their PCI debuggers,
> PLXMon and PLXMon95, and phyacc.vxd
> driver.
>
> I would like to see if I can adapt the
> VxD to win98, it only works for win95.

Do you really want to do this?  PLXMon is not exactly the world's
friendliest or most sophisticated program, and although I'm very, very happy
that PLX includes _any_ sort of initial debugging program like PLXMon, you
very rapidly get to the point where you need to start writing your own test
code anyway (either using PLX's API -- which is not particularly fancy, but
does get the job done -- or your own device driver).

Heck, in Windows 95/98 you can still do evil things like write directly to
any memory or port you want to.  You can whip up test programs pretty fast
in such an environment.

---Joel Kolstad



Article: 23590
Subject: How much would a PCI core be worth?
From: "Boogie" <NOSPAMbrian@psn.net>
Date: Sat, 1 Jul 2000 13:38:28 -0700
Links: << >>  << T >>  << A >>
How much would a simple PCI core be worth?  I've been wondering this for a
while.  I realize that free cores are in development, and that the prices
for some commercial cores are around 5k-30k not including support.  Yikes.
What about a cheap core!  I'm talking around/under 100 bucks, more like $25
to $50.  What you would get is a pure vhdl code, (no netlist crapola),
verified, synthesizable PCI core.  The only catch is that there would be no
support!  What do you expect.  It's almost trivial to write a simple PCI 32
bit target, once you've digested the the PCI spec, although I've really only
dealt with embedded PCI applications where there was no configuration cycle.
As for writing a master, that's a bit more difficult but within reach.  So
something like $25 for a simple target and $50 for a master/target.

Maybe there are some legal issues that I'm not aware of that inflate the
prices of commercial cores, or other things.  Maybe the only way around this
is to offer a free core.

Anyway, just a thought.




Article: 23591
Subject: Re: Anyone tried the Virtex dev. board from Avnet?
From: Jiri Gaisler <jgais@ws.estec.esa.nl>
Date: Sun, 02 Jul 2000 00:42:59 +0200
Links: << >>  << T >>  << A >>
Lars Rzymianowicz wrote:
> 
> Hi!
> 
> There is a new Virtex Development System from Avnet Design Services.
> Have a look at:
> http://www.avnetmarshall.com/dynamic/html/html/semi/marketing/xlx-19990526semw.html
> 
> Does anyone have experience with it?
> It currently has a XCV300-BG432 mounted, but the datasheet mentions
> also a XCV800 version. Is the larger one available?

I have tried to order this board from AVNET UK, SE and BE without
success. If you know how to order it, please let me know.

Thanks, Jiri Gaisler - European Space Agency.

Article: 23592
Subject: Re: Maximum Speed on obtainable on FPGAs?
From: murray@pa.dec.com (Hal Murray)
Date: 2 Jul 2000 02:01:20 GMT
Links: << >>  << T >>  << A >>

> I find these generalizations misleading. "Routing delays more than twice the
> logic delays, and 4 or 5 levels of logic between registers" is not a
> representative assumption. It is too pessimistic.

I would have said "far too pessimistic", but that probably reflects
the types of things I work on.


I've been wondering about this area for a long time.  I just noticed
something interesting, at least to me.

I think the key is a difference in design style.  It's top-down vs
bottom-up.

Top-down people write their code in some HDL, pour it into the
tools, and see how fast it runs.

Bottom-up people start by understanding the hardware details, figure
out how fast they can make the inner loop go, and then try to fit
everything else around that.

Both sets of people spend a lot of time fighting tools.  Bottom-up
people know what they want out and have to figure out what to put
into the tools to get that result.  Top-down people know what they
want to put into the tools and have to figure out how to get the
tools to do something good with that.
-- 
These are my opinions, not necessarily my employers.  I hate spam.

Article: 23593
Subject: Re: Viewlogic schematic from Synplify edif output?
From: fliptron@netcom.com (Philip Freidin)
Date: 2 Jul 2000 02:35:58 GMT
Links: << >>  << T >>  << A >>
Simon wrote:
> 
> Nope.  The LUTs have attributes attached which correspond
> to the LUT SRAM contents and thus define the LUT logic.

The latest version of ViewSim, and the latest version of the Virtex
libraries are supposed to be able to simulate ROMs with init=xxxx
attributes attached. This was fixed about 6 months ago. No announcement
was made, so you just needed to trip over the updates.

If you go into the most current Viewlogic Viewdraw Virtex library,
and look at the LUT4 symbol, you will see a default @init="0000"

Push down and you will find a simulation model to match.

There is probably a way to get from where you are to where you want to be,
given the above info. I haven't done it, and I suspect it will take a bit
of screwing around to get it right. For instance, I had a play with this
stuff a few months ago, and to get the init to work, and set the value to
8000, I had to overide the default to @init=8000 and attach another
attribute init=8000 to both get it to simulate and to generate the chip I
wanted. I believe this is a bug in the library definition, but I am
burntout with trying to get Xilinx to care about the quality of this
stuff. At least they eventually added support for Virtex for
Viewdraw/Viewsim users.  (this init stuff also should work with the SRL16
and block RAMS too)

Philip Freidin

Article: 23594
Subject: Re: Viewlogic schematic from Synplify edif output?
From: fliptron@netcom.com (Philip Freidin)
Date: 2 Jul 2000 02:45:04 GMT
Links: << >>  << T >>  << A >>
In article <8jm9qe$ji0$1@slb7.atl.mindspring.net>,
Philip Freidin <fliptron@netcom.com> wrote:
>
>The latest version of ViewSim, and the latest version of the Virtex
>libraries are supposed to be able to simulate ROMs with init=xxxx
>attributes attached. This was fixed about 6 months ago. No announcement
>was made, so you just needed to trip over the updates.
> ... more helpful stuff deleted ...

You might also want to look at http://support.xilinx.com/techdocs/5968.htm

Philip Freidin

Article: 23595
Subject: Re: Viewlogic schematic from Synplify edif output?
From: Rickman <spamgoeshere4@yahoo.com>
Date: Sun, 02 Jul 2000 01:34:38 -0400
Links: << >>  << T >>  << A >>
Thanks a lot. This can save a lot of trouble when you want to closely
control the mapping and placement of a function. The old way of using
gates and a FMAP was just so clunky. I will never understand why Xilinx
always wants to tell its users how they should do design. 

Now if I can just get them to let me enter a single equation for the LUT
instead of having to calculate the hex contents myself. 



Philip Freidin wrote:
> 
> In article <8jm9qe$ji0$1@slb7.atl.mindspring.net>,
> Philip Freidin <fliptron@netcom.com> wrote:
> >
> >The latest version of ViewSim, and the latest version of the Virtex
> >libraries are supposed to be able to simulate ROMs with init=xxxx
> >attributes attached. This was fixed about 6 months ago. No announcement
> >was made, so you just needed to trip over the updates.
> > ... more helpful stuff deleted ...
> 
> You might also want to look at http://support.xilinx.com/techdocs/5968.htm
> 
> Philip Freidin

-- 

Rick Collins

rick.collins@XYarius.com

Ignore the reply address. To email me use the above address with the XY
removed.



Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX

Internet URL http://www.arius.com
Article: 23596
Subject: Re: How much would a PCI core be worth?
From: Tom Burgess <tom.burgess@home.com>
Date: Sun, 02 Jul 2000 06:38:21 GMT
Links: << >>  << T >>  << A >>
The obvious next step is to PAY companies to use your PCI core. It's clear that
you are not going to support much of a business on a few dozen sales at $25,
and there will be so many FREE cores to choose from that the PCI core consuming
masses will be befuddled, so why not invest now in building market share of this
lucrative market? Say, pay users a reverse royalty of $2 per unit sold, but require
their product ads to contain your bold swirly logo, "Boogie inside". You could recoup by
selling T-shirts, web portal thingies, and garden tools. For $25K, customers could
use the core without the silly logo and would also receive a free pizza and beverage
of their choice along with a psychic hotline subscription. When's the IPO? :)

regards, tom

Boogie wrote:
> 
> How much would a simple PCI core be worth?  I've been wondering this for a
> while.  I realize that free cores are in development, and that the prices
> for some commercial cores are around 5k-30k not including support.  Yikes.
> What about a cheap core!  I'm talking around/under 100 bucks, more like $25
> to $50.  What you would get is a pure vhdl code, (no netlist crapola),
> verified, synthesizable PCI core.  The only catch is that there would be no
> support!  What do you expect.  It's almost trivial to write a simple PCI 32
> bit target, once you've digested the the PCI spec, although I've really only
> dealt with embedded PCI applications where there was no configuration cycle.
> As for writing a master, that's a bit more difficult but within reach.  So
> something like $25 for a simple target and $50 for a master/target.
> 
> Maybe there are some legal issues that I'm not aware of that inflate the
> prices of commercial cores, or other things.  Maybe the only way around this
> is to offer a free core.
> 
> Anyway, just a thought.
Article: 23597
Subject: Remedies after the Fathers' Day Massacre
From: Peter Alfke <palfke@earthlink.net>
Date: Sun, 02 Jul 2000 06:47:32 GMT
Links: << >>  << T >>  << A >>
Two weeks ago, some of you posted strong opinions about the
user-unfriendliness of our Applinx CD-ROM.
These were your main objections:

1. "I don't want to see the Hollywood opening"
2. "I refuse to add anything to my pc-installation. Windoze is fragile
enough. I just want to read the data sheets and app notes."
3."Spartan files should not be locked. I want to cut and paste"
4."The CD-ROM should not expire"
5."I hate marketing"

We took a serious look at these complaints and came up with the
following solutions:

1. As I posted already: Just hit ESCAPE

2. As I posted already: Open the CD with Explorer.
Then you can either double-click on the databook.htm file, and open it
with Explorer,
or you double-click on the databook.pdf files and open them with
Acrobat.

3. Never again will we copy-protect a data sheet or app note. Spartan
info on the web is now unprotected, thanks to your comments.

4. The CD-ROM does not "expire". Bad choice of word on our part. You can
use any Applinx CD-ROM until your Pentium turns to dust. After six
months we just remind you that you might be better off getting a new
CD-ROM. Ignore that, if you really feel like it. The same goes for our
software. You will then be without updates and support, but nothing will
evaporate or die or explode.

5. Marketing is a necessary function. You may dislike the style ( as I
do I sometimes), but without marketing, there would be no new products.
Somebody has to coordinate the introduction, promotion, pricing,
production, sales etc. Learn to accept marketing, life without them
would be worse.

Greetings, and keep designing with Virtex and Spartan.  Neat parts!

Peter Alfke, Xilinx Applications




Article: 23598
Subject: Re: How much would a PCI core be worth?
From: "Joel Kolstad" <Joel.Kolstad@USA.Net>
Date: Sun, 2 Jul 2000 01:44:25 -0700
Links: << >>  << T >>  << A >>
"Tom Burgess" <tom.burgess@home.com> wrote in message
news:395EE415.69976A9D@home.com...
> The obvious next step is to PAY companies to use your PCI core.

No, no.  Far simpler to set up a Napster-like "IP exchange" center where
users can sit around and type in the keywords of cores they're after --
"PCI," "USB," "SMPTE," "8255," "Vending Machine," etc. -- and have it pull
them straight off of other users' hard drives without ever having gone
through your own server!  You avoid any nasty legal issues -- at least until
someone like PLX Technologies pulls a Metallica and sues you -- and end up
in the top ten web destinations on the Internet so that your advertising
revenues make you a multi-millionaire overnight!

---Joel Kolstad



Article: 23599
Subject: Re: Viewlogic schematic from Synplify edif output?
From: "Simon" <simonb@tile.demon.co.cuthis.uk>
Date: Sun, 2 Jul 2000 11:47:55 +0100
Links: << >>  << T >>  << A >>
You could add the equation as an attribute, then write a small
program to scan the EDIF and convert the equation to an INIT.
This would still leave the simulation to be dealt with...

Rickman wrote in message <395ED46E.D072C66A@yahoo.com>...
>
>Now if I can just get them to let me enter a single equation for the LUT
>instead of having to calculate the hex contents myself.





Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarApr2017

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search