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Messages from 23650

Article: 23650
Subject: Re: BIST in FPGAs?
From: Rickman <spamgoeshere4@yahoo.com>
Date: Tue, 04 Jul 2000 10:18:29 -0400
Links: << >>  << T >>  << A >>
They test the chips at the factory, don't they? I don't know if Xilinx
will part with their test vectors, but I would bet that you could come
up with some number (hopefully small) of bit files that test the chip
pretty thoroughly. I met someone once that did this for a company that
he worked for. I believe he told me he got some amount of support from
Xilinx and then extended that info to fit his needs. 


Greg Neff wrote:
> 
> In article <395F75F2.1088FCE7@earthlink.net>,
>   palfke@earthlink.net wrote:
> > Looks to me like a strong argument for SRAM-based FPGAs, where such
> issues
> > can be resolved by re-configuration, and the user-design need not be
> > burdened with BIST, because everything can be pre-tested in a separate
> > configuration.
> (snip)
> 
> I'm not sure that this would be valid from a test perspective.  How do
> you know if your test bitstream tests all of the logic and interconnect
> that is used for the mission bitstream?  This is very P&R dependent.
> The purpose of BIST is to test the logic paths that are in use, and I'm
> not convinced that a separate test bitstream could be made to do this.
> Each bitstream will use different CLB inputs and outputs, CLB
> configurations, interconnect switches, etc.
> 
> --
> Greg Neff
> VP Engineering
> *Microsym* Computers Inc.
> greg@guesswhichwordgoeshere.com
> 
> Sent via Deja.com http://www.deja.com/
> Before you buy.

-- 

Rick Collins

rick.collins@XYarius.com

Ignore the reply address. To email me use the above address with the XY
removed.



Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX

Internet URL http://www.arius.com
Article: 23651
Subject: Re: BIST in FPGAs?
From: rk <stellare@nospamplease.erols.com>
Date: Tue, 04 Jul 2000 10:26:13 -0400
Links: << >>  << T >>  << A >>
A few random comments:

Rickman wrote:

> I am not a test expert, but I don't think it is very common to build in scan
> test for the internal parts of a chip design. The internal parts of a chip
> are so reliable, that it is very, very seldom that they ever stop working
> once built correctly.

It depends on the system requirements.  Some systems designs require that
in-circuit you can test that all is well.  This test may be run periodically
on systems that are used infrequently but need high availability when needed
or when performing a mission critical function and periodic testing is called
for.  For example, in some 1960's aerospace computers, for some critical
systems time was taken out of processing to run diagnostics.  In many systems
that I have designed, support for testing was built into the logic so that the
system (logic + everything else) can be verified either in environmental tests
or in the field.

Some system requirements dictate that not only must the systems be testable
but that X% of all faults be diagnosible down to a certain level.  Obviously
this is critical for field repair by technicians.

As for the internal parts of the chip being reliable, that is true, but note
that the number of elements on a chip are increasing, well, rapidly.  See the
discussion on 500 million transistors on a chip!  Without redundancy, the
reliability model is series reliability and the probabilities must be
multiplied giving a reliability equation of the form p^n.  p must be very
close to 1 for good chip reliability.  Of course, chip reliability is pretty
good with the failure rate in FITS still being quite low.  Memories typically
include redundancy.  Some of this is used at the factory to increase yield;
others are done in the field either automagically or during maintenance.  A
nice chip to look at is some models of the IBM LUNA DRAM, where they have ECC
for real-time correction of data that is read back; they also have software
writable memories for replacement of failed rows and columns [iirc - I do
remember it's there but not positive both rows and columns can be switched]
during maintenance.

From the 1994 Quicklogic Databook, p. 2-16:

     All pASIC 1 devices have a built-in serial scan path linking the
     logic cell register functions.  This is provided to improve factory
     test coverage and to permit testing by the user with automatically
     generated test vectors following programming....

=====================================

> With that said there are two reasons that you (I will speek for myself
> as "you") might want to do scan based test. One is that you want to test
> that the part is connected correctly and there is no damage to the IOs which
> is much more common than internal problems.

I also note that one semiconductor engineer that I saw at a conference
remarked that about 1/2 of all failures are on the I/O's, the other half is
internal, based on experience.

=====================================

> The other is that you may have a design that is hard to do factory test by
> observing the IO pins. Sometimes it takes a very long test to be sure that
> you have toggled every node in the chip and observed all possible outcomes.
> It is also possible that there is NO test (without scan based testing) that
> can tell you if a given node has an error. (Makes you wonder if the error
> matters!)

Remember he's using Actel Act 2 technology and can directly observe the output
of all logic elements on the scope.  There is often no need to propagate
signals to the I/O pins to show that a node is not S-A-1 or S-A-0.  IDDQ
testing [often overlooked in my opinion] is often useful for the detection of
bridging faults and has been used for this technology in the past.  While the
static ICC of the devices is not zero, it is constant for a device [and
typically very constant from device to device] permitting IDDQ techniques to
be used, although a bit differently than in ASICs. This technology also does
not have tri-state busses and internal termination resistors, making this
technique more viable.  A variation called differential IDDQ testing is used
for the diagnosis of bridging faults.  An example of a bridging fault in Act 2
technology can be an unintentionally programmed antifuse resistively
connecting two logic signals whose tracks cross with an unprogrammed antifuse
between them.

=====================================

> So if you are doing scan test for the second reason, then go for it. But if
> you don't have problems generating test vectors to adequately test your
> chip, then scan based test of internals is likely overkill.

It depends on how good the tools are.  I used to generate vectors for Act 2
technology and it was a b*tch.  Took a very long time.  And the results
weren't that good in terms of test coverage.  While computers are faster now
and have larger memories, I don't know how practical it is.  Another
consideration is how well is the design geared for test.  If you plan for it
up front you can do quite a bit better.  Generating them after the fact (I had
to do this for a number of designs sent in for evaluation) can often result in
poor test coverage; that is, less then 20% and often less than 10%.  An
expensive tool and process that didn't help all that much.  BIST was much
faster, better, and cheaper in many cases.

===================================

> But if you are designing for space or some military applications, then
> the initial assumption is incorrect and you may have to detect internal
> failures in the field.

Agreed.  Also, don't forget fields such as medical applications, as many
diagnostic and treatment machines are electronically controlled.  There was a
case a number of years ago with a software fault and an x-ray machine that had
bad consequences.  Another field is commercial aviation where fly-by-wire
systems are now being used.

Have a good fourth!
----------------------------------------------------------------------
rk                               But Mother Nature, unlike Congress
stellar engineering, ltd.        and the press and even the space
stellare@erols.com.NOSPAM        workers, can't be bluffed.
Hi-Rel Digital Systems Design    -- James Oberg, 2000


Article: 23652
Subject: Programming Virtex with the MultiLINX cable
From: SteVe <Ste@xxx.it>
Date: Tue, 04 Jul 2000 16:37:45 +0200
Links: << >>  << T >>  << A >>
I was thinking about programming my Virtex FPGA with the MultiLINX cable
by Xilinx. In particular I was considering the use of the slave serial
mode. On the page
http://toolbox.xilinx.com/docsan/2_1i/data/common/hug/fig17.htm
I found a scheme for the connection. There is just one question: which
is the value for VCC? 2.5V? 3.3V? Or is it the same?

Thanks,
SteVe


Article: 23653
Subject: Re: How to augment the output of a Xilinx lfsr in verilog??
From: est0@lehigh.edu
Date: Tue, 04 Jul 2000 14:52:07 GMT
Links: << >>  << T >>  << A >>
Actually, what I need to do is quite simple. For reasons that I won't
go into here, we need a sequence with an even number of bits. I need
4096 rather than 4095 bits. So, what we set up to do in our
preliminary simulation work is to take the sequence that we get from
our Gold code generator, which exclusive OR's two length 12 maximal
LSFR's to get 1 of many 4095 bit long Gold codes. (The exact sequence
we get is determined by the sequence that we load into one of the two
maximal length sequence generators. Then, no matter what the specific
4095 bit pattern is, we want to add a 4096th bit, which we want to be
a 0. (We could have chosen a 1, but we chose a 0 and based our
reception algorithm on that, so I want to produce that sequence. In
other words, if we had a 4 stage generator, and the 15 output bits
were 000100110011110, we now want the output to be 00010011000111100,
and we want this to repeat until we tell the system to use a different
code.

It may be that I can't do what I want to do without adding some
additional gates and stopping the PN generator for one bit, but I am
hoping that I can do it without having to do that. 

TIA,
Ed

On Tue, 04 Jul 2000 04:25:25 GMT, Peter Alfke <palfke@earthlink.net>
wrote:

>If, for whatever strange reason, you want to lengthen the sequence by its
>one missing count, you have no alternative but to have a wide AND gate that
>detects the state where all but the rightmost bit are zeros, and then,
>during this 2-bit event, inverts (XORs) the feedback, so that it includes
>the all-zero state.
>(I prefer to exclude the all-ones state, since Xilinx FPGAs naturally reset
>to zero, but this may be irrelevant nowadays).
>So, the cost is a wide parallel gate, which you, of course, can emulate
>with a sequential state machine, if you prefer.
>But again: why all this?
>
>Peter Alfke
>==========================================================
>Hal Murray wrote:
>
>> > almost does what I want. However, it, like all lsfr's, puts out 2^n-1
>> > states before it repeats. I need to augment or stall that output so
>> > that I add a 0 to the end of every sequence, so as to create sequences
>> > with a length of 2^n. I see all sorts of mention of how easy that is
>> > to do, but I can't figure it out, and nowhere is it explained. Does
>> > anyone know how to do what I want to do?
>>
>> What are you really trying to do?
>>
>> Note that the LFSR type circuits generate 1 bit at a time, not
>> a sequence of n bit wide words.
>>
>> It's pretty hard to distinguish the output of an LFSR from
>> the corresponding system that does include the all-0s state.
>> (It's just a single 0 bit in the output sequence.)
>>
>> If you are worried about the missing 0 unbalancing your
>> statistics, the simple fix is probably to use a bigger LFSR.
>>
>> If you want the all-zero word output, your first problem is
>> to get a clean sequence of words.  I think the output of an
>> LFSR is good if you step it N cycles to get an N bit word.
>> If you can't wait that long, you can use independent LFSRs
>> for each bit.  (You need to make sure they don't run in
>> lock step, perhaps by making them different lengths.)
>>
>> Using the bottom N bits of an N+k bit LFSR clocked N bits
>> between samples will give you (2^k)-1 all 0 words compared
>> to (2^k) samples of all other values.
>>
>> If it helps, you can turn things upside down with an inverter
>> in the right place and make the all 1s state the missing one.
>> --
>> These are my opinions, not necessarily my employers.  I hate spam.

Article: 23654
Subject: Altera and Xilinx processor core announcements
From: "Jan Gray" <jsgray@acm.org>
Date: Tue, 04 Jul 2000 15:40:48 GMT
Links: << >>  << T >>  << A >>
Altera announced "three families-the NiosT soft core embedded processor, the
ARMr-based hard core embedded processor, and the MIPS-basedr hard core
embedded processor" [1]. Also, Altera announced that Motorola and Altera
"have entered discussions toward a licensing agreement to embed Motorola
processor core technology into Altera programmable logic devices" [2].

Xilinx announced "The Xilinx and ARC Cores Alliance for Configurable
Processor Cores on Xilinx FPGAs" [3].

In my Circuit Cellar article series [4-6] I wrote "...this series
demonstrates that a streamlined and thrifty CPU design, optimized for FPGAs,
can achieve a cost-effective integrated computer system, even for low-volume
products that can't justify an ASIC run."

If you will pardon the cliche, these announcements from Altera and Xilinx
have legitimized FPGA CPU soft cores and SoCs.  You will know that FPGA
processor cores are mainstream when we start to see FPGA CPU articles and
performance/size/power tables in Microprocessor Report. :-)

For starters, here's an apples-to-oranges size comparison.  While these
processor cores have quite different features, capabilities, and
performance, all are pipelined RISC embedded processor cores that can run
integer C code.  (A logic cell is a vague unit of FPGA area comprising
approximately one 4-LUT and one FF).

* Nios (16-bit data): 1100 APEX LEs => approx 1100 logic cells
* Nios (32-bit data): 1700 APEX LEs => approx 1700 logic cells
* ARC ("basecase"): 1517 Virtex slices => approx 3000 logic cells
* our xr16 (16-bit data): 130 XC4000x CLBs: (258 4-LUTs, 52 3-LUTs, 165 FFs,
112 TBUFs) => approx 310-420 logic cells
* our xr32 (32-bit data, work in progress) => approx 470-600 logic cells

Jan Gray
Gray Research LLC
www.fpgacpu.org

Links.
[1] http://www.altera.com/html/products/excalibur.html
[2] http://www.altera.com/html/new/pressrel/pr_ex_motorola.html
[3] http://www.xilinx.com/products/logicore/alliance/arc/arcspot.htm
[4] http://www.circuitcellar.com/pastissues/articles/gray116/gray116.pdf
[5] http://www.circuitcellar.com/pastissues/articles/gray117/gray117.pdf
[6] http://www.circuitcellar.com/pastissues/articles/gray118/gray118.pdf



Article: 23655
Subject: Re: BIST in FPGAs?
From: Phil Hays <spampostmaster@sprynet.com>
Date: Tue, 04 Jul 2000 08:42:45 -0700
Links: << >>  << T >>  << A >>
Greg Neff wrote:

> I'm not sure that this would be valid from a test perspective.  How do
> you know if your test bitstream tests all of the logic and interconnect
> that is used for the mission bitstream?  This is very P&R dependent.

Test coverage is almost never 100%.  Yet I think a fairly high number could be
produced by the one of following procedures:

Place and route your design, with a outside ring of CLBs prohibited.  Make sure
that no routing (other than to IOBs) goes into this outer ring.  Cut the core of
the design into a hard macro, and instantiate it into the test design.  Rerun
place and route, which should use the outside ring of CLBs for the test design
and leave the hard macro in place, including routing internal to the core
design.

Alternative:

If incremental place and route works, which is a new feature of 3.1i, then place
and route the core, then use the core as a starting point to generate the
functional design and the self test design.

I have NOT tried this.  I have a brand new copy of Xilinx 3.1i sitting in the
CDROM tray that I'd like to try with something not production, and if I have
interesting results on this I'll give a report.


-- 
Phil Hays
Article: 23656
Subject: Re: BIST in FPGAs?
From: Greg Neff <gregneff@my-deja.com>
Date: Tue, 04 Jul 2000 16:17:39 GMT
Links: << >>  << T >>  << A >>
In article <396205F5.2873C89D@sprynet.com>,
  Phil Hays <spampostmaster@sprynet.com> wrote:
> Greg Neff wrote:
>
> > I'm not sure that this would be valid from a test perspective.  How
do
> > you know if your test bitstream tests all of the logic and
interconnect
> > that is used for the mission bitstream?  This is very P&R dependent.
>
> Test coverage is almost never 100%.

OK, I need to remember to stop using words like "all".  Certainly, test
coverage is not likely to achieve 100% coverage.

> Yet I think a fairly high number could be
> produced by the one of following procedures:
>
> Place and route your design, with a outside ring of CLBs prohibited.
Make sure
> that no routing (other than to IOBs) goes into this outer ring.  Cut
the core of
> the design into a hard macro, and instantiate it into the test
design.  Rerun
> place and route, which should use the outside ring of CLBs for the
test design
> and leave the hard macro in place, including routing internal to the
core
> design.
>
> Alternative:
>
> If incremental place and route works, which is a new feature of 3.1i,
then place
> and route the core, then use the core as a starting point to generate
the
> functional design and the self test design.
>
> I have NOT tried this.  I have a brand new copy of Xilinx 3.1i
sitting in the
> CDROM tray that I'd like to try with something not production, and if
I have
> interesting results on this I'll give a report.
>
> --
> Phil Hays
>

OK, these sound pretty good to me.  I think I would be inclined to work
it from the other end.  I would start with a design that included all
of the BIST logic, run a P&R, remove the BIST logic, and then run a
guided P&R.  This should leave all of the mission logic and routing in
place, and you wouldn't have to worry about what resources to reserve
for the BIST logic.  As with your suggestions, the only thing that
should change is the routing from the IOBs to the logic. The removal of
the BIST logic would only be necessary if it introduces an unacceptable
performance impact.

--
Greg Neff
VP Engineering
*Microsym* Computers Inc.
greg@guesswhichwordgoeshere.com


Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 23657
Subject: silicon
From: ramesh_z@my-deja.com
Date: Tue, 04 Jul 2000 16:23:48 GMT
Links: << >>  << T >>  << A >>













Hi friends,

          I have implemented some arithmetic units,
like fast adders, multipliers, dividers using logic
synthesis tools(xc4000) and I have obtained good results(small delays)
If I implement these in silicon,
will the delay increase or decrease or remain the same.

THANK YOU,
ramesh
mail : ramesh.z@mailcity.com









Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 23658
Subject: Re: why???
From: krw@attglobal.net (Keith R. Williams)
Date: 4 Jul 2000 17:45:22 GMT
Links: << >>  << T >>  << A >>
On Sun, 2 Jul 2000 12:59:59, erika_uk@my-deja.com wrote:

> hey all
> 
> i am just wondering why you are all worrying about that since  all the
> informations are available on xilinx web site.
> 
> why is the need for data book + cd room+...they are all online ?

My "Letterman List" of top-ten reasons:

10).  Sometimes I like to get away from the computer and just 
read. There are some places I don't want a computer or where it 
would be unusable.

9).  Sometimes I work at home sucking through a 50Kbps straw.

8).  Sometimes I work from a hotel room sucking through a 28.8K 
straw (or worse).

7).  On occaision I work at a vendor's site and have no straw.

6).  Even at work the network is often so overloaded that it 
makes me wish for my 50kbps straw.

5).  When I'm in the lab, I don't have ready access to all my 
bookmarks and such.

4).  When I'm in the lab trying to figure out why something isn't
working that simply *must* work, it's nice to have my dog-ear'd 
note-scribbled hardcopy of the databook so I can read the poorly 
written prose and look at my notes, just once more.  "...AHA!  
*That* what they mean!"  

3).  I really don't want to print it the databook myself.  My HP 
ink-jet printer wouldn't like it. I do this, but it's not as nice
as a bound copy.

2).  At $1300/part, I'd like the $20 book too, thank you. I'm not
buying many parts, which is likely why I haven't seen my 2000 
copy of the Xilinx data book - or they are *really* slow doleing 
them out.  

1).  Sometimes I like to lean back in my chair with my feet up 
and a technical book in my hands.  It makes it look like I'm 
studying real hard. ;-)

Sure, the web is a fantastic resource.  CD's are great.  However,
they haven't come close to replacing books and the "paperless 
office" is more of a dream today than it was twenty years ago.

----
  Keith R. Williams

Article: 23659
Subject: Re: Programming Virtex with the MultiLINX cable
From: "Alun" <alun101@DELETEtesco.net>
Date: Tue, 4 Jul 2000 21:13:34 +0100
Links: << >>  << T >>  << A >>
> I found a scheme for the connection. There is just one question: which
> is the value for VCC? 2.5V? 3.3V? Or is it the same?

My reading of it was that it copes with either and draws more current if
it's 2.5V. I guess it's got a switcher inside.

Alun
Camdigital


Article: 23660
Subject: Re: Problem with uploading in XC95288 using ISP with HW-JTAG-PC
From: "Simon Bilodeau" <sbilodo@videotron.ca>
Date: Tue, 4 Jul 2000 17:41:24 -0400
Links: << >>  << T >>  << A >>
Is it normal to have 200 ohms resistance between TCLK and TMS and between
TCLK and TDI pins directly on the chip?

I saw that those pins influence each other because the programmer's pins
can't get enough current on IC's pins (the programmer works well alone) and
I didn't see anything special that could make a short on the board.

anybody knows why

thanks in advance

Simon




"G. Hobson Frater" <hobson.frater@xilinx.com> wrote in message
news:395D4D14.B5958F6C@xilinx.com...
> Simon,
>
> If you haven't already, you might want to check the Xilinx Answers
database at
> http://support.xilinx.com.  In the Answers Search Field try typing
something
> like " bit position '0' ".  Answer record #2881 may help.
>
> -Hobson
> Xilinx Applications
>
> Simon Bilodeau wrote:
>
> > Hi,
> >
> > i<m new in ISP with CPLD and i have an error uploading a version in my
CPLD.
> > Every connection seems do be ok but i always get that error...
> >
> > Any idea?
> >
> > Log file :
> >
> > Loading Boundary-Scan Description Language (BSDL) file
> > 'C:/Fndtn/xc9500/data/xc95288.bsd'.....completed successfully.
> > Checking boundary-scan chain integrity...ERROR:JTag - Boundary-scan
chain
> > test failed at bit position '0' on instance 'projet24(Device1)'.
> >  Check that the cable, system and device JTAG TAP connections are
correct,
> >  that the target system power supply is set to the correct level,
> >   that the system grounds are connected and that the parts are properly
> > decoupled.
> > ERROR:JTag - Boundary scan chain has been improperly specified.  Please
> > check your configuration and re-enter the boundary-scan chain
information.
> > Boundary-scan chain validated unsuccessfully.
> > ERROR:JTag - : The boundary-scan chain has not been declared correctly.
> >  Verify the syntax and correctness of the device BSDL files, correct the
> > files,
> >  reset the cable and retry this command.
>


Article: 23661
Subject: Re: MPEG audio questions...
From: "gary" <dont.spam@me.net>
Date: Tue, 4 Jul 2000 22:44:40 +0100
Links: << >>  << T >>  << A >>
Hi Lars,

I understand Analog Devices do an off-the-shelf decoder, but I was hoping to
integrate the MPEG bit with the other bits I need in an FPGA.

Thanks for your reply.

Gary.





Lars <Lotzen@intersci.com> wrote in message news:ee6cf4c.0@WebX.sUN8CHnE...
> Hi Gary,
>
> I don't know the answer for the first question, but I'm pretty sure a MPEG
algorithm implementation is not for free.
>
> What do you think about a ready MPEGI Layer II,III (known as mp2,mp3) Chip
for about $50?
>
> BYE
> Lars


Article: 23662
Subject: Re: Serial Number embedded in PROM.
From: korthner@my-deja.com
Date: Tue, 04 Jul 2000 23:46:07 GMT
Links: << >>  << T >>  << A >>
Thanks for the advice, Rick.

> That would probably work fine, but how would you read it? AFAIK, some
of
> the pins used for reading the PROM during configuration are not usable
> as IOs during normal operation (CCLK, DONE-). I guess you could attach
> extra pins to the signals which are not accessable by your FPGA design
> during configuration.

That's what I was thinking of doing.  I know that I can't drive CCLK
after startup, and one of the others (Forget which), so I figured I'd
connect them to an extra FPGA pin(s).

And figured I'd put the serial number in the last spot in the PROM, and
at SerialNumberReading time, I would just shift everything into an n-
bit shift register until the PROM was empty, and whatever was left in
the shift register, that's my serial number.

> I am looking at taking a different tact. I have been thinking about
> using a small (very small) micro to boot my board. I may have it do
some
> other things like monitor power supply voltages and replace a board
> control register, but the main fuction is to boot the initial FPGA
load.

I'm missing something, I think.  I've seen other people mention using a
micro to boot a FPGA. . . . . Why?  If you're not using anything fancy
like reprogrammability or readback, isn't it easier/cheaper to just
plug a PROM in a socket, and let the FPGA suck up the bitstream itself?

> My
> current board has a Dallas one wire part on it to provide a serial
> number and some non-volatile storage for board configuration data.

That's the other thing we're looking at.  I assume, then, that you've
got the Dallas part (2401?) up and running, no problem?  Can you by any
chance let me know how big the onewire-control logic inside the FPGA
is?  I have a *very* little amount of space left (20% of a Xilinx
Spartan '05), so I figure I don't have what it takes to do the timing
requirements.  If you could send me a copy of the VHDL code, that'd be
wonderful.  But if you can't, I understand completely.

Thanks!
-Kent



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Before you buy.
Article: 23663
Subject: Re: Programming Virtex with the MultiLINX cable
From: korthner@my-deja.com
Date: Wed, 05 Jul 2000 00:00:00 GMT
Links: << >>  << T >>  << A >>
Hey, Steve.

Sorry, but this isn't going to answer your question, just adds a
question of my own.

I don't really see why a person would want to program an FPGA with a
cable, unless it was only for debugging.  If it's debugging, then it
makes sense, you don't waste a PROM or the time to burn it, and so on.

But other than debugging, what's the purpose?

Thanks.
-Kent


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Before you buy.
Article: 23664
Subject: Re: Virtex DLL deskew of board clock with a clock/2
From: korthner@my-deja.com
Date: Wed, 05 Jul 2000 00:55:04 GMT
Links: << >>  << T >>  << A >>
Hi, Utku.

I may have an idea for you.  If it's a really bad one, then I hope
somebody else will shoot me down before you waste a lot of time trying
it.

First, I have a question, though. If your input clock is a frequency
'f', and your output clock to all your chips are at frequency 'f', why
would you have a restriction that the feedback clock be at frequency
'f/2'?

Now to my solution:

It requires the use of 2 DLLs however, not only one.  Maybe there's a
better way of doing it with 1 DLL and a Clock divider, but I haven't
figured it out.

Also, I'm not actually sure that this will work with Xilinx, running a
feedback signal off the chip, when the source comes from on-chip.
Also, since I'm using 2 DLLs, I've doubled the clock skew.  I think.

If the diagram below doesn't make any sense at all, try pasting it inte
Notepad or anything with fixed-width fonts.

                      .-------------. Off-chip feedback.
 --------------------|--------------|--
  .-----------.      |              |
 |  _______   |fb    |   _______    |
 | |  DLL  |  |      |  |  DLL  |   |
 ~>|fb     |  |       ~>|fb     |   |
   |       |  |         |       |   |
 f |       |  |         |       |   |
-->|in   1f|--'   .---->|     1f|---'
   |       |     |f/2   |       |
   |   1/2f|-----'      |     2f|-------> Out to chips at original freq.
    -------              -------

-kent



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Before you buy.
Article: 23665
Subject: Re: Serial Number embedded in PROM.
From: Peter Alfke <peter@xilinx.com>
Date: Tue, 04 Jul 2000 19:28:29 -0700
Links: << >>  << T >>  << A >>


Rickman wrote:

> That would probably work fine, but how would you read it? AFAIK, some of
> the pins used for reading the PROM during configuration are not usable
> as IOs during normal operation (CCLK, DONE-). I guess you could attach
> extra pins to the signals which are not accessable by your FPGA design
> during configuration.
>

I am pretty sure that you could directly connect an FPGA output to the CCLK
pin, and thus kick the SPROM after it has done its duty of configuring the
FPGA. I have never tried that, but it seems natural ( Remember: all other
outputs are 3-state during and before configuration, and CCLK has a
resistive pull-up after the end of configuration...).

Peter Alfke

Article: 23666
Subject: Help I/O pin
From: "Andrew Buckin" <ipm_grp@iptelecom.net.ua>
Date: Wed, 5 Jul 2000 07:13:26 +0300
Links: << >>  << T >>  << A >>
After programmer EPM7064STC100-10
All pin are in a condition an output.

Global pin in GND
Programmer ByteBlaster.



Article: 23667
Subject: Re: BIST in FPGAs?
From: Rickman <spamgoeshere4@yahoo.com>
Date: Wed, 05 Jul 2000 00:33:45 -0400
Links: << >>  << T >>  << A >>
I disagree that you can't get 100% coverage for test. I am sure that
Xilinx tests every chip they make 100%. Since the chip is fully
programmable, I doubt that they needed to design in special test
circuitry or modes. Certainly this may take more than a single bit file.
But I am sure that you can test every transistor, every wire and every
connection in a Xilinx FPGA if you need to do that. 

As I said in my other post, I once met an engineer who was designing bit
files for Xilinx chips to do 100% test in military systems. They would
do a complete test of the hardware every time they powered up. I think
this was in the XC3000 and XC4000 parts. 


Greg Neff wrote:
> 
> In article <396205F5.2873C89D@sprynet.com>,
>   Phil Hays <spampostmaster@sprynet.com> wrote:
> > Greg Neff wrote:
> >
> > > I'm not sure that this would be valid from a test perspective.  How
> do
> > > you know if your test bitstream tests all of the logic and
> interconnect
> > > that is used for the mission bitstream?  This is very P&R dependent.
> >
> > Test coverage is almost never 100%.
> 
> OK, I need to remember to stop using words like "all".  Certainly, test
> coverage is not likely to achieve 100% coverage.
> 
> > Yet I think a fairly high number could be
> > produced by the one of following procedures:
> >
> > Place and route your design, with a outside ring of CLBs prohibited.
> Make sure
> > that no routing (other than to IOBs) goes into this outer ring.  Cut
> the core of
> > the design into a hard macro, and instantiate it into the test
> design.  Rerun
> > place and route, which should use the outside ring of CLBs for the
> test design
> > and leave the hard macro in place, including routing internal to the
> core
> > design.
> >
> > Alternative:
> >
> > If incremental place and route works, which is a new feature of 3.1i,
> then place
> > and route the core, then use the core as a starting point to generate
> the
> > functional design and the self test design.
> >
> > I have NOT tried this.  I have a brand new copy of Xilinx 3.1i
> sitting in the
> > CDROM tray that I'd like to try with something not production, and if
> I have
> > interesting results on this I'll give a report.
> >
> > --
> > Phil Hays
> >
> 
> OK, these sound pretty good to me.  I think I would be inclined to work
> it from the other end.  I would start with a design that included all
> of the BIST logic, run a P&R, remove the BIST logic, and then run a
> guided P&R.  This should leave all of the mission logic and routing in
> place, and you wouldn't have to worry about what resources to reserve
> for the BIST logic.  As with your suggestions, the only thing that
> should change is the routing from the IOBs to the logic. The removal of
> the BIST logic would only be necessary if it introduces an unacceptable
> performance impact.
> 
> --
> Greg Neff
> VP Engineering
> *Microsym* Computers Inc.
> greg@guesswhichwordgoeshere.com
> 
> Sent via Deja.com http://www.deja.com/
> Before you buy.

-- 

Rick Collins

rick.collins@XYarius.com

Ignore the reply address. To email me use the above address with the XY
removed.



Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

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4 King Ave
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Internet URL http://www.arius.com
Article: 23668
Subject: Re: How to augment the output of a Xilinx lfsr in verilog??
From: Rickman <spamgoeshere4@yahoo.com>
Date: Wed, 05 Jul 2000 01:28:44 -0400
Links: << >>  << T >>  << A >>
I don't think you need to stop the LFSR to do this, but I am pretty sure
you will need to add a N bit wide decoder as others have suggested. If
you use a sequence that never loads all FFs with a zero as a starting
point, you can modify the circuit to include an extra zero by using the
all zero FF state. 

Perhaps the easiest way to do that is to detect the state of all zeros
ignoring the last bit (the one shifting out). Then feed this signal as
another input to the XOR gate driving the input to the shift register.
The only two state that will activate this signal are the "normal" state
of all zeros with the last bit a one, and the "abnormal" or new state of
all zeros. When the "normal" state comes up in the FFs, the detect
circuit will invert the output of the XOR gate which should have been a
one. Now the FFs will be loaded with all zeros and the next input will
be a one which will generate the "normal" state of a one and the rest
zeros which would have followed next in the original circuit. 

I won't attempt ascii art of this since it is very difficult and should
not be attempted by the faint of heart (me!)

Actually, I think what I just wrote was stated previously by Peter
Alfke, and a bit more succinctly. Is there a reason that you didn't like
this approach?



est0@lehigh.edu wrote:
> 
> Actually, what I need to do is quite simple. For reasons that I won't
> go into here, we need a sequence with an even number of bits. I need
> 4096 rather than 4095 bits. So, what we set up to do in our
> preliminary simulation work is to take the sequence that we get from
> our Gold code generator, which exclusive OR's two length 12 maximal
> LSFR's to get 1 of many 4095 bit long Gold codes. (The exact sequence
> we get is determined by the sequence that we load into one of the two
> maximal length sequence generators. Then, no matter what the specific
> 4095 bit pattern is, we want to add a 4096th bit, which we want to be
> a 0. (We could have chosen a 1, but we chose a 0 and based our
> reception algorithm on that, so I want to produce that sequence. In
> other words, if we had a 4 stage generator, and the 15 output bits
> were 000100110011110, we now want the output to be 00010011000111100,
> and we want this to repeat until we tell the system to use a different
> code.
> 
> It may be that I can't do what I want to do without adding some
> additional gates and stopping the PN generator for one bit, but I am
> hoping that I can do it without having to do that.
> 
> TIA,
> Ed
> 
> On Tue, 04 Jul 2000 04:25:25 GMT, Peter Alfke <palfke@earthlink.net>
> wrote:
> 
> >If, for whatever strange reason, you want to lengthen the sequence by its
> >one missing count, you have no alternative but to have a wide AND gate that
> >detects the state where all but the rightmost bit are zeros, and then,
> >during this 2-bit event, inverts (XORs) the feedback, so that it includes
> >the all-zero state.
> >(I prefer to exclude the all-ones state, since Xilinx FPGAs naturally reset
> >to zero, but this may be irrelevant nowadays).
> >So, the cost is a wide parallel gate, which you, of course, can emulate
> >with a sequential state machine, if you prefer.
> >But again: why all this?
> >
> >Peter Alfke
> >==========================================================
> >Hal Murray wrote:
> >
> >> > almost does what I want. However, it, like all lsfr's, puts out 2^n-1
> >> > states before it repeats. I need to augment or stall that output so
> >> > that I add a 0 to the end of every sequence, so as to create sequences
> >> > with a length of 2^n. I see all sorts of mention of how easy that is
> >> > to do, but I can't figure it out, and nowhere is it explained. Does
> >> > anyone know how to do what I want to do?
> >>
> >> What are you really trying to do?
> >>
> >> Note that the LFSR type circuits generate 1 bit at a time, not
> >> a sequence of n bit wide words.
> >>
> >> It's pretty hard to distinguish the output of an LFSR from
> >> the corresponding system that does include the all-0s state.
> >> (It's just a single 0 bit in the output sequence.)
> >>
> >> If you are worried about the missing 0 unbalancing your
> >> statistics, the simple fix is probably to use a bigger LFSR.
> >>
> >> If you want the all-zero word output, your first problem is
> >> to get a clean sequence of words.  I think the output of an
> >> LFSR is good if you step it N cycles to get an N bit word.
> >> If you can't wait that long, you can use independent LFSRs
> >> for each bit.  (You need to make sure they don't run in
> >> lock step, perhaps by making them different lengths.)
> >>
> >> Using the bottom N bits of an N+k bit LFSR clocked N bits
> >> between samples will give you (2^k)-1 all 0 words compared
> >> to (2^k) samples of all other values.
> >>
> >> If it helps, you can turn things upside down with an inverter
> >> in the right place and make the all 1s state the missing one.
> >> --
> >> These are my opinions, not necessarily my employers.  I hate spam.

-- 

Rick Collins

rick.collins@XYarius.com

Ignore the reply address. To email me use the above address with the XY
removed.



Arius - A Signal Processing Solutions Company
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Internet URL http://www.arius.com
Article: 23669
Subject: Spartan II PCI32 suggestions ?
From: Muzaffer Kal <muzaffer@kal.st>
Date: 05 Jul 2000 01:39:12 EDT
Links: << >>  << T >>  << A >>
hi,
I am doing a Spartan II PCI32 board with a single chip attached to the
FPGA on the top (bottom being the PCI connector). I am looking for any
gotchas, suggestions etc. I think I'll use the 100K Spartan II. I'd
like to design the board so that both serial rom and bitblaster
programming are possible. I am assuming this is doable. Also will the
PC system need a reset whenever I reprogram the board ? I am hoping
that if I don't change the PCI footprint of the card, I won't have to
reset.

thanks,

Muzaffer

Article: 23670
Subject: Re: Serial Number embedded in PROM.
From: Rickman <spamgoeshere4@yahoo.com>
Date: Wed, 05 Jul 2000 01:45:26 -0400
Links: << >>  << T >>  << A >>
korthner@my-deja.com wrote:
> 
> Thanks for the advice, Rick.
> That's what I was thinking of doing.  I know that I can't drive CCLK
> after startup, and one of the others (Forget which), so I figured I'd
> connect them to an extra FPGA pin(s).

PROG-, DONE, CCLK are the ones that can't be used for anything else.
Also DOUT I think. INIT- and DIN are user IOs after config. So you would
need to provide a user IO connections to DONE/CE- and CCLK/CLK. 

 
> And figured I'd put the serial number in the last spot in the PROM, and
> at SerialNumberReading time, I would just shift everything into an n-
> bit shift register until the PROM was empty, and whatever was left in
> the shift register, that's my serial number.

Yes, that would work fine. You will need a counter matched to the size
of your PROM to stop it. 

 
> I'm missing something, I think.  I've seen other people mention using a
> micro to boot a FPGA. . . . . Why?  If you're not using anything fancy
> like reprogrammability or readback, isn't it easier/cheaper to just
> plug a PROM in a socket, and let the FPGA suck up the bitstream itself?

There is no reason to use a micro unless you can use it for some other
tasks as well. In my case I was looking for a way to replace the one
wire serial number part (in which I would also use the EEPROM/PROM) and
realized that it could replace a couple of other parts. Now I am looking
for the perfect uC that will replace all the misc logic chips on my
board. If I could find one that had three analog comparators as well as
the Flash, EEPROM, UART and a dozen or more IOs I would have it made.
But it is hard to find everything in one part. 

 
> That's the other thing we're looking at.  I assume, then, that you've
> got the Dallas part (2401?) up and running, no problem?  Can you by any
> chance let me know how big the onewire-control logic inside the FPGA
> is?  I have a *very* little amount of space left (20% of a Xilinx
> Spartan '05), so I figure I don't have what it takes to do the timing
> requirements.  If you could send me a copy of the VHDL code, that'd be
> wonderful.  But if you can't, I understand completely.

The Dallas part is very easy to use. The documentation is not real clear
though. But you can read between the lines and figure out what is going
on. We used the on board DSP to do all this so I don't know how large
the circuit would be in an FPGA. 

You just need a few timers and a finite state machine (FSM). The one
wire chip communicates in a polled mode where every bit sent in either
direction is started by the FPGA with a one uS low pulse (all drivers
are OC and there is a single 4.7K pullup). In that 1 uS the one wire
chip will pick up the ball and drive it to a zero if it is sending you a
zero or leave it float if it is sending you a one. A zero is held for
another 15 uS max. If you are sending a zero or one, you do the same (1
uS v. 15 uS). There is also a reset pulse sent to the one wire chip
which is a zero for over 60 uS. 

This is how you send/receive bits. There is then a protocol on top of
that to read the data in the one wire chip and to program it. If you
just need to read the serial number and nothing else, I think there is a
command to read it out cold. The other commands require you to "address"
the chip with the SN. 

This is all a bit hazy as it has been awhile since I looked at it and I
did not do the coding. But this is the jist of it. Certainly the bit
level is not hard to do if you have a clock handy (and who doesn't?).
The higher level protocol will take a bit of FSM design. 

But if you are short on free hours, I could do the VHDL for you. It
might even save you a little time/money since I have a leg up on the one
wire parts and I can even test the VHDL on my board. 

Maybe someone else has done this in VHDL?


-- 

Rick Collins

rick.collins@XYarius.com

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removed.



Arius - A Signal Processing Solutions Company
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Article: 23671
Subject: Re: Serial Number embedded in PROM.
From: Rickman <spamgoeshere4@yahoo.com>
Date: Wed, 05 Jul 2000 01:48:12 -0400
Links: << >>  << T >>  << A >>
I think you will also need to connect a user IO to the DONE signal. This
one will have gone high at the end of config and reset the PROM. So it
will have to be pulled low again and all the bits read out until the end
of the PROM. 


Peter Alfke wrote:
> 
> Rickman wrote:
> 
> > That would probably work fine, but how would you read it? AFAIK, some of
> > the pins used for reading the PROM during configuration are not usable
> > as IOs during normal operation (CCLK, DONE-). I guess you could attach
> > extra pins to the signals which are not accessable by your FPGA design
> > during configuration.
> >
> 
> I am pretty sure that you could directly connect an FPGA output to the CCLK
> pin, and thus kick the SPROM after it has done its duty of configuring the
> FPGA. I have never tried that, but it seems natural ( Remember: all other
> outputs are 3-state during and before configuration, and CCLK has a
> resistive pull-up after the end of configuration...).
> 
> Peter Alfke

-- 

Rick Collins

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Ignore the reply address. To email me use the above address with the XY
removed.



Arius - A Signal Processing Solutions Company
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Internet URL http://www.arius.com
Article: 23672
Subject: Re: Serial Number embedded in PROM.
From: Rickman <spamgoeshere4@yahoo.com>
Date: Wed, 05 Jul 2000 01:52:11 -0400
Links: << >>  << T >>  << A >>
One small advantage to using a micro in place of the PROM is that after
config, you need to use two additional user IO pins to talk to the PROM.
But using the micro would let you use the INIT- and DIN pins as your IO
for reading the serial number. You only need data and clock. You could
even do that with one pin if you used a protocol like the one wire
chips. 


korthner@my-deja.com wrote:
> I'm missing something, I think.  I've seen other people mention using a
> micro to boot a FPGA. . . . . Why?  If you're not using anything fancy
> like reprogrammability or readback, isn't it easier/cheaper to just
> plug a PROM in a socket, and let the FPGA suck up the bitstream itself?


-- 

Rick Collins

rick.collins@XYarius.com

Ignore the reply address. To email me use the above address with the XY
removed.



Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

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301-682-7666 FAX

Internet URL http://www.arius.com
Reply-To: "Alasdair MacLean" <nojunk@gecm.com>
Article: 23673
Subject: Re: MPEG audio questions...
From: Bernhard Josef Rieder <bernhard@ratte.tuwien.ac.at>
Date: Wed, 05 Jul 2000 07:00:33 +0100
Links: << >>  << T >>  << A >>
In article "gary" <dont.spam@me.net> wrote:

> (1) How complex is the decoder, how much logic would I need?

have a look at http://www.mpg123.de/ for the C source of a software
decoder. It seems difficult ......
 

> (2) Do you have to pay to use MPEG in your own codecs?

I think you only have to pay if you use the algorithm published by
frauenhofer institute*. If you are not living in the US or in Germany
it is likely to be legally anyway :)

* It seems to be almot impossible NOT to use it


Bernhard

Article: 23674
Subject: Re: BIST in FPGAs?
From: "Alasdair MacLean" <nojunk@gecm.com>
Date: Wed, 5 Jul 2000 08:53:14 +0100
Links: << >>  << T >>  << A >>
Bill Lenihan <lenihan3we@earthlink.net> wrote in message
news:395F7311.4C0D6F44@earthlink.net...
> We have an FPGA design that will be targeting an Actel 1200 series FPGA
> (antifuse, one-time-programmable). It will be coded in Verilog,
> simulated w/ Model Tech's ModelSim PE simulator (PC Win 95/NT),
> synthesized in Synopsys FPGA Compiler II (Unix), and P&R done w/ Actel's
> backend tools (Unix).
>
> The systems people are making serious noise about requiring this design
> to have Built-In Self-Test (yes, we know about the gate & speed penalty
> we pay for this, and that it may be bigger for FPGAs than it is for
> ASICs because of the granularity difference), meaning:
>
> (1) the mission-logic registers must be turned into scan-able registers
> (2:1 mux in front of D-input) and assembled into N chains, where N is
> typically 2 <= N <= 64.
>
> plus the following (w/ non-scan-able registers) would need to be
> stitched into the design:
>
> (2.1) LFSR-based pattern generator
> (2.2) LFSR-based signature analyzer / response compressor
> (2.3) control logic (wired back w/ hooks to the "CPU bus" or whatever
> other communications port reports BIST pass/fail status) to do M scan
> sequences.
>
> Has anyone done these things for an FPGA? If so, what tools?
>
> I know that the EDA industry has tools that routinely do step (1) for
> ASICs, but does anyone do this for FPGAs? Can any EDA tool take an EDIF
> netlist produced by an FPGA synthesis tool, insert scan registers & wire
> chains [adding ports for the scan in(s), scan out(s), scan enable
> control(s)], and have the new modified netlist accepted by the FPGA P&R
> tools?
>
> Can any EDA tool automate steps (2.1-2.3), at all, let alone for FPGAs?
>
> We are interested in finding out how much, if any, of these tasks are
> automatically done by EDA tools for FPGAs. Naturally we can build all
> this testability explicitly into the HDL source code if we have to, but
> we want to avoid that.
>
> Even if we can only do step (1) but not steps (2.1-2.3), we may still be
> able to do some scan-based test, perhaps with an external
> microcontroller performing steps (2.1-2.3).
>
> --
> ==============================
> William Lenihan
> lenihan3weNO@SPAMearthlink.net
> ==============================
>
>

Bill,
Actel published an application note on this very subject in their 1995
databook. The article was titiled "Efficient BIST Techniques for Field
Programmable Gate Arrays" and was written by a guy called Warren Savage of
Tandem Computers. If you can't get hold of a copy from Actel let me know and
I'll scan it and email it to you.

        -- Alasdair

Alasdair MacLean,
Principal Development Engineer,
BAE Systems,
Sensor Systems Division,
Silverknowes,
Edinburgh.





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