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Messages from 23975

Article: 23975
Subject: tutorial on configurable system-on-chip design is available
From: Dave Vanden Bout <devb@xess.com>
Date: Wed, 19 Jul 2000 09:52:32 -0400
Links: << >>  << T >>  << A >>
XESS Corp. is releasing the fourth section of its "myCSoC" tutorial for free downloading at http://www.xess.com/myCSoC-CDROM.html.  We will release a new section each week.

Each section describes a design example for the Triscend configurable system-on-chip device (CSoC).  The Triscend TE505 CSoC integrates an 8051 microcontroller core with a programmable logic array to create a chip whose software and hardware are both reprogrammable.  The tutorial examples show how the Triscend FastChip development software is used to configure the TE505's programmable logic into peripheral functions that cooperate with the microcontroller core.

--
|| Dr. Dave Van den Bout   XESS Corp.               (919) 387-0076 ||
|| devb@xess.com           2608 Sweetgum Dr.        (800) 549-9377 ||
|| http://www.xess.com     Apex, NC 27502 USA   FAX:(919) 387-1302 ||
Article: 23976
Subject: Re: FPGA Conferences
From: vikramp <vikramp@xilinx.com>
Date: Wed, 19 Jul 2000 07:26:14 -0700
Links: << >>  << T >>  << A >>


Almost all  the FPGA / PLD related conferences are listed at
http://www.ee.ubc.ca/~stevew/conf.html

Vikram Pasham
Xilinx Applications

EKC wrote:

>     Does anyone know whether or not there are any PLD-related conferences
> scheduled to take place in the US before mid-September? If so, which ones?
>
> Thanks,
>
> EKC

Article: 23977
Subject: Re: I found it for you 6334
From: cjfocf@mnet.com
Date: 19 Jul 2000 14:44:41 GMT
Links: << >>  << T >>  << A >>
Is this it Johanna ?  http://forward.to/research



"Johanna svenson" <J.Svenson@surnet.se> wrote in message

news:398F7447.95599EA7@surnet.se...



>   Hey there, I use to know a cool site but I cant 

>   remember the adress any more. Do you still have

>   it Nadine ?

Article: 23978
Subject: Fundation serial & Alliance serial
From: zdai@uoguelph.ca (Zhibin Dai)
Date: 19 Jul 2000 15:22:34 GMT
Links: << >>  << T >>  << A >>
Hi,

Does anybody know the big difference between fundation serial s/w and 
Alliance serial s/w?

I have to choose either using Workview Office plus Alliance tools or 
using Fundation serial. But I don't know which option is better.

Any help would be appreciated.


Zhibin

Article: 23979
Subject: Summary: Re: Silicon Valley Housing Nightmare?
From: husby@fnal.gov (Don Husby)
Date: Wed, 19 Jul 2000 15:41:20 GMT
Links: << >>  << T >>  << A >>
Thanks to all who responded to this.  In addition to the responses
posted here, I got about 10 via email.  The consensus (~80%) is that
housing cost is a major problem but there is some tradeoff of longer
commute time for better housing.  A few people pointed out that
with good floorplanning, you can optimize your commute to go against
the rush hour traffic.

  Suggested alternatives were: the East coast, North Bay, Hawaii, and
Zimbabwe.  



--
Don Husby <husby@fnal.gov>             http://www-ese.fnal.gov/people/husby
Fermi National Accelerator Lab                          Phone: 630-840-3668
Batavia, IL 60510                                         Fax: 630-840-5406
Article: 23980
Subject: FPGAs in AC Magnetic Field
From: Dick Maio <maio@csciences.com>
Date: Wed, 19 Jul 2000 11:44:29 -0400
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.
--------------66976936B1D065C355FF79D5
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

Does anyone know if FPGAs (e.g.., Xilinx) will be damaged (or cause
their program to be disrupted) when subjected to an AC magnetic field
(~50 to 60 Hz)?  This field is a de-gaussing (demagnetizing) field in
the order of several Gauss (several times the earth's field of ~ 550
mG).  Thanks for any information

--
Dick Maio
Chesapeake Sciences Corporation
1127B Benfield Blvd., Millersville, MD 21108-2540
TEL: 410-923-1300 x3090 FAX: 410-923-2669
E-MAIL: maio@csciences.com


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Content-Transfer-Encoding: 7bit
Content-Description: Card for Dick Maio
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begin:vcard 
n:Maio;Dick Maio
x-mozilla-html:FALSE
adr:;;;;;;
version:2.1
email;internet:maio@csciences.com
x-mozilla-cpt:;-10992
fn:Dick Maio
end:vcard

--------------66976936B1D065C355FF79D5--

Article: 23981
Subject: Re: FPGAs in AC Magnetic Field
From: Greg Neff <gregneff@my-deja.com>
Date: Wed, 19 Jul 2000 16:11:58 GMT
Links: << >>  << T >>  << A >>
In article <3975CCDD.C62D76FE@csciences.com>,
  Dick Maio <maio@csciences.com> wrote:
>
> Does anyone know if FPGAs (e.g.., Xilinx) will be damaged (or cause
> their program to be disrupted) when subjected to an AC magnetic field
> (~50 to 60 Hz)?  This field is a de-gaussing (demagnetizing) field in
> the order of several Gauss (several times the earth's field of ~ 550
> mG).  Thanks for any information
>
(snip)

We have designed Xilinx FPGAs (XC5200 and Spartan XL) into 36KW high
energy switching power supplies.  I don't know the magnitude of the H
fields from the nearby switching inductors, but some of the system
engineers were worried that our digital controller wouldn't work
because of the magnetic fields.  The controllers have been working fine
for a few years now, and we have not had any reports of system upsets
during operation.

--
Greg Neff
VP Engineering
*Microsym* Computers Inc.
greg@guesswhichwordgoeshere.com


Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 23982
Subject: Re: search free pcb programmer FPGA or CPLD
From: Leon Heller <leon_heller@hotmail.com>
Date: Wed, 19 Jul 2000 16:20:57 GMT
Links: << >>  << T >>  << A >>
In article <8kuut4$k2k$1@nnrp1.deja.com>,
  Leon Heller <leon_heller@hotmail.com> wrote:
> In article <3961A99F.CFD63176@olfac.univ-lyon1.fr>,
>   Bernard Bertrand <bertrand@olfac.univ-lyon1.fr> wrote:
> > Hello,
> >
> > I start working in VHDL and
> > i purchase a free PCB programmer for FPGA or CPLD chip
> > (Altera, xillinx, Cypress...)
> >
> > Thank you for you answer
> > bertrand@olfac.univ-lyon1.fr
>
> I've designed my own PCB for a chinese copy of the Altera ByteBlaster,
> and had a couple made. You are welcome to the Gerber and Excellon
files
> if you want to get your own made.

Further to the above, they are on my web site.

Leon
--
Leon Heller, G1HSM
Tel: (Mobile) 079 9098 1221 (Work) +44 1327 357824
Email: leon_heller@hotmail.com
Web: http://www.geocities.com/SiliconValley/Code/1835


Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 23983
Subject: Re: Fundation serial & Alliance serial
From: rickman <spamgoeshere4@yahoo.com>
Date: Wed, 19 Jul 2000 12:37:57 -0400
Links: << >>  << T >>  << A >>
I don't know what you mean by "serial", but the Foundation software
includes Aldec schematic capture software and if you buy the synthesis
version, FPGA Express. Neither of these tools is the "premier" tool for
FPGA design according to many designers. 

Many prefer Viewlogic for schematic. I have used both and like Viewlogic
a little better than Aldec. The busses in Aldec are a real PITA. Also,
the files that Viewlogic saves are text and so can be version controlled
a little more efficiently, easily. But both will do the job. 

The support is also an issue. Xilinx provides the entire Foundation
package and so directly supports it. The Viewlogic package is not
directly supported by Xilinx which can sometimes cause difficulty in
getting answers to questions. 

The HDL synthesis is another issue. FPGA Express is clearly not as good
as some of the other tools available. But it is much cheaper in the
Foundation package. So you get what you pay for (sometimes). 



Zhibin Dai wrote:
> 
> Hi,
> 
> Does anybody know the big difference between fundation serial s/w and
> Alliance serial s/w?
> 
> I have to choose either using Workview Office plus Alliance tools or
> using Fundation serial. But I don't know which option is better.
> 
> Any help would be appreciated.
> 
> Zhibin

-- 

Rick Collins

rick.collins@XYarius.com

Ignore the reply address. To email me use the above address with the XY
removed.



Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX

Internet URL http://www.arius.com
Article: 23984
Subject: Re: Summary: Re: Silicon Valley Housing Nightmare?
From: "Andy Peters" <apeters.Nospam@nospam.noao.edu.nospam>
Date: Wed, 19 Jul 2000 10:03:10 -0700
Links: << >>  << T >>  << A >>
Don Husby wrote in message <8l4i70$e5$1@info3.fnal.gov>...
>Thanks to all who responded to this.  In addition to the responses
>posted here, I got about 10 via email.  The consensus (~80%) is that
>housing cost is a major problem but there is some tradeoff of longer
>commute time for better housing.  A few people pointed out that
>with good floorplanning, you can optimize your commute to go against
>the rush hour traffic.
>
>  Suggested alternatives were: the East coast, North Bay, Hawaii, and
>Zimbabwe.

I would recommend Tucson, but then again, I'm from New Jersey.  And the
typical silicon valley shack cost three times what I paid for a 2000 sq ft
home with cactus.


-- a
-----------------------------------------
Andy Peters
Sr Electrical Engineer
National Optical Astronomy Observatories
950 N Cherry Ave
Tucson, AZ 85719
apeters (at) noao \dot\ edu

"A sufficiently advanced technology is indistinguishable from magic"
     --Arthur C. Clarke



Article: 23985
Subject: Erasing PLD's
From: Miket2000@postmaster.co.uk (Mike Trowers)
Date: Wed, 19 Jul 2000 18:13:14 GMT
Links: << >>  << T >>  << A >>
Hi all,

I've posted this before but no-one answered so here goes again... 

What pin's would I need to erase locked devices?

I have a few devices of the above with the JTAG port disabled, I made
an error in my programmer, and now I need to erase them. I have been
told that I'd need a third party programmer to do this, but surely I
only need to design a board for myself. Has anyone ever done this, or
have any links that I could find usefull, I've done a bit of surfing
around but found nothing as of yet.

Thanks

Mike.

PS. I hope the no replies aren't anything personal... (Mister Paranoia
jumps on my shoulder)
Article: 23986
Subject: Re: Erasing PLD's
From: Miket2000@postmaster.co.uk (Mike Trowers)
Date: Wed, 19 Jul 2000 18:15:32 GMT
Links: << >>  << T >>  << A >>
Oh forgot the devices are atf1508as devices.

Thanks again I hope...

Mike

On Wed, 19 Jul 2000 18:13:14 GMT, Miket2000@postmaster.co.uk (Mike
Trowers) wrote:

>Hi all,
>
>I've posted this before but no-one answered so here goes again... 
>
>What pin's would I need to erase locked devices?
>
>I have a few devices of the above with the JTAG port disabled, I made
>an error in my programmer, and now I need to erase them. I have been
>told that I'd need a third party programmer to do this, but surely I
>only need to design a board for myself. Has anyone ever done this, or
>have any links that I could find usefull, I've done a bit of surfing
>around but found nothing as of yet.
>
>Thanks
>
>Mike.
>
>PS. I hope the no replies aren't anything personal... (Mister Paranoia
>jumps on my shoulder)

Article: 23987
Subject: Re: Dual Port RAM
From: paul@physics.indiana.edu (Paul Smith)
Date: 19 Jul 2000 18:48:16 GMT
Links: << >>  << T >>  << A >>
Ah, finally an answer to my original question.  Thanks, Ian!

Paul


In article <3975A3FD.84DD392A@lucent.com>,
	"Ian J. Smith" <ianjs@lucent.com> writes:
> We've had great success with Xilinx DP RAMs here. The tools are rather
>good too.  Altera still have some catching up to do.
Article: 23988
Subject: Re: FPGAs in AC Magnetic Field
From: Austin Lesea <austin.lesea@xilinx.com>
Date: Wed, 19 Jul 2000 12:21:24 -0700
Links: << >>  << T >>  << A >>
Dick,

The longest 'wires' in the silicon can be ~20 mm.

The voltages on this wire are in the 1-2 volt range, so a disturb voltage
would be ~100 mV.  So, your problem is one of:  if I have a wire 20 mm
long, what magentic field induces 100 mV on the wire at distance X.

Any physics students out there to solve Gauss' equations to see what the
induced electric voltage is from a 3 Gauss 60 Hz Field with distance from
a 20 mm wire at the best orientation?

Austin

Dick Maio wrote:

> Does anyone know if FPGAs (e.g.., Xilinx) will be damaged (or cause
> their program to be disrupted) when subjected to an AC magnetic field
> (~50 to 60 Hz)?  This field is a de-gaussing (demagnetizing) field in
> the order of several Gauss (several times the earth's field of ~ 550
> mG).  Thanks for any information
>
> --
> Dick Maio
> Chesapeake Sciences Corporation
> 1127B Benfield Blvd., Millersville, MD 21108-2540
> TEL: 410-923-1300 x3090 FAX: 410-923-2669
> E-MAIL: maio@csciences.com

Article: 23989
Subject: Re: FPGAs in AC Magnetic Field
From: "Alun" <alun101@DELETEtesco.net>
Date: Wed, 19 Jul 2000 20:36:43 +0100
Links: << >>  << T >>  << A >>

Dick Maio <maio@csciences.com> wrote in message
news:3975CCDD.C62D76FE@csciences.com...
> Does anyone know if FPGAs (e.g.., Xilinx) will be damaged (or cause
> their program to be disrupted) when subjected to an AC magnetic field
> (~50 to 60 Hz)?  This field is a de-gaussing (demagnetizing) field in
> the order of several Gauss (several times the earth's field of ~ 550
> mG).  Thanks for any information

No. My old phyisics book says:

induced emf = mag field*area/dt
1 Weber = 10000 Gauss
mag field = 10 Gauss = 1/1000 Weber (say)
area = maximum possible loop = (2cm) squared (say)
dt = 1/100 s (approx.)

emf    =  (1/1000)Weber * (0.02m * 0.02m) / 0.01s
        = 40uV

That's not going to hurt anyone.

Alun
Camdigital


Article: 23990
Subject: synthesizer memory useage
From: Jerry English <jenglish@planetc.com>
Date: Wed, 19 Jul 2000 16:45:06 -0400
Links: << >>  << T >>  << A >>
Does anybody know if there is a significant difference between the
memory used
to synthesize a design written in verilog between FPGA Express and
Leonardo for
Altera devices? If you do would you please publish the info?

Thanks
Jerry English

Article: 23991
Subject: Re: Erasing PLD's
From: Miket2000@postmaster.co.uk (Mike Trowers)
Date: Wed, 19 Jul 2000 21:15:28 GMT
Links: << >>  << T >>  << A >>
I think I may have the answer, applying 11v to the TAP pins may
re-activate the jtag port.

Does anyone know if this is correct or not?

Mike

On Wed, 19 Jul 2000 18:13:14 GMT, Miket2000@postmaster.co.uk (Mike
Trowers) wrote:

>Hi all,
>
>I've posted this before but no-one answered so here goes again... 
>
>What pin's would I need to erase locked devices?
>
>I have a few devices of the above with the JTAG port disabled, I made
>an error in my programmer, and now I need to erase them. I have been
>told that I'd need a third party programmer to do this, but surely I
>only need to design a board for myself. Has anyone ever done this, or
>have any links that I could find usefull, I've done a bit of surfing
>around but found nothing as of yet.
>
>Thanks
>
>Mike.
>
>PS. I hope the no replies aren't anything personal... (Mister Paranoia
>jumps on my shoulder)

Article: 23992
Subject: Re: Xilinx Logic Cell counts and carry chains
From: "Steve Casselman" <sc@vcc.com>
Date: Wed, 19 Jul 2000 16:22:19 -0700
Links: << >>  << T >>  << A >>
You should ask "what company's marketing department should I be working
for?"  How many "gates" this translates into is another story but the F5 and
F6 muxes makes the Virtex CLB very powerful in terms of 4 input LUTs.

Steve Casselman, President
Virtual Computer Corporation


"rickman" <spamgoeshere4@yahoo.com> wrote in message
news:396C01FE.F9DAC670@yahoo.com...
> And what company's marketing department do you work for?  ;)
>
>
> Steve Casselman wrote:
> >
> > There are four 4 LUTs and some other stuff per CLB.
> > Really though you can do any function of 6 inputs and it is really a 6
LUT.
> > If you just used 4 LUTs to do any function of 6 inputs you would need
more
> > than four 4 LUTs. So 4.5 4 LUTs per CLB is a conservative  in my
opinion.
> >
> > Steve Casselman
>



Article: 23993
Subject: New Xilinx Student Edition
From: pratipm@yahoo.com (Pratip Mukherjee)
Date: Thu, 20 Jul 2000 00:07:57 GMT
Links: << >>  << T >>  << A >>
Does any body know when will the new version of Xilinx Student Edition with 
Foundation 2.x  be out? Since coming to know that there will be a new version 
shortly, I am holding on from buying the new version for about two months now. 
The wait is killing me.

Pratip Mukherjee
Article: 23994
Subject: Re: Xilinx Logic Cell counts and carry chains
From: John Larkin <jjlarkin@highlandSNIPTHIStechnology.com>
Date: Wed, 19 Jul 2000 18:11:55 -0700
Links: << >>  << T >>  << A >>
On Tue, 23 May 2000 12:28:52 -0400, Rickman <spamgoeshere4@yahoo.com>
wrote:

>First let me say that I am not trying to pick on Xilinx by asking so
>many questions about their devices and practices. But I am looking at
>switching to their parts for my next design and want to discuss some of
>the things I don't understand. 
>
>With that said, can anyone tell me how Xilinx comes up with their "Logic
>Cell" counts? In the XC4000 line of parts, they seem to have 2.375 Logic
>Cells per CLB. I can understand this since they have the two 4 input
>LUTs and a 3 input LUT which they must be counting as .375 Logic Cells. 
>
>But in the Spartan II line they get 4.5 Logic Cells per CLB. But if I
>understand the architechture correctly, there is no extra 3 input LUT in
>these devices. Although they have extra logic to combine the outputs of
>the four LUTs in a CLB, this logic can not be used independantly as can
>the 3 input LUT in the XC4000 series. So the maximum number of logic
>outputs you can have is determined by the number of LUTs you have, not
>the number of "Logic Cells". 
>
>So how can they count this as .5 Logic Cells per CLB? Is Logic Cell
>count the same as gate count and should be ignored?
>
>I guess this is not really a significant issue, but it does make their
>documentation a bit harder to interpret since I have to calculate the
>LUT count myself for every device I want to consider. 
>
>On a more significant note, I can't say that I understand the carry
>chain description in the Spartan II datasheet. I can't seem to cut and
>paste from the document (odd, I can do that with most other PDF
>files...) but the text says, "The Spartan-II CLB supports two separate
>carry chains, one per Slice. The height of the carry chains is two bits
>per CLB." The Virtex carry chain is described the same way so that sheds
>no additional light on the matter.
>
>Is this saying that the two slices are separate and only one carry chain
>can be used at a time? Or are the two cascadable to produce a four bit
>slice of a counter/adder? I checked the timing data and there is no
>indication of a fast connect from Cout to Cin on the same CLB or to
>adjacent CLBs. Has this gone away with the Virtex/Spartan II parts?

I think maybe they're including the I/O cells in the count. The
numbers work out about right.

John

Article: 23995
Subject: Re: Xilinx Logic Cell counts and carry chains
From: rickman <spamgoeshere4@yahoo.com>
Date: Wed, 19 Jul 2000 22:19:44 -0400
Links: << >>  << T >>  << A >>
I was just kidding about that. I understand that Xilinx is trying to
show that there is more in the CLB than just 4 input LUTs. But it is
common in many FPGAs to have a little more than the basic element.
Lucent FPGAs are the same way. 

My point was that I already understand the issues of how to use the
CLBs, I am just trying to get clear information on the actual LUT counts
in the various sized FPGAs and the way Xilinx counts them makes me do
extra work. If they would just publish the actuall counts of LUTs
instead of the marketing number, I could just refer to their data sheets
instead of having to keep a spread sheet with this information from the
various manufacturers. 

Gate counts are the most worthless numbers I know of. It is alot like
the MHz rating of processors. I have *NO* idea of how to compare a
PowerPC processor at 600 MHz to a Pentium at 600 MHz. The one thing I am
sure of is that they are not the same! So I am also sure that a 50 K
gate Xilinx part is nothing like a 50 K gate Lucent part. But if I am
not using block RAM, I do know that I can get the same design to fit in
two parts that have the same number of LUTs (or at least close). 


Steve Casselman wrote:
> 
> You should ask "what company's marketing department should I be working
> for?"  How many "gates" this translates into is another story but the F5 and
> F6 muxes makes the Virtex CLB very powerful in terms of 4 input LUTs.
> 
> Steve Casselman, President
> Virtual Computer Corporation
> 
> "rickman" <spamgoeshere4@yahoo.com> wrote in message
> news:396C01FE.F9DAC670@yahoo.com...
> > And what company's marketing department do you work for?  ;)
> >
> >
> > Steve Casselman wrote:
> > >
> > > There are four 4 LUTs and some other stuff per CLB.
> > > Really though you can do any function of 6 inputs and it is really a 6
> LUT.
> > > If you just used 4 LUTs to do any function of 6 inputs you would need
> more
> > > than four 4 LUTs. So 4.5 4 LUTs per CLB is a conservative  in my
> opinion.
> > >
> > > Steve Casselman
> >

-- 

Rick Collins

rick.collins@XYarius.com

Ignore the reply address. To email me use the above address with the XY
removed.



Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX

Internet URL http://www.arius.com
Article: 23996
Subject: Q: PAL22V10 JEDEC file-toVHDL translators?
From: no@spam.net (Tom Vrankar)
Date: Thu, 20 Jul 2000 03:30:38 GMT
Links: << >>  << T >>  << A >>
Does any JEDEC to VHDL converter exist to allow me to quickly migrate old 
circuit card designs based on rafts of 22V10s in DIPs to a single large FPGA? 
Either freeware or from a FPGA vendor? I've researched it enough to know I 
could do it, but figured it was so obvious someone else must've already done 
it, though I don't see it mentioned in any FAQs I've found.

Thanks.

						twv@
-- 
                         ---------------------------------
                                               Tom Vrankar
                                            twv at ici.net
                                 http://home.ici.net/~twv/
                                         Rhode Island, USA

Article: 23997
Subject: Re: Q: PAL22V10 JEDEC file-toVHDL translators?
From: rickman <spamgoeshere4@yahoo.com>
Date: Thu, 20 Jul 2000 00:33:26 -0400
Links: << >>  << T >>  << A >>
I take it the original source design is not available?


Tom Vrankar wrote:
> 
> Does any JEDEC to VHDL converter exist to allow me to quickly migrate old
> circuit card designs based on rafts of 22V10s in DIPs to a single large FPGA?
> Either freeware or from a FPGA vendor? I've researched it enough to know I
> could do it, but figured it was so obvious someone else must've already done
> it, though I don't see it mentioned in any FAQs I've found.
> 
> Thanks.
> 
>                                                 twv@
> --
>                          ---------------------------------
>                                                Tom Vrankar
>                                             twv at ici.net
>                                  http://home.ici.net/~twv/
>                                          Rhode Island, USA

-- 

Rick Collins

rick.collins@XYarius.com

Ignore the reply address. To email me use the above address with the XY
removed.



Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX

Internet URL http://www.arius.com
Article: 23998
Subject: Re: Warning! -- SONY SUBSTANDARD SERVICE
From: Bill Lenihan <lenihan3we@NOSPAMearthlink.net>
Date: Thu, 20 Jul 2000 07:22:28 GMT
Links: << >>  << T >>  << A >>
I had lots of problems w/ a USB-based Sony CD-RW, too. Added Sony to my shit
list, at least for computers / computer-peripherals.

An_American_Consumer@jhxcojqm.net wrote:

> Anyone considering the purchase of a Sony peripheral for their computer
> might want to give it some further thought. There clearly is not a
> reciprocal relationship between what they sell and what they service.
> -
> I purchased a CD-RW drive back in April that just recently went bad
> (won't read). When I called Sony service, I was told that I could not
> get a replacement and that I had to ship it across the country to be
> "repaired" (and we all know what that means...) - with a three (3) week
> turnaround. Assuming that they keep their 3-week commitment, with
> shipping both ways, I'd be without the use of the unit for at least
> five weeks!!!
> -
> I hardly think that's reasonable or fair.
> -
> Compare this to HP, who under the same circumstances would simply ship
> you out a replacement unit and issue a call-tag for the old one.
> -
> Sony is a behemoth in the marketplace and as such, they have an
> obligation to scale their service facilities to meet demand. To not do
> so is an indication of their lack of commitment to customer satisfaction
> and an unwillingness to stand behind their products.
> -
> Buyer be ware!
> -
> -
> -
> -
> -
> -
> -
> -
> -
>
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>
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>
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>
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>
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>
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>
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>
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>
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> eyya nag hlo nsp nyo tasd erdy oreg eorz mfsee?

--
==============================
William Lenihan
lenihan3weNO@SPAMearthlink.net
==============================


Article: 23999
Subject: DIY ByteBlaster equivalent
From: Leon Heller <leon_heller@hotmail.com>
Date: Thu, 20 Jul 2000 07:23:31 GMT
Links: << >>  << T >>  << A >>
I've put the files (schematic, Gerber and drill files) for a DIY
equivalent of the Altera ByteBlaster on my web site. It can be made for
*very* much less than Altera charges for their device.

Leon
--
Leon Heller, G1HSM
Tel: (Mobile) 079 9098 1221 (Work) +44 1327 357824
Email: leon_heller@hotmail.com
Web: http://www.geocities.com/SiliconValley/Code/1835


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