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Messages from 24450

Article: 24450
Subject: Virtex I/O going off-board.
From: Bill Lenihan <lenihan3weNOSPAM@earthlink.net>
Date: Wed, 09 Aug 2000 06:54:48 GMT
Links: << >>  << T >>  << A >>

Historically, most PWB designs in our company have an FPGA plus I/O
buffers (single-ended to differential or vice-versa, i.e., like
26LS31/32/33) for signals going off-board. This was done to

(a) isolate & protect the FPGA if shorts develop on the backplane,
(b) handle common-mode signals between boards, and
(c) the differential signals keep noise from corupting the signal at
its' destination

Recently, some newer designs are proposed that will go off-board
directly from the Virtex I/O pins. My questions:

[1] on the virtex-E data sheet, why is there a minimum specification on
LVDS common-mode voltage? (Can't it = 0v?)

[2] on the virtex-E data sheet, why is there no specification on LVPECL
common-mode voltage?

[3] what kind of short-circuit protection is there on the Virtex &
Virtex-E I/O cells? (if we get shorts on our backplane, will the Virtex
& Virtex-E survive? ..... it's not so much the cost of replacing virtex
FPGAs that worries me, but the lifetime & reliability of the PWB, whose
pad patterns aren't going to last long if we have to replace a 600-pin
Fine-pitch BGA package too often)

[4] some designers plan to take a single-ended signal inside the FPGA
core, taking it out on Pin A as LVTTL, taking an inverted version out on
pin B as LVTTL, and using the quasi-differential LVTTL pair A/B to drive
a differential line receiver (26LS32 or 26C32) on another PWB. This
sounds pretty flaky to me (even if the skew between A & B is minimized),
and I wanted to get some experienced Virtex designers' opinion of it. Do
LVTTL drivers really want to look into the 100 ohm termination that is
at the receiving end? Will the assymetry in IOL/IOH be a problem?


--
==============================
William Lenihan
lenihan3weNOSPAM@earthlink.net
==============================


Article: 24451
Subject: CLKDLL for Virtex PCI?
From: Bill Lenihan <lenihan3weNOSPAM@earthlink.net>
Date: Wed, 09 Aug 2000 07:09:02 GMT
Links: << >>  << T >>  << A >>
The Xilinx PCI Core for Virtex does not itself contain a CLKDLL.
Should (or must?) it's clock pin be driven from (a) a CLKDLL or (b) an
IBUFG instantiated at the next higher level of heirarchy?

--
==============================
William Lenihan
lenihan3weNOSPAM@earthlink.net
==============================


Article: 24452
Subject: Re: Who needs all those printed ac parameters?
From: eml@riverside-machines.com.NOSPAM
Date: Wed, 09 Aug 2000 10:16:52 GMT
Links: << >>  << T >>  << A >>
On Fri, 04 Aug 2000 16:24:41 -0400, rickman <spamgoeshere4@yahoo.com>
wrote:

>So I would say that most good designers *require* the AC timing
>parameters to be in the data sheets. 

Yes, but what use is it to know that, for example, tFANDXB (F1/2
operand inputs to XB output via AND) is 0.36ns, when you have no idea
how long it takes your signal to get to F, or from XB? Or, for an
extreme example, what about tON, the internal tristate enable? The
databook says that this is 90ps for a Virtex-6. But, the real
point-to-point delays I've measured on TRCE are, unsurprisingly, over
*50 times* this value. So the databook gives us enough information to
get 2% of the actual value.

What's the point of having only half the story, in detail, in the
databook? The detailed info has to be somewhere, together with some
routing estimates, but it might as well be in an app note as anywhere
else. More info, please, not less, but I don't care where it is.

Evan
Article: 24453
Subject: Re: XST?
From: eml@riverside-machines.com.NOSPAM
Date: Wed, 09 Aug 2000 10:18:03 GMT
Links: << >>  << T >>  << A >>
On Mon, 07 Aug 2000 23:28:44 -0400, rickman <spamgoeshere4@yahoo.com>
wrote:

>What is going on with the revamp of the tools in ISE 3.1? Does anyone
>have an idea of why Xilinx wants to change the toolset and start from
>scratch every year or two? 

Acquisition - they buy their own technology, and so don't have to ship
a third party's toolset. Of course, they'll eventually decide to
concentrate on their core business, sell off the software side, and
then ship a third party's tools, but hopefully that's a few years
away.

I, for one, won't be sorry to see the end of Aldec - I tried the
schematics for a couple of days, and gave up. I had a 30-day trial
with the Synario schematics a few years ago, and was relatively
impressed, although I didn't buy it. I used the Synario frontend with
Abel for a few years and had no problem with it.

>The one I really don't get is the Elite packages. The Express package
>supports every part other than the Virtex E > 1 million gates. For those
>largest two or three parts, they make you use a different package. Is
>there some special reason for that???

Are you sure about this? I thought you had to sign an NDA, and then
they gave you a different key for the same CD, so that you could
install the device files.

Evan
Article: 24454
Subject: Re: Xilinx Foundation 3.1i
From: eml@riverside-machines.com.NOSPAM
Date: Wed, 09 Aug 2000 10:19:18 GMT
Links: << >>  << T >>  << A >>
On Mon, 07 Aug 2000 10:09:02 -0700, Philip Freidin
<philip@fliptronics.com> wrote:

>On Mon, 07 Aug 2000 13:36:30 +0100, Rick Filipkiewicz <rick@algor.co.uk> wrote:

>>Considering that I now have to pay the ``time based license'' fee aka
>>`the shareholders are complaining and chip prices are competitive so
>>lets make more money out of the s/w' I want to know what the benefits
>>are, if any.
>
>No you dont. The second paragraph of the license is:
>
>"IF YOU HAVE OBTAINED THIS SOFTWARE AS AN UPDATE
>TO SOFTWARE FOR WHICH YOU HAVE PREVIOUSLY
>OBTAINED A LICENSE,  THE TERMS OF THAT PRIOR
>LICENSE WILL CONTINUE TO CONTROL YOUR USE OF
>THE SOFTWARE.  IF YOU ARE A QUALIFIED UNIVERSITY
>USER, YOU MAY OBTAIN AN EXTENSION OF THIS LICENSE
>BY REGISTERING WITH THE XILINX UNIVERSITY PROGRAM."

I think it's a bit more complicated than this. When they originally
announced this, about a year ago, I came to the conclusion that you
were Ok as long as you continued to pay the maintenance on your old
software. If you let the maintenance lapse - you're on holiday, for
example, and you're a couple of weeks late with that cheque - then you
no longer qualify, and you have to start buying the software on the 
new one-year scheme.

I never got a definitive answer on this, so I may be wrong. By
contrast, here's ModelSim's maintenance reminder that I got this
morning:

> ================================================================
> ModelSim uses version-based licensing which permits customers
> to use any software released while their products are under
> maintenance. For example, if the maintenance expired during
> March 2000, all software released before 1 March 2000 will run, but
> none released after that date (until maintenance is renewed).
> Note that earlier software continues to work; only later
> releases are affected by version-based licensing!

So, Xilinx, how about a statement that's as clear, concise, and
reasonable as this one? 

Evan
Article: 24455
Subject: Re: Help!! Virtex system gate count.
From: jimmy75@my-deja.com
Date: Wed, 09 Aug 2000 12:20:46 GMT
Links: << >>  << T >>  << A >>
Thanks Peter for your thorough reply. IT MAKES PERFECT SENSE. Moreover,
I will go as far as saying that it is pretty conservative. You could
easily make it look even bigger :-)

Thanks again!


Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 24456
Subject: Re: XST?
From: rickman <spamgoeshere4@yahoo.com>
Date: Wed, 09 Aug 2000 09:03:43 -0400
Links: << >>  << T >>  << A >>
eml@riverside-machines.com.NOSPAM wrote:
> >The one I really don't get is the Elite packages. The Express package
> >supports every part other than the Virtex E > 1 million gates. For those
> >largest two or three parts, they make you use a different package. Is
> >there some special reason for that???
> 
> Are you sure about this? I thought you had to sign an NDA, and then
> they gave you a different key for the same CD, so that you could
> install the device files.

I am just reading what they say on their web site. Check it out at
http://xilinx.com/products/products.htm.


-- 

Rick Collins

rick.collins@XYarius.com

Ignore the reply address. To email me use the above address with the XY
removed.



Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX

Internet URL http://www.arius.com
Article: 24457
Subject: 3-state busses on Virtex?
From: Steven Sanders <sanders@imec.be>
Date: Wed, 09 Aug 2000 16:09:54 +0200
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.
--------------5A5E82123D44B10B5D78036E
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

Hello,

I was wondering how 3-state busses are REALLY implemented in Virtex
devices. Is a real 3-state bus possible or is everything divided in
separate lines from block to block which accesses the bus?

Thanx in advance!

Steven.
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--------------5A5E82123D44B10B5D78036E--

Article: 24458
Subject: Re: Who needs all those printed ac parameters?
From: husby@fnal.gov (Don Husby)
Date: Wed, 09 Aug 2000 14:12:05 GMT
Links: << >>  << T >>  << A >>
eml@riverside-machines.com.NOSPAM wrote:
> Yes, but what use is it to know that, for example, tFANDXB (F1/2
> operand inputs to XB output via AND) is 0.36ns, when you have no idea
> how long it takes your signal to get to F, or from XB?
> ...

It does.  For example, when you're trying to meet a 7 ns cycle time
and you have a few paths that just don't make it, it helps to know that
you could shave a few picoseconds off the path (and possibly free up some
over-used routing paths) if you use a synchronous-reset or clock-enable
instead of LUT logic (or vice-versa).  While this seems like a minor
design change that can be tested quickly, such changes can actually take
hours because you might have to re-do the logic equations, then struggle
with VHDL to coax it to do what you want, than re-compile, place and route.

  A table of timing parameters lets you quickly decide whether or not
it's worth the effort.  I had a classic example of this just a few days
ago:  determine whether to implement a function using the carry chain
or combinatorial logic.  It turns out that this particular 8-bit function
is faster by about 1 ns with combinatorial logic.  If I was using a Xilinx
chip I would probably have needed the tFANDXB timing parameter for this.


 


--
Don Husby <husby@fnal.gov>             http://www-ese.fnal.gov/people/husby
Fermi National Accelerator Lab                          Phone: 630-840-3668
Batavia, IL 60510                                         Fax: 630-840-5406
Article: 24459
Subject: Re: Viewlogic Licencing
From: Greg Neff <gregneff@my-deja.com>
Date: Wed, 09 Aug 2000 17:28:55 GMT
Links: << >>  << T >>  << A >>
I just got back from vacation, so here is my belated reply:

In article <01bff9e7$9343d100$ac07f7a5@drt1>,
  "Austin Franklin" <austin@darkroom88.com> wrote:
> > Since we use both OrCAD and Viewlogic tools, I have to say that
OrCAD's
> > entry tools are easier to use, and we are more productive when using
> > them.
>
> I am sorry to sound so cynical if you are really serious,

Yup, very serious.  It's okay to be cynical, so are we.  We don't love
OrCAD, but so far it is still our board schematic tool of choice.

> but I just can't
> believe anyone would...COULD make that statement with a straight
face, or
> at least without a lot of inebriation...  OrCAD is undoubtedly the
WORST
> schematic 'scribbling' program I have ever used.  And the worst part
is,
> they charge a LOT for it!  If it was $99, I'd take it seriously.  I'd
> rather use stone and chisel...

The worst schematic package I have used is the one packaged with Xilinx
Foundation.

There is a _big_ learning curve to be proficient with OrCAD Capture.
It has a lot of quirks, but it also has a lot of power if you know how
to use it.

>
> It has the worst text handling capabilities I have ever seen.  You
can't
> like up the text unless you do it all ONE way,

Some parts of OrCAD are a PITA, and there are bugs.  That being said, I
don't know of any CAD package that doesn't have a variety of bugs.

> and bus handling is just so
> so bad.

It works OK for me...

> And...what's with "off page connectors"?  What's the point?

We don't use off page connectors, because we don't draw flat
schematics.  All of our schematics are hierarchical, so all sheet
interconnections are drawn using nets and busses via hierarchical
ports.  They are not as easy to draw as dangling nets, but they do
enhance readability of the schematics when following nets between
sheets.

> Try
> putting a net just on top of a bus that goes up...you can't!  You
have to
> do all sorts of little jaggies to go up, around and over...  And the
list
> goes on...

Again, OrCAD does have its annoying aspects, but so does any schematic
package that I have used.

>
> I personally find ViewDraw to be one of the best, if not the best
schematic
> drawing program out there...and I've used quite a few...

ViewDraw may very well be the best schematic capture package, from a
technical perspective.

> What were your
> complaints with ViewDraw?

ViewDraw produces a mess of files that you have to keep track of, and
you have to archive the libraries along with the schematics.  This is a
PITA for build configuration management, and for project delivery to
customers.  OrCAD has a single .DSN file, which includes all schematic
sheets and part symbols.

Having used both ViewDraw and OrCAD SDT / Capture for many years, I
find it faster and easier to produce symbols (parts) and schematics
with OrCAD than with ViewDraw.

And last but not least, most of our customers want board schematics in
OrCAD format.

>
> Sorry, I know this isn't the OrCAD bashing group...
>
>

You will notice that our reasons for using OrCAD are not because we
think that it is technically the best.  Things like configuration
management, portability, productivity, and readability are factors that
are important to us, and reasons why we continue to use OrCAD.

--
Greg Neff
VP Engineering
*Microsym* Computers Inc.
greg@guesswhichwordgoeshere.com


Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 24460
Subject: Re: Crossing Clock Domains.
From: "Barry Brown" <barry_brown@agilent.com>
Date: Wed, 9 Aug 2000 10:31:56 -0700
Links: << >>  << T >>  << A >>
Chris,

What is "isd magazine", please?

Thanks,
Barry Brown


Chris Fritz wrote in message ...
>You might check out an article in the March 2000 isd magazine (page 22-30)
>by Peter Alfke.
>
>"Moving Data across Asynchronous Clock Boundaries"
>
>It has some good information highlighting the problems with moving data
>between clock domains.
>
>Regards,
>Chris Fritz
>Freestone Systems Inc.
>
>
>
>K. Orthner <korthner@hotmail.nospam.com> wrote in message
>news:8F897D1AAkorthnerhotmailcom@158.202.232.7...
>> I'm working on a design where I have two clock domains.
>>
>> I've decided to implement everything crossing the two domains using
FIFOs,
>> both BlockRAM-based, and distributed RAM based.
>>
>> I've looked at two application notes that deal with this, One aimed at
the
>> Spatan-II, and one for the 4000 series.
>>
>> In the appnote for the 4000 series (XAPP051, 1996, Peter Afke), Grey
>> counters are used to improve speed and to simplify the generation of the
>> FULL and EMPTY signals to prevent "weird" states.  The new appnote for
>> Spartan-II (XAPP175, 11/99) discusses pretty much the same thing, using
>> grey counters and what-not, as well as keeping copies of "next_pointer"s
>> make full and empty synchronous signals.
>>
>> The new appnote doesn't seem to consider how to prevent problems arising
>> from using the two clock domains, however.  I've copied what it said
>below,
>> for anyone who wants to read it.
>>
>> In the old appnote, it suggested using latches, to latch the empty/fuill
>> signal that was generated in the other clock domain, and then re-clocking
>> the output of the latch with the desired clock.
>>
>> So, my question is, is it really suggested to use a latch at the output
of
>> simple combinatorial logic to "stretch" the full/empty signal and then
re-
>> clock it?
>>
>> I'm somewhat new to working in two clock domains, and I would rather
>figure
>> it all out now, as I'm doing my design, then later when I'm dabugging it.
>>
>> Thanks a million.
>>
>> -Kent
>>
>>
>> From XAPP175:
>>
>> "To solve this problem, and to maximize the speed of the control logic,
>> additional logic complexity is accepted for increased performance. There
>> are primary 9-bit Read and Write binary address counters, which drive the
>> address inputs to the Block RAM. The binary addresses are converted to
>> Gray-code, and pipelined for a few stages to create several address
>> pointers (read_addrgray, read_nextgray, read_lastgray, write_addrgray,
>> write_nextgray) which are used to generate the Full and Empty flags as
>> quickly as possible. Gray-code addresses are used so that the registered
>> Full and Empty flags are always clean, and never in an unknown state due
>to
>> the asynchronous relationship of the Read and Write clocks. In the worst
>> case scenario, Full and Empty would simply stay active one cycle longer,
>> but this would not generate an error."
>>
>
>


Article: 24461
Subject: Re: Crossing Clock Domains.
From: Peter Alfke <peter@xilinx.com>
Date: Wed, 09 Aug 2000 11:53:01 -0700
Links: << >>  << T >>  << A >>

--------------B515C7785F6D2C3E996D5E2A
Content-Type: text/plain; charset=us-ascii; x-mac-type="54455854"; x-mac-creator="4D4F5353"
Content-Transfer-Encoding: 7bit

For the article on crossing clock boundaries, just click on:

http://www.isdmag.com/editorial/2000/design0003.html

Peter Alfke
===============================================
Barry Brown wrote:

> Chris,
>
> What is "isd magazine", please?
>
> Thanks,
> Barry Brown
>
> Chris Fritz wrote in message ...
> >You might check out an article in the March 2000 isd magazine (page 22-30)
> >by Peter Alfke.
> >
> >"Moving Data across Asynchronous Clock Boundaries"
> >
> >It has some good information highlighting the problems with moving data
> >between clock domains.
> >
> >Regards,
> >Chris Fritz
> >Freestone Systems Inc.
> >
> >
> >
> >

--------------B515C7785F6D2C3E996D5E2A
Content-Type: text/html; charset=us-ascii
Content-Transfer-Encoding: 7bit

<!doctype html public "-//w3c//dtd html 4.0 transitional//en">
<html>
For the article on crossing clock boundaries, just click on:
<p><u><A HREF="http://www.isdmag.com/editorial/2000/design0003.html">http://www.isdmag.com/editorial/2000/design0003.html</A></u><u></u>
<p>Peter Alfke
<br>===============================================
<br>Barry Brown wrote:
<blockquote TYPE=CITE>Chris,
<p>What is "isd magazine", please?
<p>Thanks,
<br>Barry Brown
<p>Chris Fritz wrote in message ...
<br>>You might check out an article in the March 2000 isd magazine (page
22-30)
<br>>by Peter Alfke.
<br>>
<br>>"Moving Data across Asynchronous Clock Boundaries"
<br>>
<br>>It has some good information highlighting the problems with moving
data
<br>>between clock domains.
<br>>
<br>>Regards,
<br>>Chris Fritz
<br>>Freestone Systems Inc.
<br>>
<br>>
<br>>
<br>></blockquote>
</html>

--------------B515C7785F6D2C3E996D5E2A--

Article: 24462
Subject: Re: Crossing Clock Domains.
From: "Chris Fritz" <chris.fritz@att.net>
Date: Wed, 09 Aug 2000 19:21:40 GMT
Links: << >>  << T >>  << A >>
Integrated System Design Magizine

You can get information at their website at http://www.isdmag.com/ .

Regards,
Chris

Barry Brown <barry_brown@agilent.com> wrote in message
news:8ms4im$jsr$1@nirvana.soco.agilent.com...
> Chris,
>
> What is "isd magazine", please?
>
> Thanks,
> Barry Brown
>
>
> Chris Fritz wrote in message ...
> >You might check out an article in the March 2000 isd magazine (page
22-30)
> >by Peter Alfke.
> >
> >"Moving Data across Asynchronous Clock Boundaries"
> >
> >It has some good information highlighting the problems with moving data
> >between clock domains.
> >
> >Regards,
> >Chris Fritz
> >Freestone Systems Inc.
> >
> >
> >
> >K. Orthner <korthner@hotmail.nospam.com> wrote in message
> >news:8F897D1AAkorthnerhotmailcom@158.202.232.7...
> >> I'm working on a design where I have two clock domains.
> >>
> >> I've decided to implement everything crossing the two domains using
> FIFOs,
> >> both BlockRAM-based, and distributed RAM based.
> >>
> >> I've looked at two application notes that deal with this, One aimed at
> the
> >> Spatan-II, and one for the 4000 series.
> >>
> >> In the appnote for the 4000 series (XAPP051, 1996, Peter Afke), Grey
> >> counters are used to improve speed and to simplify the generation of
the
> >> FULL and EMPTY signals to prevent "weird" states.  The new appnote for
> >> Spartan-II (XAPP175, 11/99) discusses pretty much the same thing, using
> >> grey counters and what-not, as well as keeping copies of
"next_pointer"s
> >> make full and empty synchronous signals.
> >>
> >> The new appnote doesn't seem to consider how to prevent problems
arising
> >> from using the two clock domains, however.  I've copied what it said
> >below,
> >> for anyone who wants to read it.
> >>
> >> In the old appnote, it suggested using latches, to latch the
empty/fuill
> >> signal that was generated in the other clock domain, and then
re-clocking
> >> the output of the latch with the desired clock.
> >>
> >> So, my question is, is it really suggested to use a latch at the output
> of
> >> simple combinatorial logic to "stretch" the full/empty signal and then
> re-
> >> clock it?
> >>
> >> I'm somewhat new to working in two clock domains, and I would rather
> >figure
> >> it all out now, as I'm doing my design, then later when I'm dabugging
it.
> >>
> >> Thanks a million.
> >>
> >> -Kent
> >>
> >>
> >> From XAPP175:
> >>
> >> "To solve this problem, and to maximize the speed of the control logic,
> >> additional logic complexity is accepted for increased performance.
There
> >> are primary 9-bit Read and Write binary address counters, which drive
the
> >> address inputs to the Block RAM. The binary addresses are converted to
> >> Gray-code, and pipelined for a few stages to create several address
> >> pointers (read_addrgray, read_nextgray, read_lastgray, write_addrgray,
> >> write_nextgray) which are used to generate the Full and Empty flags as
> >> quickly as possible. Gray-code addresses are used so that the
registered
> >> Full and Empty flags are always clean, and never in an unknown state
due
> >to
> >> the asynchronous relationship of the Read and Write clocks. In the
worst
> >> case scenario, Full and Empty would simply stay active one cycle
longer,
> >> but this would not generate an error."
> >>
> >
> >
>
>


Article: 24463
Subject: Timing Constraints
From: "Andreas Wuestefeld" <andreas.wuestefeld@ertec.com>
Date: Wed, 9 Aug 2000 21:30:35 +0200
Links: << >>  << T >>  << A >>
Hi,

how can I get the external clock in my VHDL-Program? There is only VHDL, no
Schematic. I'm usig the Foundation 2.1i and want to programm a Spartan FPGA.
The BUFGS is programed with the Language Assistent. There are no synthesis
errors. What do I have to do in the Constraint Editor or in the ucf-file?

Thanks

Andreas


Article: 24464
Subject: Advantages and desadvantages of a reconfigurable processor
From: robby75@my-deja.com
Date: Wed, 09 Aug 2000 20:49:18 GMT
Links: << >>  << T >>  << A >>
Hi FPGA freaks,

Can you, please, enumerate the advantages and disadvantages of a
microprocessor with an on-chip reconfigurable logic. A year ago,
Triscend have anounced the first Micro-controller with reconfigurable
logic (configurable system on a chip CSoC). Apart from Xess who have
developed a board based on CSoC, I did not hear much about it.
The idea seems great and dates from some time now. Are there any
practical limitations?

NB. CSoC is just an example, consider the idea itself...

Cheers.



Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 24465
Subject: Replacement for Altera ByteBlaster & ByteBlasterMV
From: bingoeugene@my-deja.com
Date: Thu, 10 Aug 2000 01:06:46 GMT
Links: << >>  << T >>  << A >>
Reliable and cost effective replacement solution for the Altera
Corporation ByteBlaster and ByteBlasterMV download cable. Downloads
data from the MAX+PLUS  II development software.Programs MAX  9000,
7000 in-system. Configures FLEX  20K, 10K, FLEX 8K, FLEX 6K devices

AnyVoltage VCC ( from 1.8 V - 5.5 V)

AnyVoltage FPGA / EPLD I/O ( 1.8 V - 5.5 V)

3' Cable version available

You will never need another FPGA downloader.


Please visit: http://welcome.to/nefdesign.com


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Before you buy.
Article: 24466
Subject: Re: XST?
From: Ray Andraka <ray@andraka.com>
Date: Thu, 10 Aug 2000 01:48:08 GMT
Links: << >>  << T >>  << A >>


rickman wrote:
> 
> rodger wrote:
> >
> > XST is Xilinx Synthesis Technology and is included, I believe, with
> > the new Foundation ISE 3.1i. Foundation ISE 3.1i is based, I believe,
> > on the Synario Project Navigator and includes a schematic capture tool.
> 
> What is going on with the revamp of the tools in ISE 3.1? Does anyone
> have an idea of why Xilinx wants to change the toolset and start from
> scratch every year or two?

Yeah, it's to make consultants go crazy
keeping up with the tools :-)

Seriously, the explanation I got was
that the relationships with 3rd party
tools suppliers sours after a period of
time.  Maybe they should work on
industrial relations instead.  The way I
see it, it is just one more cheap tool I
have to either work around or convince
the customer that the savings is more
than eaten up in design time/difficulty.

> 
> Now instead of supporting two Foundation tools (Basic and Express), they
> are supporting seven different versions of the tools. And then they tell
> us that it is too much support work to give out the bitstream
> information... ???
> 
> The one I really don't get is the Elite packages. The Express package
> supports every part other than the Virtex E > 1 million gates. For those
> largest two or three parts, they make you use a different package. Is
> there some special reason for that???
> 
> --
> 
> Rick Collins
> 
> rick.collins@XYarius.com
> 
> Ignore the reply address. To email me use the above address with the XY
> removed.
> 
> Arius - A Signal Processing Solutions Company
> Specializing in DSP and FPGA design
> 
> Arius
> 4 King Ave
> Frederick, MD 21701-3110
> 301-682-7772 Voice
> 301-682-7666 FAX
> 
> Internet URL http://www.arius.com

-- 
-Ray Andraka, P.E.
President, the Andraka Consulting Group,
Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com  or
http://www.fpga-guru.com
Article: 24467
Subject: Re: Can i see Gate-delay and Interconnection-delay of circuit on FPGA
From: Ray Andraka <ray@andraka.com>
Date: Thu, 10 Aug 2000 01:53:56 GMT
Links: << >>  << T >>  << A >>
This is not something the faint of heart
would want to do in an FPGA.  If you are
going to do it, you'll want to
structurally instantiate your design
rather than synthesize it, and you'll
want to do at least the placement by
hand to make sure the routing doesn't
kill you.  You may even find that you
need to do the routing by hand as well. 
For the delays, you need to look at the
post PAR results, as the stuff from the
synthesizer is only an estimate based on
the logic inferred.  Your best path for
success will have you spending a
considerable amount of time in the
timing anaylzer and FPGA editor tools..

Phunjapa Ruangsinsup wrote:
> 
> I must design asynchronous circuit on FPGA and I must know Gate-delay and
> interconnection delay for create Complete signal check (the signal which
> have delay longest than another in circuit). I design by RTL-VHDL code and
> synthesis by Xilinx Foundation 2.1i, my synthesis output is VHDL and SDF
> code. So can i use delay report from SDF code to be a Gate-delay?? and Where
> i can see interconection-delay of each signal??

-- 
-Ray Andraka, P.E.
President, the Andraka Consulting Group,
Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com  or
http://www.fpga-guru.com
Article: 24468
Subject: Re: Crossing Clock Domains.
From: Peter Alfke <palfke@earthlink.net>
Date: Thu, 10 Aug 2000 03:09:55 GMT
Links: << >>  << T >>  << A >>

--------------DBEFDE7E9382F9840B673ED8
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Content-Transfer-Encoding: 7bit


For the article on crossing clock boundaries, just click on:

http://www.isdmag.com/editorial/2000/design0003.html

Peter Alfke
==============================
Chris Fritz wrote:

> Integrated System Design Magizine
>
> You can get information at their website at http://www.isdmag.com/ .
>
> Regards,
> Chris
>

--------------DBEFDE7E9382F9840B673ED8
Content-Type: text/html; charset=us-ascii
Content-Transfer-Encoding: 7bit

<!doctype html public "-//w3c//dtd html 4.0 transitional//en">
<html>
&nbsp;
<br>For the article on crossing clock boundaries, just click on:
<p><u><A HREF="http://www.isdmag.com/editorial/2000/design0003.html">http://www.isdmag.com/editorial/2000/design0003.html</A></u><u></u>
<p>Peter Alfke
<br>==============================
<br>Chris Fritz wrote:
<blockquote TYPE=CITE>Integrated System Design Magizine
<p>You can get information at their website at <a href="http://www.isdmag.com/">http://www.isdmag.com/</a>
.
<p>Regards,
<br>Chris
<br>&nbsp;</blockquote>
</html>

--------------DBEFDE7E9382F9840B673ED8--

Article: 24469
Subject: Re: 3-state busses on Virtex?
From: Philip Freidin <philip@fliptronics.com>
Date: Wed, 09 Aug 2000 23:05:41 -0700
Links: << >>  << T >>  << A >>
On Wed, 09 Aug 2000 16:09:54 +0200, Steven Sanders <sanders@imec.be> wrote:

>Hello,
>
>I was wondering how 3-state busses are REALLY implemented in Virtex
>devices. Is a real 3-state bus possible or is everything divided in
>separate lines from block to block which accesses the bus?
>Thanx in advance!
>Steven.

The best way to answer questions like this is to get the IBM patent
server to help you. Try this:

    http://204.146.135.160/cgi-bin/viewpat.cmd/US05677638__

and

   http://204.146.135.160/cgi-bin/viewpat.cmd/US05847580__

and

   http://204.146.135.160/cgi-bin/viewpat.cmd/US05939930__


Philip Freidin

Mindspring that acquired Earthlink that acquired Netcom has
decided to kill off all Shell accounts, including mine.

My new primary email address is    philip@fliptronics.com

I'm sure the inconvenience to you will be less than it is for me.
Article: 24470
Subject: Re: 17 clocks in a Virtex
From: Ben Franchuk <bfranchuk@jetnet.ab.ca>
Date: Thu, 10 Aug 2000 07:51:34 +0000
Links: << >>  << T >>  << A >>
Emil Blaschek wrote:
> 
> Jonas Thor schrieb:
> >
> > Hi,
> >
> > Hello!
> >
> > We have an interesting problem, 17 clocks that are not synchronized.
> > We are going to prototype an 8 port Ethernet (10 Mbit) switch in a
> > Virtex 1000. There's one tx-clock and one rx-clock for each interface
> > and there is a global clock which we will set to 10Mhz. The tx are rx
> > clocks are 2.5 MHz. The reason why the global clock will only be at 10
> > MHz is simply because we want to make the design more challenging,
> > since a low clock rate makes the queing and buffering handling more
> > difficult. I should say that I work at a university, so we are allowed
> > to make things more difficult than they really are ;)

Would not working in 4 bit nibbles be easyier as they match your 2.5 Mhz
tx/rx clocks and be easier to sync to that clock, rather than the 10Mhz
data stream. 

> >
> > Anyway our first problem is to synch the data from the 8 ports to the
> > global clock. Since we have 17 clocks we are out of global clock
> > routing. My first idea would be to have 16 16-bit deep asynch fifos
> > implemented in CLBs. Each port would have one rx fifo and one tx fifo
> > and the fifos should be placed as close to the port as possible. The
> > fifo would be based on Peter Alfkes appnote (XAPP051 I believe).
> >
> > However the problem here, as I see it, is to make sure that the skew
> > between the port data rx and tx clocks are minimal.
> >
> > Any comments about the suggested solution? Some other approach that
> > migth be better? I have never worked with a Virtex device before.
> > Previous work has been with the XC4000 and these have different clock
> > distributing resources compared the Virtex series.

> You certainly will not need 17 Clocks.
> At 10 MHz you can use oversampling.
> If you have a stabile 80MHz Clock, cou can get the incomming data,
> correlating the clock by finding the state-Changes in the incomming
> data_stream and then extracting each bit.
> Gives a lot of logic, but you only need a single clock.
> Dont worry a 80 MHz Design in VERTEX E is possible.

But they don't have a 80 Mhz clock, just a 10Mhz one.
(I assume that is phase locked to the data stream).
Ben.
-- 
"We do not inherit our time on this planet from our parents...
 We borrow it from our children."
"Octal Computers:Where a step backward is two steps forward!"
 http://www.jetnet.ab.ca/users/bfranchuk/index.html
Article: 24471
Subject: FPSLIC Software availability
From: "Ulf Samuelsson" <ulf@atmel.spammenot.com>
Date: Thu, 10 Aug 2000 11:01:50 +0200
Links: << >>  << T >>  << A >>
People interested in the Atmel FPSLIC (Combined AVR RISC, FPGA, SRAM) chip,
may be interested to know that the S/W toolsuite has now been released.
This includes
* AVR Studio Debugger
* IDS 7 FPGA layout tools (Figaro)
* Mentor Leonardo
* Mentor Modelsim VHDL
* Mentor Seamless coverification tool

An evaluation board with a 4 month S/W license will be available in 6-8
weeks.

--
Best regards,
ulf at atmel dot com
The contents of this message is intended to be my private opinion and
may or may not be shared by my employer Atmel Sweden



Article: 24472
Subject: Where i can found Gate-delay or CLB internal-delay
From: "Phunjapa Ruangsinsup" <mpr@siampage.com>
Date: Thu, 10 Aug 2000 02:05:10 -0700
Links: << >>  << T >>  << A >>
I'm design my circuit, synthesis and Place & route my circuit by xilinx
foundation 2.1i. I try to see net-delay (interconnect-delay). And i found
only net-delay by FPGA Editor, So Where i can see Gate-delay or CLB
internal-delay?
Article: 24473
Subject: leonardo/altera/LPM_RAM_DP
From: cmautner@frqwol3ux.frequentis.frq (Christian Mautner)
Date: 10 Aug 2000 09:28:20 GMT
Links: << >>  << T >>  << A >>
Hi, all.

I have the following problem: My current design (ACEX (aka cheap 10ke), 
synthesis with leonardo) needs some dual ported RAMs. I explicitly instantiate
them, like

> m : LPM_RAM_DP
>     GENERIC MAP (lpm_widthad => depthbits,
> [...]
>     PORT MAP (
>         rdclock => clk,
> [...]

Now, unfortunately leonardo does not recognize the modules: 

> Total accumulated area : 
> [...]
>  Black Box lpm_ram_dp_2_10_1024_REGISTERED_REGISTERED_REGISTERED_REGISTERED_
UNUSED_LPM_RAM_DP_UNUSED :     2
>  Black Box lpm_ram_dp_8_5_32_REGISTERED_REGISTERED_REGISTERED_REGISTERED_UNU
SED_LPM_RAM_DP_UNUSED :     4

And then the timing analysis is far off reality, as I don't believe
that reading from a registered output could need 5ns.

> Critical path #1, (path slack = -4.3):
> [...]
> default arrival at blackbox outputs                                  5.00

As can seen from the slack, I would meet the timing if leonardo would
know the realistic arrival time from the RAM.

Anyone got a similar problem? Would automatic RAM inferring (which I
do not trust) help? Can I tell leonardo anthing about the timing of
the black boxes?

BTW, I know that the timing report from the synthesis tool is not too
usefull at all, but finding the critical paths is easier with leonardo
than with MaxPlus2.

chm.

-- 
Christian Mautner                           Frequentis Vienna, Austria
cmautner@frequentis.com                               +43-1-81150-2331
Article: 24474
Subject: Re: 17 clocks in a Virtex
From: Emil Blaschek <emil.blaschek@siemens.at>
Date: Thu, 10 Aug 2000 13:24:56 +0200
Links: << >>  << T >>  << A >>
Jonas Thor schrieb:
> 
> Hi,
> 
> Hello!
> 
> We have an interesting problem, 17 clocks that are not synchronized.
> We are going to prototype an 8 port Ethernet (10 Mbit) switch in a
> Virtex 1000. There's one tx-clock and one rx-clock for each interface
> and there is a global clock which we will set to 10Mhz. The tx are rx
> clocks are 2.5 MHz. The reason why the global clock will only be at 10
> MHz is simply because we want to make the design more challenging,
> since a low clock rate makes the queing and buffering handling more
> difficult. I should say that I work at a university, so we are allowed
> to make things more difficult than they really are ;)
> 
> Anyway our first problem is to synch the data from the 8 ports to the
> global clock. Since we have 17 clocks we are out of global clock
> routing. My first idea would be to have 16 16-bit deep asynch fifos
> implemented in CLBs. Each port would have one rx fifo and one tx fifo
> and the fifos should be placed as close to the port as possible. The
> fifo would be based on Peter Alfkes appnote (XAPP051 I believe).
> 
> However the problem here, as I see it, is to make sure that the skew
> between the port data rx and tx clocks are minimal.
> 
> Any comments about the suggested solution? Some other approach that
> migth be better? I have never worked with a Virtex device before.
> Previous work has been with the XC4000 and these have different clock
> distributing resources compared the Virtex series.
> 
> Jonas Thor
> NoSpamthor@sm.luth.seNoSpam - remove the obvious when replying
> Lulea University of Technology
> Sweden


You certainly will not need 17 Clocks.
At 10 MHz you can use oversampling.
If you have a stabile 80MHz Clock, cou can get the incomming data, 
correlating the clock by finding the state-Changes in the incomming
data_stream and then extracting each bit.
Gives a lot of logic, but you only need a single clock.
Dont worry a 80 MHz Design in VERTEX E is possible.

Happy Coding 
DI(TU) E.Blaschek


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