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Messages from 24525

Article: 24525
Subject: Re: Xilinx chip not programming correctly
From: Peter Alfke <peter@xilinx.com>
Date: Fri, 11 Aug 2000 15:17:44 -0700
Links: << >>  << T >>  << A >>
Below is the answer I got from one of our application engineers.

In the early XC4000 data sheet, I had written some tutorial comments:

"Start-up is the transition from the configuration process to the intended user operation. This means a change fromone clock source to another, and a change from interfacing to parallel or serial configuration data while most outputs are 3-stated, to normal user operation with active I/O.
Start-up must make sure that the user logic wakes up gracefully, that the outputs become active without causing contention with configuration signals, and that the internal flip-flops are being released from global set or reset at the right time."

I have often compared this to the most dramatic moment in anybody's life, when being switched away from free oxygen supply in the womb, to active breathing. Usually involves a clap on the behind for proper synchronization.
Anyhow, this is what I got from Mark in Applications. Hope it answers your question:


The warning message from bitgen is simply indicating to the user that their
design has a signal attached to the STARTUP CLK pin, which would ordinarily
indicate that they wish to use this signal as the startup clock, but they
have specifically selected the CCLK for the startup clock via the command
line. We consider this a warning because the circuit will function (using
CCLK for startup) but it seems likely that the designer probably wanted to
use their own clock for startup. Otherwise there is no point in connecting
a signal to the STARTUP CLK pin in the first place.

I also doubt that the xchecker program is the problem, but in the M1.5 release
that he is using the replacement for xchecker is hwdebugr.exe. It is a GUI that
has more functionality than xchecker but it does support the xchecker cable.

Mark
=======================================
Ramy wrote:

> Thanks Peter.
>
> I suspect the problem is in the bit file generated. This is the log file BOX.BGN at the end. It mentions a possible warning about the STARTUP and the CCLK. I don't understand what it means. Could you explain its meaning and a possible fix?
>
> I'm using an external 8 MHz clock that is divided into a 2 MHz clock inside the chip. This clock signal is connected to the STARTUP and all other flipflops, etc. The external 8 MHz clock is used only to clock the 2-bit clock divider.
>
> Another possibility is that my XCHECKER.EXE program might be too old to program the chip? I'm using a DOS version 5.2.0. I haven't been able to find a more recent version. If you know where I can find it, (DOS or UNIX) that would be great.
>
> This is the log file:
> ----------------------------
> Loading device database for application Bitgen from file "box.ncd".
>
>    "box" is an NCD, version 2.27, device xc4010e, package pg191, speed -4
>
> Loading device for application Bitgen from file '4010e.nph' in environment
>
> C:/fndtn.
>
> Opened constraints file box.pcf.
>
> BITGEN: Xilinx Bitstream Generator M1.5.25
>
> Copyright (c) 1995-1998 Xilinx, Inc.  All rights reserved.
>
> Fri Jul 21 13:13:47 2000
>
> bitgen -l -w -g ConfigRate:SLOW -g TdoPin:PULLNONE -g M1Pin:PULLNONE -g DonePin:PULLUP -g CRC:enable -g StartUpClk:CCLK -g SyncToDone:no -g DoneActive:C1 -g OutputsActive:C3 -g GSRInactive:C4 -g ReadClk:CCLK -g ReadCapture:enable -g ReadAbort:disable -g M0Pin:PULLNONE -g M2Pin:PULLNONE box.ncd
>
> WARNING:x4kbs:36 - There is a STARTUP component with a signal on the CLK pin
>
>    but StartupClk is Cclk.
>
> Running DRC.
>
> DRC detected 0 errors and 0 warnings.
>
> Saving ll file in "box.ll".
>
> Creating bit map...
>
> Saving bit stream in "box.bit".

Article: 24526
Subject: OPAL sw ex natsemi ?
From: Jim Granville <jim.granville@designtools.co.nz>
Date: Sat, 12 Aug 2000 11:48:12 +1200
Links: << >>  << T >>  << A >>
- I am looking for a copy of the old OPAL software. ( ~1995 )
It was used by natsemi for their now defunct MAPL family.

I have found Opaljr, but not OPAL. If anyone has a URL for
OPAL, or a copy ( it came on 5 1/4 disks :-) they can email,
it would be appreciated.

TIA Jim G.
Article: 24527
Subject: Re: Getting into FPGAs
From: "Tony Burch" <tony@BurchED.com.au>
Date: Sat, 12 Aug 2000 10:03:41 +1000
Links: << >>  << T >>  << A >>
>a hard time finding out information about obtaining
>FPGAs or any of the hardware one might use to program an FPGA,
>preferably in an inexpensive manner. :) Software info seems


Burch Electronic Designs sells some low cost, easy to use
FPGA Prototyping Kits.  Xilinx, Altera, Atmel, Lucent and
Actel kits are available.  www.BurchED.com.au
Kit prices start at US$66.

The Altera Max+PlusII Baseline software, which you can
use with the BED-ALTERA-BASE+ Kit, is freely
downloadable from the Altera website at
www.altera.com

Best regards
Tony Burch
www.BurchED.com.au



Article: 24528
Subject: Re: Easy question on programming
From: rickman <spamgoeshere4@yahoo.com>
Date: Fri, 11 Aug 2000 21:01:22 -0400
Links: << >>  << T >>  << A >>
Help wrote:
> 
> Hi, I'm using the Xilinx Foundation 2.1 software and coding in VHDL for a
> 5210 FPGA.  I was wondering if there is (or is there supposed to be) any
> difference in terms of delay/switching times between using a buffer vs. an
> and gate.  For example:
> 
> Buffer:
>   A <= B when en = '1' else 'Z';
> 
> AND:
>   A <= B and en;
> 
> Also, will this use a buffer, or an AND gate (or something else)?
>   A <= B when en='1' else '0';
> 
> Thanks.
> 
> (BTW, anybody have advice on some good web sites with VHDL syntax tricks
> and/or sample code?)

The timing of a buffer is very different from the timing of a gate
(LUT). The data sheet I have for the 5210-5 shows 4.2 nS from I to a
longline, 6.0 nS for the EN to the longline. The LUT delay for the same
part is 4.6 nS. So the delays are not identical, but they are somewhat
different. 

It will be likely that the routing delays will dominate the difference
in logic delays. 

The last example you give should produce an AND gate in the LUT. The
VHDL you have shown will normally produce a mux with two inputs and a
control. But since one input is a constant 0, the logic simplifies to an
AND gate. 


-- 

Rick Collins

rick.collins@XYarius.com

Ignore the reply address. To email me use the above address with the XY
removed.



Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX

Internet URL http://www.arius.com
Article: 24529
Subject: Help!! Bit serial Baugh-Wooley multiplier
From: jj_okocha@my-deja.com
Date: Sat, 12 Aug 2000 03:56:27 GMT
Links: << >>  << T >>  << A >>
Hi Guys,

Can anybody show me ( or point me toward a reference)how does a bit
serial Baugh-Wooley multiplier work??? I have a book which describes an
array multiplier (bit parallel) based on Baugh-Wooley algorithm. I
wanna know how does a bit serial one work?

Thanks a lot!


Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 24530
Subject: Re: Comparing Xilinx FPGAs
From: Peter Alfke <palfke@earthlink.net>
Date: Sat, 12 Aug 2000 04:16:49 GMT
Links: << >>  << T >>  << A >>


rickman wrote:

> For Xilinx like devices, you are much better off comparing LUT counts.
> But even there you will not be able to use the published numbers as
> Xilinx counts some imaginary LUTs to account for other features in the
> logic.

As I have said before, one can argue about the value of these
not-so-imaginary LUTs. In XC4000/Spartan there really is a third LUT in each
CLB, albeit with only 3 inputs. And Virtex has a bunch of circuits to
concatenate LUTs, so adding a half LUT to the count is not unreasonable, if
you want to compare "logic capacity".
For comparison between different Xilinx families, it makes sense to consider
the marketing LUT numbers. For comparison against the competition, you
should not ignore nice things like clock enable ( very nice to have, very
expensive when you don't get it for free...), lots of DLLs for eliminating
on-chip clock delay, LUT-RAM, LUT-shiftregisters, and of course BlockRAM (
and lots of 2's complement multipliers in the next family).

Peter Alfke

> So count the rows and the columns and multiply. This gives you
> the CLB count. In the XC4000 and Spartan series multiply by 2 to get a
> LUT count, in Virtex and Spartan II series multiply by 4 to get the LUT
> count.
>
> The LUT count is a much better measure of size equivalence between
> different Xilinx families. But do keep in mind that the Virtex and
> Spartan II lines have block RAM which can be very useful.
>
> --
>
> Rick Collins
>
> rick.collins@XYarius.com
>
> Ignore the reply address. To email me use the above address with the XY
> removed.
>
> Arius - A Signal Processing Solutions Company
> Specializing in DSP and FPGA design
>
> Arius
> 4 King Ave
> Frederick, MD 21701-3110
> 301-682-7772 Voice
> 301-682-7666 FAX
>
> Internet URL http://www.arius.com

Article: 24531
Subject: state encoding in Synplify!!!
From: "threehero" <threehero@sina.com>
Date: Sat, 12 Aug 2000 16:42:02 +0800
Links: << >>  << T >>  << A >>
I use VHDL and Synplify to describe and synthesize my design, respectively.
when i designed a state machine, I used the attribute of syn_encoding to
specify the type of state encoding, such as "gray".The number of states in
my
state machine is 20.But when I looked in the log file after synthesis, I
found
my state encoding had been converted to "one-hot" by Synplify automatically.
Why did it do such? I did not need "one-hot". How could i tell it what I
want
the state encoding to be?

Any suggestions and replies would be very appreciated!

jianjie


Article: 24532
Subject: Re: Yes but I want graphics.
From: Sigurd Urdahl <sigurdur@naglfar.ifi.uio.no>
Date: 12 Aug 2000 11:39:50 +0200
Links: << >>  << T >>  << A >>
Ben Franchuk <bfranchuk@jetnet.ab.ca> writes:

> 
> Playing around with the Altera software, using schematic entry
> I ask how can you save your schematic as a graphics image file?
> I am doing a homebrew cpu and would like to have the schematics
> on my web page. I can print to postscript printer (and save as
> file) to get postscript but it would be nice to get a GIF
> as well.

There are lots of programs that convert PS to GIF. XV does it nicely
under *nix. Search the net.

-sig
-- 
sigurd urdahl
Article: 24533
Subject: Re: Xilinx, XVC300, 18V02
From: Laurent Gauch <laurent.gauch@aps-euro.com>
Date: Sat, 12 Aug 2000 10:07:45 -0400
Links: << >>  << T >>  << A >>
Hi,

I am designing a PCI card too, but with a SPARTAN-II XC2S200 and PROM XC18V02.

Now I ask me about which configuration mode I need to use?
Master Serial Mode or Master Parallel Mode.

If I use the Master Serial Mode, I can save some IOs.

But if I use this mode,  I need to make sure about my PCI configuration time.
I don't find in the PCI specification the delay between the power-on of the PC
( and my
pci card) and the first BIOS accesss.

My question is : using a XC2S200 FPGA and XC18V02 EPROM, can I use the Master
Serial Mode
to configure my SPARTAN. Also, in this mode, using 60MHz (-30% = 42Mhz), I have
calculated
34 ms to configure my Spartan-II.
Is this 34 ms enought in a pci system ?

I cannot use the Master Parallel Mode in my system, I need IOs.

Can I use the XC18V02 @ 60Mhz ?

Thank you for you comments.

Laurent



Thomas Rinder a écrit :

> Hallo,
>
> I designed a board with a Virtex 300, XC18V02 and PCI Logicore.
> If configure the virtex via JTAG the system works correctly.
>
> In Master Serial Mode the FPGA does not start up.
>
> 1.) Which settings I need for the BITGEN command (startupclk) ? I have only
> the PCI clock at GCLK2.
> 2.) It is possible to program the XC18V02 via JTAG ?
>
> Any comments about the suggested solution?
>
> Thanks.
>
> DI(TU) Thomas Rinder
>
> --
> Dipl.Ing. Thomas  Rinder
> Meß- und Informationstechnik
> Universität der Bundeswehr
> Holstenhofweg 85
> D-22043 Hamburg
> T.: +49 40 65 41 - 3369
> F.: +49 40 65 41 - 2743
> E-Mail: thomas.rinderNOSPAM@unibw-hamburg.de

Article: 24534
Subject: XC2S200 / Master Serial / PCI system
From: Laurent Gauch <laurent.gauch@aps-euro.com>
Date: Sat, 12 Aug 2000 10:21:12 -0400
Links: << >>  << T >>  << A >>
Hi all,

I am designing a PCI card using a SPARTAN-II XC2S200 and PROM XC18V02
for the PCI interface.

Now I ask me about which configuration mode I need to use?
Master Serial Mode or Master Parallel Mode.

If I use the Master Serial Mode, I can save some IOs.

But if I use the Master Serial Mode,  I need to make sure about my PCI
configuration time.
I don't find in the PCI specification the real delay between the
power-on of the PC ( and my
pci card) and the first BIOS accesss.

My question is : using a XC2S200 FPGA and XC18V02 EPROM, can I use the
Master Serial Mode
to configure my SPARTAN. Also, in this mode, using CCLK @ 42MHz (60MHz -
30%), I have calculated
34 ms to configure my Spartan-II. (1)
Is this 34 ms enought in a pci system ?

Important too, can I use the XC18V02 @ 84 Mhz (60 MHz + 40%) ?

Thank you for you comments.

Laurent

(1) CCLK Frequency in Serial mode for Spartan-II = 4 to 60MHz with
variance (-30% +40%)




Article: 24535
Subject: Re: XC2S200 / Master Serial / PCI system
From: "Austin Franklin" <austin@dark98room.com>
Date: 12 Aug 2000 14:27:35 GMT
Links: << >>  << T >>  << A >>
> But if I use the Master Serial Mode,  I need to make sure about my PCI
> configuration time.

What I have found, after designing PCI cards for 7 years, is I have never
had a PCI configuration time issue.  Every PC BIOS that we have ever seen,
does not do the PCI bus configuration until long after the BIOS built-in
self test etc. are done.  That is many many seconds...

That's been our experience.  Has anyone had anything different?  If you are
targeting something other than a PC system, you ought check with the
vendor...or if it's embedded, you can control this issue your self.

A tip for PCI FPGA debugging...if you do not want to burn a PROM, or
program the SPROM etc, you can power up the system, hit the 'DEL' key (what
ever gets you into the BIOS configuration screen), then download your
FPGA...and continue...then the BIOS will configure your board...

Article: 24536
Subject: Re: Verilog multiplier in Xilinx...
From: "Austin Franklin" <austin@dark98room.com>
Date: 12 Aug 2000 14:36:47 GMT
Links: << >>  << T >>  << A >>
// posted to comp.arch.fpga so other people could just use it instead of
have to re-invent
// this yet again....

`timescale 1ns/1ns
`include "GenericConstants.vh"

//
// 24 bit signed by 24 bit unsigned shift-accumulate multiplier.
// this takes 24+ cycles to complete.
//

module SOURCE_GAIN (

		I_clk,
		I_reset,

		I_dav,
		I_din,
		I_SOURCE_LF_GAIN,
		I_s_lf_enabled,

		O_dav,
		O_dout

		) ;

input		I_clk ;
input		I_reset ;

input		I_dav ;			// data on I_din valid this cycle
input	[31:0]	I_din ;			// Signed 24 bit 2's compliment, MSB justified
input	[23:0]	I_SOURCE_LF_GAIN ;	// unsigned 24 bit gain multiplier
input		I_s_lf_enabled ;	// low allows MF data/dav to bypass this module

output		O_dav ;			// data on O_dout valid this cycle
output	[31:0]	O_dout ;		// output data

//
// Internal registers/signals
//

reg	[4:0]	counter ;	// shift counter...counts up to 24
reg	[46:0]	a_reg ;		// DIN shift register
reg	[23:0]	b_reg ;		// Gain shift register
reg	[46:0]	acc_reg ;	// 23 bit number times a 24 bit number results in 47
bits

reg		din_sign_reg ;	// save input data sign

wire	[22:0]	pre_dout ;	// intermediate for 2's compliment conversion
wire	[22:0]	comp_din ;	// intermediate for 2's compliment conversion

reg	[31:0]	lf_dout ;	// LF data output
reg		lf_dav ;	// LF data available output


//
// Output for bypass of MF data and dav
//

assign	O_dout[31:0] = I_s_lf_enabled ? lf_dout[31:0] : I_din[31:0] ;
assign	O_dav = I_s_lf_enabled ? lf_dav : I_dav ;


//
// Mux for positive or negative input...if negative input, convert to 2's
compliment.
//

assign	pre_dout[22:0] = din_sign_reg ? (~acc_reg[46:24] + 1) :
acc_reg[46:24] ;


//
// convert I_din from 2's compliment negative number to positive number
//

assign	comp_din[22:0] = ~(I_din[30:8] - 1) ;


//
//	How this is supposed to work...  this takes 24 cycles to do a
shift/accumulate.
//	a_reg is loaded with the value on I_din when I_dav is active, and b_reg
is loaded with
//	the balue on I_SOURCE_LF_GAIN when I_dav is active.
//
//	a_reg is shifted up every clock cycle and XOR'd to bit 0 of b_reg,
//	then added to the previous value of acc_reg to accumulate the result. 
b_reg is
//	shifted down every cycle to allow only bit 0 of b_reg to be XOR'd with
a_reg.
//
//	counter is started when I_dav is active, and counts to 25 and stops.
//	At counter == 24, O_dav is asserted for one cycle to say the data is
valid on O_dout.
//

always @ (posedge I_clk or posedge I_reset)

	begin

		if (I_reset == `ASSERTED) begin

			counter[4:0]		<= 5'b1_1001 ;
			a_reg[46:0]		<= 47'h0000_0000_0000 ;
			b_reg[23:0]		<= 24'h00_0000 ;
			acc_reg[46:0]		<= 47'h0000_0000_0000 ;
			din_sign_reg		<= 1'b0 ;

			lf_dav			<= `LOW ;
			lf_dout[31:0]		<= 32'h0000_0000 ;

		end

		else begin

			// save sign bit
			din_sign_reg		<= I_dav ? I_din[31] : din_sign_reg ;

			casex ({I_dav, (counter[4:0] == 5'b1_1000)})

				2'b1x :	counter[4:0]	<= 5'b0_0000 ;		// reset
				2'b00 :	counter[4:0]	<= counter[4:0] + 1 ;	// running
				2'b01 :	counter[4:0]	<= 5'b1_1000 ;		// hold

			endcase

			// a_reg
			// load a_reg when I_dav goes high with I_din.  If I_din is negative,
			// use convert 2's compliment input.  Shift up if not loading

			casex ({ I_dav, I_din[31]})

				2'b0x : a_reg[46:0]	<= {a_reg[45:0], 1'b0} ;
				2'b10 : a_reg[46:0]	<= {24'h00_0000, I_din[30:8]} ;
				2'b11 : a_reg[46:0]	<= {24'h00_0000, comp_din[22:0]} ;

			endcase

			// b_reg
			// load b_reg when I_dav goes high with I_SOURCE_LF_GAIN data.
			// Shift down if not loading

			b_reg[23:0]		<= I_dav ? I_SOURCE_LF_GAIN[23:0]
							 : {1'b0, b_reg[23:1]} ;

			// acc_reg
			// AND the LSB of the b_reg with the a_reg and add it to the acc_reg

			case (I_dav)

				1'b1 : acc_reg[46:0]	<= 47'h0000_0000_0000 ;	// reset
				1'b0 : acc_reg[46:0]	<= ({47{b_reg[0]}} & a_reg[46:0])
							 + acc_reg[46:0] ;	// accumulate

			endcase

			lf_dav			<= (counter[4:0] == 5'b1_0111) ;

			lf_dout[31:0] 		<= {din_sign_reg, pre_dout[22:0], 8'h00} ;

		end

	end

endmodule

Article: 24537
Subject: Re: Comparing Xilinx FPGAs
From: Ray Andraka <ray@andraka.com>
Date: Sat, 12 Aug 2000 16:27:53 GMT
Links: << >>  << T >>  << A >>


Peter Alfke wrote:
> 
> rickman wrote:
> 
> > For Xilinx like devices, you are much better off comparing LUT counts.
> > But even there you will not be able to use the published numbers as
> > Xilinx counts some imaginary LUTs to account for other features in the
> > logic.
> 
> As I have said before, one can argue about the value of these
> not-so-imaginary LUTs. In XC4000/Spartan there really is a third LUT in each
> CLB, albeit with only 3 inputs. And Virtex has a bunch of circuits to
> concatenate LUTs, so adding a half LUT to the count is not unreasonable, if
> you want to compare "logic capacity".
> For comparison between different Xilinx families, it makes sense to consider
> the marketing LUT numbers. For comparison against the competition, you
> should not ignore nice things like clock enable ( very nice to have, very
> expensive when you don't get it for free...), lots of DLLs for eliminating
> on-chip clock delay, LUT-RAM, LUT-shiftregisters, and of course BlockRAM (
> and lots of 2's complement multipliers in the next family).
> 
FWIW, the f5, F6 muxes in Virtex are not
as useful as the HLUTs were in 4K.  They
only perform the multiplxer function,
and they necessarily use both LUTs in
the slice even if one LUT is just used
for a pass-through.  The H-LUT in 4K
could be programmed with any 3 input
function, and the inputs could come
directly from outside the CLB allowing
you to use the 4 LUTs for unrelated
stuff.  In the case of the 4K family,
the HLUT was truely useful so I had no
qualms about calling it an extra LUT. 
In Virtex, I find that the instances
where I really can use the F5 mux are
relatively rare.  I can count on my
hands the number of times I've used the
f6 mux...and that is from well over 8
million gates worth of Virtex designs.
Because the use of these muxes
necessitates the use of all the LUTs
leading to it and because the function
is limited to a mux function, I think
calling the muxes an extra half LUT is
quite aggressive.

As for the clock enable I do agree. 
However, the lack of high speed high
fanout nets limits its use in fast
circuits.  The secondary high fanout
nets are way too slow for use in the
type designs where the clock enables
would be helpful on a large scale.  You
wind up using extra CLBs to construct a
clock enable tree to keep up with the
speeds the chip is otherwise capable
of.  For DSP designs, the big CLB count
savers are the ability to use the LUT as
RAM and the capability of the carry
chain architecture compared to the
competition, but then you all have seen
my comments to that effect.

> Peter Alfke
> 
> > So count the rows and the columns and multiply. This gives you
> > the CLB count. In the XC4000 and Spartan series multiply by 2 to get a
> > LUT count, in Virtex and Spartan II series multiply by 4 to get the LUT
> > count.
> >
> > The LUT count is a much better measure of size equivalence between
> > different Xilinx families. But do keep in mind that the Virtex and
> > Spartan II lines have block RAM which can be very useful.
> >
> > --
> >
> > Rick Collins
> >
> > rick.collins@XYarius.com
> >
> > Ignore the reply address. To email me use the above address with the XY
> > removed.
> >
> > Arius - A Signal Processing Solutions Company
> > Specializing in DSP and FPGA design
> >
> > Arius
> > 4 King Ave
> > Frederick, MD 21701-3110
> > 301-682-7772 Voice
> > 301-682-7666 FAX
> >
> > Internet URL http://www.arius.com

-- 
-Ray Andraka, P.E.
President, the Andraka Consulting Group,
Inc.
401/884-7930     Fax 401/884-7950
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Article: 24538
Subject: Re: Fast (> 100Mb) serial link to PC
From: "Joel Kolstad" <Joel.Kolstad@USA.Net>
Date: Sat, 12 Aug 2000 17:11:11 GMT
Links: << >>  << T >>  << A >>
This may have already been mentioned (I just switched news servers so I'm a
little out of sync with the newsgroup), but where I work we've been quite
happy using gigabit fiber optical transceivers from Amp (269152-1),
serializer/deserializers from HP (HDMP-1536... AMCC and others make clones),
and very small amounts of logic to do 8B/10B encoding/decoding.

---Joel Kolstad



Article: 24539
Subject: Re: QuickLogic PCI/FPGA chip (QL5064)...experiences?
From: Magnus Homann <d0asta@mis.dtek.chalmers.se>
Date: 12 Aug 2000 20:13:19 +0200
Links: << >>  << T >>  << A >>
"Austin Franklin" <austin@d44arkroom.com> writes:

> Thanks, have you actually used this chip?
> 
> 
> Mark Korsloot <markk@alcom.nl> wrote in article
> <39880AE9.305845C9@alcom.nl>...
> > Galileo Technology has standard 64-bit 66MHz PCI Interface chips (eg.
> > GT64121).
> > 
> > See www.galileot.com
> > 
> > Mark
> > 
> > Austin Franklin wrote:
> > > 
> > > I have a design that currently uses a PLX 9080, and I need to move it
> to a
> > > 64 bit and/or 66MHz PCI interface...  PLX does not currently offer a
> > > solution, that I can find...neither does AMCC.  Any suggestions for off
> the
> > > shelf chips to do this, or any experience with the QuickLogic QL5064
> > > interface chip?
> > > 
> > > Thanks!


I've used the GT-64120, which is pretty much the same if I remember
correctly. It's a complete system controller with memory and PCI
interface and a PowerPC interface.

Homann
-- 
Magnus Homann, M.Sc. CS & E
d0asta@dtek.chalmers.se
Article: 24540
Subject: Re: Who needs all those printed ac parameters?
From: Magnus Homann <d0asta@mis.dtek.chalmers.se>
Date: 12 Aug 2000 20:18:58 +0200
Links: << >>  << T >>  << A >>
Peter Alfke <palfke@earthlink.net> writes:

> This is Peter speaking. It is not an official  Xilinx proposal.
> It is also not an attempt to save cost and paper, although it would
> do that as a side benefit.

As living in Sweden, where trees abound and paper/pulp is a big export
commodity, I say "keep the paper"!

Quite frankly, i would like more detailed descriptions of the inner
workings, to figure out which way is the best to implement smoething.

Homann
-- 
Magnus Homann, M.Sc. CS & E
d0asta@dtek.chalmers.se
Article: 24541
Subject: Virtex 2.5V part with 5V IO problems
From: "Dan" <daniel.deconinck@sympatico.ca>
Date: Sat, 12 Aug 2000 18:38:15 GMT
Links: << >>  << T >>  << A >>
Hello

V50-6PQ240C with a 2.5V supply from a LM2937ET-2.5 and a Vcco at 3.3 volt
from a LM2937ET-3.3.


The TTL inputs are noisy.  I am interfacing the V50 to a SAA7110 Philips
video ADC.

How reliable is the V50 with 5V TTL inputs?

By touching (with my hand) the input trace & pins I am able to get a clean
input. But I can not be shipped with the product.

I wonder if the one chip I have is flaky ? I tried bringing in other TTL
signals from another PCB via a patch wire and had the same poor results.

I have several  successful Xilinx designs using the SAA7110.  This is my
first Virtex design and this is a real road block.

Ideas.


Sincerely
Daniel DeConinck



Article: 24542
Subject: Re: Yes but I want graphics.
From: somogyi@ee.ualberta.ca (Paul Somogyi)
Date: 12 Aug 2000 18:47:37 GMT
Links: << >>  << T >>  << A >>
You should download ghostscript/ghostview for windows.  Then
you can view postscript files in windows, plus you can "print"
to a variety of printers and file formats, including gif and
bmp.

You can download this from http://www.cs.wisc.edu/~ghost/

Paul

BTW, if you have access to unix then ghostscript is probably
installed.  It comes with scripts to convert ps to other
formats.


Ben Franchuk (bfranchuk@jetnet.ab.ca) wrote:
> Playing around with the Altera software, using schematic entry
> I ask how can you save your schematic as a graphics image file?
> I am doing a homebrew cpu and would like to have the schematics
> on my web page. I can print to postscript printer (and save as
> file) to get postscript but it would be nice to get a GIF
> as well.
> Ben.
> PS.I still have to find a good generic postscript printer
> to use.
> -- 
> "We do not inherit our time on this planet from our parents...
>  We borrow it from our children."
> "Octal Computers:Where a step backward is two steps forward!"
>  http://www.jetnet.ab.ca/users/bfranchuk/index.html
Article: 24543
Subject: Re: state encoding in Synplify!!!
From: wq998@my-deja.com
Date: Sat, 12 Aug 2000 23:29:35 GMT
Links: << >>  << T >>  << A >>
using syn directive /* synthesis syn_encoding="gray" */

wwq

In article <8n32kt$4ns$1@sunlight.pku.edu.cn>,
  "threehero" <threehero@sina.com> wrote:
> I use VHDL and Synplify to describe and synthesize my design,
respectively.
> when i designed a state machine, I used the attribute of syn_encoding
to
> specify the type of state encoding, such as "gray".The number of
states in
> my
> state machine is 20.But when I looked in the log file after
synthesis, I
> found
> my state encoding had been converted to "one-hot" by Synplify
automatically.
> Why did it do such? I did not need "one-hot". How could i tell it
what I
> want
> the state encoding to be?
>
> Any suggestions and replies would be very appreciated!
>
> jianjie
>
>


Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 24544
Subject: Re: Virtex 2.5V part with 5V IO problems
From: Peter Alfke <palfke@earthlink.net>
Date: Sun, 13 Aug 2000 04:52:28 GMT
Links: << >>  << T >>  << A >>


Dan wrote:

> Hello
>
> V50-6PQ240C with a 2.5V supply from a LM2937ET-2.5 and a Vcco at 3.3 volt
> from a LM2937ET-3.3.
>
> The TTL inputs are noisy.  I am interfacing the V50 to a SAA7110 Philips
> video ADC.
>
> How reliable is the V50 with 5V TTL inputs?
>
> By touching (with my hand) the input trace & pins I am able to get a clean
> input.

"The inputs are noisy". Does that mean, the ADC chip generates a noisy
output?
Then you have to fix that.
Maybe you got away with this in the past because the FPGAs were slower...

Which input standard did you program for the Virtex pins?

Input noise is not generated by the receiver, but usually by the driver or
the pc-board.
BTW: "you" seem to be no more than a 100 pF capacitor. Maybe that's a cheaper
(hokey) solution,  :-)

Just some ideas...
Peter Alfke, Xilinx Applications.

Article: 24545
Subject: Re: CLKDLL for Virtex PCI?
From: Eric Crabill <eric.crabill@xilinx.com>
Date: Sun, 13 Aug 2000 00:17:44 -0700
Links: << >>  << T >>  << A >>

Hi Bill,

You must not use a CLKDLL with the Xilinx PCI
core for Virtex.  If you use a CLKDLL, you will
create a non-compliant design.

Please use the design files that are shipped
with the core, which contain all the necessary
input/output buffer instantiations.  If you do
not use the supplied files, the associated
constraint files will fail to produce the
desired results.

Thanks,
Eric Crabill

Bill Lenihan wrote:
> 
> The Xilinx PCI Core for Virtex does not itself contain a CLKDLL.
> Should (or must?) it's clock pin be driven from (a) a CLKDLL or (b) an
> IBUFG instantiated at the next higher level of heirarchy?
> 
> --
> ==============================
> William Lenihan
> lenihan3weNOSPAM@earthlink.net
> ==============================
Article: 24546
Subject: Re: Virtex 2.5V part with 5V IO problems
From: Philip Freidin <philip@fliptronics.com>
Date: Sun, 13 Aug 2000 02:12:27 -0700
Links: << >>  << T >>  << A >>
On Sat, 12 Aug 2000 18:38:15 GMT, "Dan" <daniel.deconinck@sympatico.ca> wrote:

>Hello
>
>V50-6PQ240C with a 2.5V supply from a LM2937ET-2.5 and a Vcco at 3.3 volt
>from a LM2937ET-3.3.
>The TTL inputs are noisy.  I am interfacing the V50 to a SAA7110 Philips
>video ADC.

The inputs are quite sensitive and fast. If you see noise on the input to the
FPGA, it is not coming from the FPGA (unless you made a mistake in the design).
It is more likely coming from the ADC, or the PCB traces. For data signals into
the FPGA, you should not clock the data in until all the inputs are at a
stable and reliable logic level. For clock inputs to the FPGA, the requirements
are more stringent. You should have a signal that cleanly rises and falls, with
no glitches on either edge, and ringing must be minimized too.

>How reliable is the V50 with 5V TTL inputs?

I am sure they meet whatever spec is in the data sheet.

>By touching (with my hand) the input trace & pins I am able to get a clean
>input. But I can not be shipped with the product.

Well, you could be shipped with one instance, but that would restrict your
production run somewhat.

If you think about it, your finger placed on an input is just acting like a
capacitor, and is probably slowing down the edge rate. This wont kill glitches
reliably (so dont try horible fixes like putting a capacitor on the signal), but
because glitches due to signal integrity issues occur at a somewhat fixed time
relative to the signal source transition, and trace length, the glitch may be
occuring at a different part of a signal transition, and maybe not as it is
going through threshold. Look into proper termination.

On the other hand (pun intended) your finger is basically an outer skin, with
meat inside (and bone which I will ignore for obvious reasons). So maybe a
sausage (which has a skin, and sometimes is filled with meat) could be shipped
with each system.

>I wonder if the one chip I have is flaky ? I tried bringing in other TTL
>signals from another PCB via a patch wire and had the same poor results.

Without knowing the edge rates, and how you terminated the signal, and how you
connected the grounds, I cant really comment.

>I have several  successful Xilinx designs using the SAA7110.  This is my
>first Virtex design and this is a real road block.
>Sincerely
>Daniel DeConinck

Good luck
Philip Freidin

Philip Freidin

Mindspring that acquired Earthlink that acquired Netcom has
decided to kill off all Shell accounts, including mine.

My new primary email address is    philip@fliptronics.com

I'm sure the inconvenience to you will be less than it is for me.
Article: 24547
Subject: Re: state encoding in Synplify!!!
From: rickman <spamgoeshere4@yahoo.com>
Date: Sun, 13 Aug 2000 07:47:11 -0400
Links: << >>  << T >>  << A >>
threehero wrote:
> 
> I use VHDL and Synplify to describe and synthesize my design, respectively.
> when i designed a state machine, I used the attribute of syn_encoding to
> specify the type of state encoding, such as "gray".The number of states in
> my
> state machine is 20.But when I looked in the log file after synthesis, I
> found
> my state encoding had been converted to "one-hot" by Synplify automatically.
> Why did it do such? I did not need "one-hot". How could i tell it what I
> want
> the state encoding to be?
> 
> Any suggestions and replies would be very appreciated!
> 
> jianjie

I don't use Synplify, so I can't say for sure, but it may be that using
"Gray" coding would be very consuming of gates and the software was
smart enough to turn that off. A "Gray" coded FSM would use 5 bits to
encode 20 states. Each transistion in your state diagram (including the
"stay in this state" transistions) would require the full state vector
to be decoded. This may have required a lot of logic if you have a lot
of transistions. 

I don't think this would produce so many gates that you could not have
built the FSM, but I think "Gray" coding would require a lot more gates
than straight binary. I will have to think about that a bit. 


-- 

Rick Collins

rick.collins@XYarius.com

Ignore the reply address. To email me use the above address with the XY
removed.



Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX

Internet URL http://www.arius.com
Article: 24548
Subject: Re: tbuf
From: krw@attglobal.net (Keith R. Williams)
Date: 13 Aug 2000 14:36:04 GMT
Links: << >>  << T >>  << A >>
On Thu, 10 Aug 2000 21:05:09, "Domagoj" <domagoj@engineer.com> 
wrote:

> > What about the Automatic replacement of internal Tristates available in
> > Synthesis tools.?
> 
>     Had no idea about that possiblity.. :)
> Which tools can do that ?

Synplify has an attribute that will do this.  I believe it'll go 
either way, but I can't remember.

----
  Keith
Article: 24549
Subject: Re: Virtex 2.5V part with 5V IO problems
From: Ray Andraka <ray@andraka.com>
Date: Sun, 13 Aug 2000 15:16:45 GMT
Links: << >>  << T >>  << A >>

Philip Freidin wrote:
>
> On the other hand (pun intended) your finger is basically an outer skin, with
> meat inside (and bone which I will ignore for obvious reasons). So maybe a
> sausage (which has a skin, and sometimes is filled with meat) could be shipped
> with each system.

Ship it with cheap sausage, that way
theres a good chance you get the bone
too ;-)

-- 
-Ray Andraka, P.E.
President, the Andraka Consulting Group,
Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com  or
http://www.fpga-guru.com


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