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Hi, Tomek. >Why after writing a synthesizable project we have to write in this way >that latches was the least in the project. Latches are not synhesis >efficient, if yes will tell me why? Most FPGA's don't have latches available for use. Usually FPGA's consist of combinational logic element (Such as LUTs), and Flip-Flops. It is possible to use a latch in your design, and it will synthesize, but it's rather inefficient, because the synthesis tool "creates" the latch out of normal logic elements. Hope this helps. -KentArticle: 25226
While we're on make, does anyone know of a good Windows make? I use gmake and the make shipped with VxWorks. The gmake DOS port is pretty useless; it has problems with shells, changing directories, and so on. The VxWorks one is better, but still has problems. >[rest of dreaming snipped (but shared - I'd love to see embedded perl there, >and NOT tcl)] Why not Tcl? Tcl: Spectrum, Synplify, DC, ModelSim, FPGA Express(?), Renoir(?) Perl: Xilinx, Renoir(?) I get the impression that Tcl is now much more popular in EDA. Perl may be better at text processing, but the last thing I want to do is learn yet another language. EvanArticle: 25227
<cross-posted to comp.lang.vhdl> On Fri, 25 Aug 2000 12:24:38 +0200, Jens Hildebrandt <hil@e-technik.uni-rostock.de> wrote: >Hello, > >I have a problem with the names Synopsys_1999.10 uses for multiple >instances of a component created using the VHDL "generate" construct. >For instance, when using a construct like > >for i in 0 to 7 generate > instance_name: component_name port map ( > ... > ); >end generate; > >eight instances of component_name would be created. Synopsys adds a >suffix to the instance_names to get different names for all instances. >Up to now I was used to this suffixes being sequential numbers (in most >cases equal i), but since updating to Synopsys_1999.10 these numbers >seem to have no relation to i but instead choosen according to some >hidden rule known only by Synopsys. >Does anyone out there know how to force Synopsys to use sequential >numbers as suffixes or a VHDL construct to define instance names as a >function of i? > >TIA > >Jens This code: G: for i in 1 to 2 generate comp: my_comp port map (...); end generate; should generate the names G(1).comp and G(2).comp in VHDL'93. The names are undefined in '87. That is, at least, the accepted wisdom, but I can't find this in the '93 LRM, and I'm sceptical. In any event, Synsopsys can do what it wants with the output netlist, which could include putting in arbitrary names, so I think you're on your own. EvanArticle: 25228
Steven, http://www.support.xilinx.com/xapp/xapp234.pdf Describes the Select Link (tm) interface, and other applications notes on the website explain how you can choose any one of 30 I/O standards (with memory cells) and any number of drive strengths (which allow you to do very wide custom buses without any resistors -- by using lvttl4 or lvtt6 whose output Z ~ 50 -60 ohms!!!). I would recommend using Hyperlynx, or some other SI tool, and using our IBIS models, and your PCB parameters, and modeling and choosing the best IO standard vs. drive strength vs. loading and lengths. Use the worst SI case: FAST/STRONG (coldest operating temperature, highest Vcc, fastest silicon) to make sure you are OK with the ringing, crosstalk, and so on. I have seen customer designs with multiple 72 bit busses operating at 155.52 MHz, multiple 128 bit busses, one or two 256 bit busses. The SDRAM applications notes are useful reading as their interfaces are operating at or near 200 MHz DDR for 400 Mb per pin. The 622 Mb/s DDR per pin app note is also a good read. Twelve io pins > 6.4 Gb/s ... people are doing it in Virtex E. The choices are yours, and the Virtex and Virtex E parts are versatile enough to make the bus you want, optimally. Resistors MAY be necessary due to the single driver, 8 load bus structure WITH ANY METHOD FROM ANY VENDOR. At least with Virtex you can spin your own drivers and strengths to compromise and reduce or eliminate the resistors. The SI engineering is required at such speeds, and must be done, and observation of all guidelines (SSO requirements in APP133) also must be observed. FAE's, and others are available to review your application, Austin Lesea IC Design Xilinx Steven DeLong wrote: > I have an application that requires the connection of a large amount of > I/O between multiple FPGAs on a single PCB. The application requires one > type of device to fan in/out to 8 each of a second type of device. Each > connection requires about 6.4 Gbit of bandwidth in each direction. > > One connection scheme could use two 32 bit buses (one bus in each > direction) between each of the eight devices and the one device. The bus > bits would each run at 200 Mb/s. That's 64 single ended > drivers/receivers on each of the eight devices and 512 single ended > drivers/receivers on the other device. > > Does anyone have any experience with anything similar to the above > and/or large amounts of high-speed interconnect between chips? What type > of I/O was used (LVTTL, LVDS, HSTTL, etc.) What, if any type of > terminations were used? Any other suggestions? > > I would like to avoid external terminations and reduce as much as > possible the number of physical routes between the devices because of > PCB real estate limitations.Article: 25229
On 31 Aug 2000 10:22:55 GMT, korthner@hotmail.nospam.com (K. Orthner) wrote: >Hi, Tomek. > >>Why after writing a synthesizable project we have to write in this way >>that latches was the least in the project. Latches are not synhesis >>efficient, if yes will tell me why? > >Most FPGA's don't have latches available for use. Usually FPGA's consist >of combinational logic element (Such as LUTs), and Flip-Flops. Xilinx 4kxla, among some other families, are the exception. They do support latches directly. > >It is possible to use a latch in your design, and it will synthesize, but >it's rather inefficient, because the synthesis tool "creates" the latch out >of normal logic elements. Some tools, or at least some versions of some tools (e.g., some previous Leonardo Spectrum versions) manage to not use the available latches and instead build them out of RAM elements or normal logic elements. > >Hope this helps. > >-Kent Jason Jason T. Wright Cygnion CorpArticle: 25230
My experiences over the last couple years on that very issue are why I'm running Leonardo Spectrum on the PC. (I'm also running the Xilinx back-end tools on the PC, which is about twice as fast as what I was seeing on the Sparc I was using. ModelSim on the PC is significantly faster that VSS was on the workstation for VHDL simulation.) Keep in mind, however, it could be partly that it was an old Sparc--i.e., not "state of the art." PCs have come a long way. Jason On Thu, 31 Aug 2000 06:42:06 GMT, Bill Lenihan <lenihan3weNOSPAM@earthlink.net> wrote: >I have a Verilog design I inherited that was developed in Xilinx >Foundation (takes about 1300 FFs, 1400 LUTs in virtex) and I notice that >Foundation synthesizes this (supposedly with Synopsys FPGA Express under >the hood) in about 2 minutes, but Synopsys FPGA Compiler II (on a Unix >Sun Ultra Sparc w/ 1 Gbyte of RAM) crashes when I synthesize the whole >design top-down ..... and synthesizes in 45 minutes (with errors) if I >do bottom-up synthesis. > >I thought FCII was supposed to be the state-of-the-art synthesis tool, >with more features than FE and the same 'engine' as FE. > >Any ideas why FCII would be performing so poorly compared to FE? >Are there special switches or settings that need to be turned on? > >-- >============================== >William Lenihan >lenihan3weNOSPAM@earthlink.net >============================== > > Jason T. Wright Cygnion CorpArticle: 25231
The Virtex family storage element can be configured as either an edge triggered flip flop or as a level sensitive latch. There are lots of good reasons to use latches instead of flipflops. These are, 1) The clock to out of a latch is not in the critical timing path as it is for a flip flop. This is not very important in the current generation of FPGAs because interconnect delays dominate the overall path delay. In the future this may change as the interconnect architectures are improved. 2) One stage of a pipe can effectively steal some time from another stage making it easier to meet timing. 3) Latch designs are less sensitive to clock skew than edge triggered designs, this is not that important in FPGAs where the clock is well controlled, it's very important in ASICs. 4) In ASICs a latch is half as expensive as a flip flop. In FPGAs the cost is the same. The principal disadvantage of a latch design is that the timing analysis is much harder. Josh "K. Orthner" wrote: > > Hi, Tomek. > > >Why after writing a synthesizable project we have to write in this way > >that latches was the least in the project. Latches are not synhesis > >efficient, if yes will tell me why? > > Most FPGA's don't have latches available for use. Usually FPGA's consist > of combinational logic element (Such as LUTs), and Flip-Flops. > > It is possible to use a latch in your design, and it will synthesize, but > it's rather inefficient, because the synthesis tool "creates" the latch out > of normal logic elements. > > Hope this helps. > > -KentArticle: 25232
In article <39A64966.36BD53E2@e-technik.uni-rostock.de>, Jens Hildebrandt <hil@e-technik.uni-rostock.de> writes: >Hello, > >I have a problem with the names Synopsys_1999.10 uses for multiple >instances of a component created using the VHDL "generate" construct. >For instance, when using a construct like > >for i in 0 to 7 generate > instance_name: component_name port map ( > ... > ); >end generate; <snipped> Hi Jens, Try posting the request in ESNUG:- > > ============================================================================ > Trying to figure out a Synopsys bug? Want to hear how 11,000+ other users > dealt with it? Then join the E-Mail Synopsys Users Group (ESNUG)! > > !!! "It's not a BUG, jcooley@world.std.com > /o o\ / it's a FEATURE!" (508) 429-4357 > ( > ) > \ - / - John Cooley, EDA & ASIC Design Consultant in Synopsys, > _] [_ Verilog, VHDL and numerous Design Methodologies. > > Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222 > Legal Disclaimer: "As always, anything said here is only opinion." > The complete, searchable ESNUG Archive Site is at http://www.DeepChip.com > ============================================================================ > > Here's how to subscribe or unsubscribe to the E-mail Synopsys Users Group > (ESNUG) mailing list via the > Majordomo listserver. > > Subscribe > > I use the majordomo list server. To subscribe to ESNUG send an e-mail: > > To: esnug-request@world.std.com > Subject: ESNUG admin > > subscribe esnug your@emailaddress > > For example, if your e-mail address was "josh@motorola.com" you'd send: > > To: esnug-request@world.std.com > Subject: ESNUG admin > > subscribe esnug josh@motorola.com > > and the computer AUTOMATICALLY adds you to the ESNUG mailing list. > > To post a letter/question/reply/opinion on the ESNUG newsletter, send it to > me at jcooley@world.std.com and, if it's a reply to a particular ESNUG Item, > please note that ESNUG and Item Number in your "Subject:" line. > -- Regards, Brent Hayhoe. Nortel Networks plc, Tel: +44 (0)1279-402937 Harlow Laboratories, London Road, Fax: +44 (0)1279-403930 Harlow, Essex, CM17 9NA, U.K. Email: hayhoe@nortelnetworks.comArticle: 25233
On Thu, 31 Aug 2000 10:57:22 GMT, eml@riverside-machines.com.NOSPAM wrote: ><cross-posted to comp.lang.vhdl> > >On Fri, 25 Aug 2000 12:24:38 +0200, Jens Hildebrandt ><hil@e-technik.uni-rostock.de> wrote: > >>Hello, >> >>I have a problem with the names Synopsys_1999.10 uses for multiple >>instances of a component created using the VHDL "generate" construct. >>For instance, when using a construct like >> >>for i in 0 to 7 generate >> instance_name: component_name port map ( >> ... >> ); >>end generate; >> >>eight instances of component_name would be created. Synopsys adds a >>suffix to the instance_names to get different names for all instances. >>Up to now I was used to this suffixes being sequential numbers (in most >>cases equal i), but since updating to Synopsys_1999.10 these numbers >>seem to have no relation to i but instead choosen according to some >>hidden rule known only by Synopsys. >>Does anyone out there know how to force Synopsys to use sequential >>numbers as suffixes or a VHDL construct to define instance names as a >>function of i? >> >>TIA >> >>Jens > >This code: > >G: for i in 1 to 2 generate > comp: my_comp port map (...); >end generate; > >should generate the names G(1).comp and G(2).comp in VHDL'93. The >names are undefined in '87. That is, at least, the accepted wisdom, >but I can't find this in the '93 LRM, and I'm sceptical. In any event, >Synsopsys can do what it wants with the output netlist, which could >include putting in arbitrary names, so I think you're on your own. > >Evan I had another look at the LRM, section 14.1, and the path_name attribute for 'comp' would be a string of the form "prefix:g(1):comp" and "prefix:g(2):comp", where 'prefix' gives the path down to G. However, a vendor wouldn't be obliged to use this in an output netlist. There's nothing you can do in the VHDL to change the naming convention. EvanArticle: 25234
you can download such a VHDL procedure implemented in C at http://www.model.com/support/technote/index.html (first technical note) I used is for Synopsys' VSS and works fine regards, Frank Van de Sande CDMA Asic engineer Sirius Communications http://www.siriuscomm.com "Paul Somogyi" <somogyi@ee.ualberta.ca> wrote in message news:8o7bsp$afk$1@pulp.srv.ualberta.ca... > Hello, > > I didn't see the previous responses to this post... so here's my 2 cents. > > It can be done with some simulators. I've used Cadence leapfrog/ncsim, > and looked at internal signals using the C library interface. If you're > using this simulator, start "openbook" and under the product guide will > be the C library interface. That documentation describes how to write a > shared library (Sun or HP) that the simulator can use. In particular, > you can write the implementation of a VHDL procedure in C. > > What you want to do only requires one function call from the C code into > the simulator: there is a call to propogate one signal onto another one; > these signals can be located anywhere in the design. So I just created > signals in my testbench of the same types as the internal signals, and > used this VHDL/C function call to "assign" the internal signals to the > testbench ones (note that you don't have any normal VHDL drivers for > the testbench signals). > > To do this purely in VHDL is impossible. > > Paul > > > Nestor (nestor@ece.concordia.ca) wrote: > > Hi Everyone. > > > Does anyone know how to access an internal signal or a port in VHDL when > > doing a simulation with a VHDL testbench? I have instantiated a block > > within my top level VHDL design and I would like to monitor some of its > > internal signals and some of its ports. My aim is to write the observed > > values to a file using a VHDL testbench since it will be easier for me to > > compare the results in a spreadsheet program. I am already able to write > > the inputs and outputs for the top level design instantiated as a > > unit-under-test (UUT) in the VHDL testbench (all the ports are visible and I > > can assign them to a signal that I declare in the testbench). > > > My problem is how to access signals internal to that UUT. I am able to > > access these internal signals within the simulator's graphical view, but I > > cannot export that information in a readable format using the simulator's > > menus. Is there a way to achieve what I want using the VHDL syntax directly > > within the VHDL testbench? > > > Thanks in advance for your help. > > > Nestor > >Article: 25235
On Tue, 29 Aug 2000 18:09:48 -0700, Andy Peters <@> wrote: > >Check in the FPGA Express constraints GUI, and make sure you didn't set >that attribute to FALSE there. Also, *never* forward-annotate timing >constraints from FPGA Express (that is, one of the FPGA Express options >is "Export Timing Constraints"). That puts lots of constraints into >your EDIF that don't need to be there, especially when most of your >constraints will be covered by a simple PERIOD attached to the clock. > You should try FPGA Express 3.4. Much improvement there, they create now a *.ncf file, and don't put the timing constraints in the edif file anymore. And, they use simple PERIOD statements in the ncf file. I define (most) timing constraints in fexp (in tcl, not in the GUI, of course), and I am quite satisfied. chm. -- cmautner@ - Christian Mautner mail.com - Vienna/Austria/EuropeArticle: 25236
On Thu, 31 Aug 2000 10:55:56 GMT, eml@riverside-machines.com.NOSPAM wrote: >While we're on make, does anyone know of a good Windows make? I use >gmake and the make shipped with VxWorks. The gmake DOS port is pretty >useless; it has problems with shells, changing directories, and so on. >The VxWorks one is better, but still has problems. I am happy with the cygnus tools (www.cygnus.com, now redhat), it contains not only make, but also bash and gzip and everything else you need to make your NT feel like a real computer. > >>[rest of dreaming snipped (but shared - I'd love to see embedded perl there, >>and NOT tcl)] > >Why not Tcl? > >Tcl: Spectrum, Synplify, DC, ModelSim, FPGA Express(?), Renoir(?) >Perl: Xilinx, Renoir(?) > >I get the impression that Tcl is now much more popular in EDA. Perl >may be better at text processing, but the last thing I want to do is >learn yet another language. > Sure, Tcl is more popular. But, as a language, it sucks. In contrary to Perl which just is perfect. Ever tried to do some programming (as opposed to scripting) in Tcl? Horrible. But that might be the EDA industry's idea, to prevent customers from shooting themselves in their feet. chm. -- cmautner@ - Christian Mautner mail.com - Vienna/Austria/EuropeArticle: 25237
It has been over 24 hours since I posted this and I have not seen it come back in the newsgroup, and hence am trying again. rickman wrote: > Neil Nelson wrote: > > > Another point I'd like to make obvious is how restricting a set of signed NDAs could > > > be at subsequent interviews. > > > > > > Q: "Well, I signed this one there, and this other one elsewhere. Do these NDA > > > documents screw me here?" > > > A: "Well, sign this NDA and I'll send these over to our corporate attorney and we'll > > > figure something out." > > > > > > Matt > > > > I am not having an easy time imagining how an NDA signed for the purposes of an > > interview at one company would cause a difficulty interviewing or signing an NDA > > (for the purposes of the interview) at another company. Do you have a fairly > > concrete example of how such a difficulty would come about? Typically at an > > interview you talk about your own skills and substantial experiences that would > > relate to the potential job. What company specific information someone might give > > to you at one interview would seem far afield of the information you are expected to > > provide about yourself at another interview. > > > > Regards, > > > > Neil Nelson > > The concern is not that you could not interview with other companies. > The concern is that by promising not to disclose information to others, > you may be limited as to what you can work on for a new company. > Certainly it is best if you don't have any restrictions. But just by > working on a similar product, you can provide the appearance that you > have disclosed information if the product ends up being very similar to > what the NDA covered. > > The worst possible scenario was what I encountered where the NDA covered > an unlimited range of information that was not identified. Then you have > no idea of what you should not discuss or possibly work on. > > I believe at least one post in this long thread gave an example of a > situation of an NDA preventing an engineer from working on a certain > project in the new company. The new company chose to prevent the > appearance of a violation of the NDA. Certainly you can see where this > can be a limiting factor to your career. It may not cost you a job, or > it won't get you fired, but it makes you less useful and flexible to > your employer. Matt's meaning then was that a job seeker had worked for several different companies (not just interviewed), each with an NDA such that when interviewing for a new job the total area of concern for these previous NDAs had the appearance (possibly substance) of covering areas of the new job. The one post you may be talking about in the last paragraph sounds like Jon's post where the result went against the NDA company's claim. I.e., the company thought the NDA applied, but it did not. In Jon's case the NDA was not the direct problem but rather it was the NDA company's interpretation of claims an NDA gave them that was the problem. Though this is an NDA related problem, it appears to be secondary, and not one we are directly concerned with. However, if it is a general concern, we perhaps need to note that it should have a different treatment. But the cumulative effect of NDAs as they reduce employment potential has at least the appearance of being a concern. Generally one is more employable with increasing experience as that experience is of the kind useful to a potential employer. E.g., if I had worked for Intel on new chip technology, I should be worth a fair amount to Advanced Micro Devices (AMD) who would have a similar interest. It would not be proper for Intel to restrict my employment potential by essentially removing the advantages of my experience, but Intel would want to restrict technical advantages it has that are relatively secret, that they have spent considerable resources on finding and developing from being handed to AMD on a silver platter. It would seem proper to notify the new company of existing NDA agreements a job seeker has, and hopefully has a copy of, if they think it is important. But I doubt any NDA requires you to notify the NDA company of who you may choose to work for, what the new company's business is, and certainly the new company has no agreement to tell any previous employer which of their prior employees they have hired. Balancing the interests between the NDA company and the prior employee (now a job seeker) could become difficult, but it seems to me that the job seeker is initially ahead in the potential of getting a good job as the NDA company would not normally know what the job seeker is doing, and a prior NDA is not in the interests of a new company and rather points to a class of skills that should be of interest to them--having been in a position to have an NDA at, say, Intel for their chip technology requires related non-NDA skills in the general area of chip technology. A generally worded NDA tends toward being ineffective in that the NDA company would need to show, if they were to make a subsequent claim against a prior employee, that the prior employee transferred company- specific information that was damaging to the NDA company. E.g., Intel could not require an NDA against chip technology in general and then enforce it because there are a large number of organizations involved in chip technology and much of chip technology is public domain. Such an NDA would need to be construed to covering specific Intel chip technology that if transferred would damage Intel, which requires Intel, if they were to make a claim, that specific chip technology was transferred by a specific individual, and that such a transfer was damaging to Intel. This will not be an easy case to make. It would be easier for an NDA company to make it worthwhile for employees to stay than attempting such a legal quagmire. But finally, I think we need a better concrete example that illustrates the suggested problem. Jon's example rather argues how _ineffective_ an NDA can be. Regards, Neil NelsonArticle: 25238
Thanks to Jason, Ben, and Joshua for correcting me; seems as though many FPGA families *do* support using latches directly (Although the tools may not.) -KentArticle: 25239
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"rickman" <spamgoeshere4@yahoo.com> wrote in message news:39AD09F8.FC6DBDB0@yahoo.com... > Or possibly the voltage. As you reduce the geometry, the power supply > voltage needs to decrease as well. Actually I would have preferred that > it be a 1.8 volt process to be compatible with some of the DSP chips I > would like to use. But these days the core voltages are all over the > map. TI has new chips that use 1.5, 1.6 and 1.8 volts. What difference > does 0.1 volts make??? > Rick Collins Aren't Pentium and Alpha chips "tuned" during wafer test to find the exact supply voltage at which they operate at the maximum possible frequency? This voltage is then encoded into 5 pins which connect to the external power supply control chip to program it to deliver the optimum voltage, between 1.3 and 3.5 volts in 50 mV increments. Sometimes I long for the days when everything ran at 5 volts. We now have some units in production with three different logic supply voltages, to cater to all the different chips. Luckily, power supply technology has become so good that it doesn't take much space or heat. But it still represents an extra source of EMI and single point failures. Maybe we'll all standardize again on 0.7 volts or so, in about 5 years. In the meantime, it's the pits... Tom Meagher ICS Triplex Houston TXArticle: 25241
Tom Meagher wrote: > > "rickman" <spamgoeshere4@yahoo.com> wrote in message > news:39AD09F8.FC6DBDB0@yahoo.com... > > Or possibly the voltage. As you reduce the geometry, the power supply > > voltage needs to decrease as well. Actually I would have preferred that > > it be a 1.8 volt process to be compatible with some of the DSP chips I > > would like to use. But these days the core voltages are all over the > > map. TI has new chips that use 1.5, 1.6 and 1.8 volts. What difference > > does 0.1 volts make??? > > Rick Collins > > Aren't Pentium and Alpha chips "tuned" during wafer test to find the exact > supply voltage at which they operate at the maximum possible frequency? > This voltage is then encoded into 5 pins which connect to the external power > supply control chip to program it to deliver the optimum voltage, between > 1.3 and 3.5 volts in 50 mV increments. > > Sometimes I long for the days when everything ran at 5 volts. We now have > some units in production with three different logic supply voltages, to > cater to all the different chips. Luckily, power supply technology has > become so good that it doesn't take much space or heat. But it still > represents an extra source of EMI and single point failures. > > Maybe we'll all standardize again on 0.7 volts or so, in about 5 years. In > the meantime, it's the pits... I have never heard that they are "tuned" since to the best of my knowledge all chips run faster at higher voltages. They pick a voltage that the chip will not self destruct at and try to keep it low to minimize power consumption. But I am pretty sure they don't alter it for each chip. They just pick a voltage for a given spin of the part and test them all at that voltage. The TI DSP chips seem to go for whatever voltage they feel like designing to that day. The TMS320VC33 uses 1.6 volts which is not any kind of a standard. To supply this voltage you have to use an adjustable regulator. -- Rick Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 25242
Hello, Why the code below is incorrect to synthesis for FPGA Express: always @(negedge CLK or posedge Write2CWR) if (Write2CWR) OUT=OUT_mode_after_CWR; else OUT=OUT_mode; Error during synthesis is: Sequential mapping has detected that the cell '/ver1-optimized/OUT_reg' uses both the asynchronous 'set' and 'clear' pins. What should I correct in this code? With regards Tomek T.Brychcy@ime.pz.zgora.plArticle: 25243
On Wed, 30 Aug 2000 15:23:34 -0700, Neil Nelson wrote: >rickman wrote: > >> Neil Nelson wrote: >> > > Another point I'd like to make obvious is how restricting a set of signed NDAs could >> > > be at subsequent interviews. >> > > >> > > Q: "Well, I signed this one there, and this other one elsewhere. Do these NDA >> > > documents screw me here?" >> > > A: "Well, sign this NDA and I'll send these over to our corporate attorney and we'll >> > > figure something out." >> > > >> > > Matt >> > >> > I am not having an easy time imagining how an NDA signed for the purposes of an >> > interview at one company would cause a difficulty interviewing or signing an NDA >> > (for the purposes of the interview) at another company. Do you have a fairly >> > concrete example of how such a difficulty would come about? Typically at an >> > interview you talk about your own skills and substantial experiences that would >> > relate to the potential job. What company specific information someone might give >> > to you at one interview would seem far afield of the information you are expected to >> > provide about yourself at another interview. >> > >> > Regards, >> > >> > Neil Nelson >> >> The concern is not that you could not interview with other companies. >> The concern is that by promising not to disclose information to others, >> you may be limited as to what you can work on for a new company. >> Certainly it is best if you don't have any restrictions. But just by >> working on a similar product, you can provide the appearance that you >> have disclosed information if the product ends up being very similar to >> what the NDA covered. >> >> The worst possible scenario was what I encountered where the NDA covered >> an unlimited range of information that was not identified. Then you have >> no idea of what you should not discuss or possibly work on. >> >> I believe at least one post in this long thread gave an example of a >> situation of an NDA preventing an engineer from working on a certain >> project in the new company. The new company chose to prevent the >> appearance of a violation of the NDA. Certainly you can see where this >> can be a limiting factor to your career. It may not cost you a job, or >> it won't get you fired, but it makes you less useful and flexible to >> your employer. > >Matt's meaning then was that a job seeker had worked for several different >companies (not just interviewed), each with an NDA such that when >interviewing for a new job the total area of concern for these previous NDAs >had the appearance (possibly substance) of covering areas of the new job. > >But finally, I think we need a better concrete example that illustrates the >suggested problem. Jon's example rather argues how _ineffective_ an NDA >can be. Neil, my point was exactly as understood by Rick. It was the idea of a accumulation of NDAs that prompted me to post my original suggestion. Suppose that one were to be interviewed at company "X" that made a device that really was quite unique. Because of the device's uniqueness, or the company's belief of its uniqueness, that person was asked to sign an NDA so that when he was given a tour of the facilities he would not be able to reveal what he had seen as an upcoming product. Well, a job-seeker should not put all his eggs into one basket; he should shop around. So, our person goes and visits another company and -- as the devil would have it -- they're working on a secret project too. The product this second company is readying for market is similar to the first company's. And because the interviewee must reveal the NDA to the second employer because he is interested in working for the second company, he may in the end not be hired because of the unwillingness of the second compnay to deal with legal issues. And, what if the NDA signed for the first company prohibits the interviewee from even revealing the purpose of the NDA? Such was my line of thought ... Really though, I'm burned out on this thread! I think beating a dead horse isn't going to get anything more said than that already has. This thread ought to be archived and made a resource for interviewers, and interviewees. Thanks, Matthew StabenArticle: 25244
I guess you meant functional simulation and not timing simulation (par is done...) when using Synplify you have to set the xc_props attribute(for details see support.xilinx.com). I have no idea how to avoid setting both (the attribute and the generic) to the init value. One strange thing is that XILINX whats a bit_vector for the simulation (generic) and a string for synthesis (attribute) - however when you initalize the RAM via attribute in your VHDL code, check the edif file - the ram content must appear in the file. As far as I know RAM inference is a special Synplify feature. I suggest to instantiate the RAMs as black box, because you avoid troubles when switching the synthesis tool (and synthesis is faster and RAM inference doesn't support all features of the RAMs....) Ciao ThomasArticle: 25245
Tomasz Brychcy wrote: > Hello, > > Why the code below is incorrect to synthesis for FPGA Express: > > always @(negedge CLK or posedge Write2CWR) > > if (Write2CWR) > OUT=OUT_mode_after_CWR; > else > OUT=OUT_mode; > > Error during synthesis is: > > Sequential mapping has detected that the cell '/ver1-optimized/OUT_reg' uses > both the asynchronous 'set' and 'clear' pins. > > What should I correct in this code? > > With regards > > Tomek > > T.Brychcy@ime.pz.zgora.pl Because in the Write2CWR set/reset branch of the ``if'' OUT is not being set to a constant.Article: 25246
Anybody know how can I run these tools - ahdl2blf, blifopt, etc. - from the command line ? The ISE GUI seems to use some strange object called exewrap to invoke them.Article: 25247
Matthew Staben wrote: > Neil, my point was exactly as understood by Rick. It was the idea of a accumulation > of NDAs that prompted me to post my original suggestion. Suppose that one were to be > interviewed at company "X" that made a device that really was quite unique. Because > of the device's uniqueness, or the company's belief of its uniqueness, that person was > asked to sign an NDA so that when he was given a tour of the facilities he would not > be able to reveal what he had seen as an upcoming product. Well, a job-seeker should > not put all his eggs into one basket; he should shop around. > So, our person goes and visits another company and -- as the devil would have it -- > they're working on a secret project too. The product this second company is > readying for market is similar to the first company's. And because the interviewee > must reveal the NDA to the second employer because he is interested in working for > the second company, he may in the end not be hired because of the unwillingness of > the second company to deal with legal issues. And, what if the NDA signed for the > first company prohibits the interviewee from even revealing the purpose of the NDA? Do these interview NDAs require you to say to other subsequent companies that you interview with that you have an NDA with a previously interviewed company? What I am saying here is that the purpose of an NDA is to not disclose company specific information of a substantial secret nature that in doing so would damage the NDA company. You may interview with Company A that has an NDA and manages to give you apparently secret information during the short time of the interview, but if you do not disclose it to Company B who is working on the same project, you have not violated the NDA. The primary reasons that I did not think we were talking about just interview NDAs were because: there would necessarily be a short opportunity to obtain useful NDA information, the ability of an NDA company to make effective their agreement would be very low, and easy defenses could be given by the job-seeker if somehow an NDA company made a claim against the job-seeker. Here is a possible defense: If being an NDA company, I tell with little useful reason a number of people my supposed secrets and then expect an NDA to protect my secrets, that would not be the expected behavior of a company trying to keep secrets. One keeps a secret by not telling as against telling everyone and then asking them to keep it a secret. If we all know, it is not a secret. Regards, Neil NelsonArticle: 25248
Hi Hannah; I've done a test design using 8 clocks, just because I wanted to see how they'd be handled. None of them used the global clock inputs. The clocks ran 8 simple 8-bit counters, and were able to run at ~300 MHz, according to the timing analysis (the constraint was for 100 MHz). This probably isn't representative of your design, so your mileage may vary. My only advice is that you plan the design such that your clock inputs will be near the bulk of the logic that they will be gating. That should help minimize clock skew. Cheers, Jamie "Hanna Bruno" <hbruno@tellium.com> wrote in message news:39AD1C81.965A0D6E@tellium.com... > Hi, > > Has anyone used more than 4 clocks in the virtex. If so did you have any > problems using the secondary global routing resources. I have used up all > the 4 global buffers and have to use another clock for part of my design. > > Thanks, > Hannah >Article: 25249
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