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Messages from 25450

Article: 25450
Subject: Re: Numerically-Controlled Crystal Oscillator (NCXO) or Digitally-Controlled Crystal Oscillator (DCXO) Designs
From: "doug" <doug@hogg.com>
Date: Mon, 11 Sep 2000 20:36:52 -0700
Links: << >>  << T >>  << A >>
Filters are a bad idea except under very special conditions.  You need
to have a fixed frequency and that frequency needs to be in a special
relationship with the clock.  If you are near a binary divisor of the clock
frequency, the jitter will produce sidebands too near the carrier to be
removed by any filter that makes reasonable sense.  The D/A makes
a tuneable filter and it works well.
I did extensive computer simulations of this when I made all digital plls
nearly 20 years ago (probably long predating any patents on the obvious
idea) and found that with a careful choice of frequency, the spurs could
be avoided in some small range.  However, making a broad range source
did not justify the effort to try to skip the D/A.  Sine lookup table are
not
necessary.
Companies like Analog Devices have made the discussion moot with their
line of cheap and versatile DDCs.  They work very well and are easy to use
and do not require much in the way of external parts.


"Austin Lesea" <austin.lesea@xilinx.com> wrote in message
news:39BD6DE1.2F8CC8DC@xilinx.com...
> You are correct in stating that a filter is required to reduce jitter,
>
> A bandpass filter with high Q is what is needed.  The PLL with VCXO has a
Q of
> millions.  A good tank circuit works also, but less well (Q ~100).
>
> Guess what happens when you put the square wave MSB) into the same band
pass
> filter?  Pop: out comes the fundamental (for less money).
>
> I always get a kick out of all of those expensive sine wave lookups tables
and
> A/D's doing nothing.
>
> If a low Q filter is used, there is some tiny improvement in the lookup
table
> conversion method due to the sideband power not adding to the overall
phase
> noise.
>
> Don't take my word for it, use a good spectrum analyzer to analyze the
sidebands
> at each point in the circuit.  Take out the D/A and see what changes.  It
> usually makes the jitter less because of D/A noise issues, reference nosie
> issues, and comparator noise issues.
>
> "The common wisdom is neither common, nor wise." anon.
>
> Austin
>
> rickman wrote:
>
> > You are not totally correct Austin. If you want a square wave without a
> > lot of jitter, then you do need the sine wave which can be filtered to
> > produce a wave of just the fundamental. This is then compared to a fixed
> > voltage to produce a square wave with no jitter.
> >
> > If you don't do this, you will have a time jitter equal to your master
> > clock period as you noted. This is often not acceptable and the sine
> > wave lookup, DAC and filter can be less circuitry than the VCXO, phase
> > comparator and filter. In fact you can get the whole shebang in one chip
> > less the filter.
> >
> > Austin Lesea wrote:
> > >
> > > Nestor,
> > >
> > > A DDFS (direct digital frequency synthesizer) is an adder/accumulator.
> > > They have been around for perhaps 30 years now.  I have used them for
> > > years in FPGAs.  The sine look up table is only used if you want a
sine
> > > wave.  I have seen people use a sine look up table, a D/A, and then
follow
> > > that mess with a comparator -- TO GET A SQUARE WAVE!  Think about it.
The
> > > MSB of the DDFS was already the signal they wanted!
> > >
> > > So, if you don't want a sine wave, don't add all that junk.
> > >
> > > The p-p jitter is the clock period used, and the Fout < 1/2 Fclock.
> > >
> > > I would use the highest frequency I could get away with.  If you
require
> > > even less jitter, the output can be passed through a single simple
VCXO
> > > used in a PLL loop with an XOR phase detector and an external RC to
remove
> > > practically all of the jitter if the frequency output range is narrow
> > > enough.
> > >
> > > Placing the DDFS in a locked loop, results in a complete digital
locked
> > > loop (Patented -- look it up, under my name).
> > >
> > > There are many nice parts out there that package the whole thing, and
are
> > > inexpensive, so you need to evaluate what it is going to be used for,
and
> > > decide if you want to build it in, or not.
> > >
> > > Also look at:
> > >
> > >  http://www.xilinx.com/xcell/xl31/xl31_32.pdf
> > >
> > > for fractional synthesis,and other NCO's.
> > >
> > > Austin Lesea
> > >
> > > Nestor wrote:
> > >
> > > > Hi.
> > > >
> > > > Does anyone know any manufacturer who fabricates
> > > > numerically-controlled crystal oscillators (NCXO), also known as
> > > > digitally-controlled crystal oscillators (DCXO) which are suitable
for
> > > > digital phase-locked loop designs in VHDL and FPGAs?
> > > >
> > > > Although these blocks resemble a numerically-controlled oscillator
> > > > (NCO), they differ in that the NCXO is not oversampled to generate
the
> > > > required output signal (an NCO needs to be oversampled by at least
> > > > 8-times in order to have an acceptable low jitter output).  Rather,
a
> > > > digital input word is fed to the NCXO and it synthesizes the
required
> > > > output frequency using a standard, low-cost crystal oscillator.  The
> > > > output is also a square wave, just like the standard crystal.  In
> > > > general, the NCXO has a narrow tuning range similar to a
> > > > voltage-controlled crystal oscillator (VCXO), e.g. +/-150ppm
relative
> > > > to a frequency in the MHz range.
> > > >
> > > > The NCXO technology is fairly recent from what I understand, but
> > > > allows one to replace a circuit composed of a digital-to-analog
> > > > converter (DAC) and a VCXO by one chip that performs the exact same
> > > > task will less design hassles.  The DCXO is ideal for custom-made
> > > > phase-locked loop (PLL) circuits using digital sections that can be
> > > > implemented in VHDL and FPGAs.
> > > >
> > > > Since I haven't been able to find any NCXO manufacturers over the
web,
> > > > I am now looking to the knowledgeable engineers, designers and
friends
> > > > that frequent these newsgroups for some potential referrals and/or
> > > > links.
> > > >
> > > > Thanks in advance for your help.
> > > >
> > > > Nestor
> >
> > --
> >
> > Rick Collins
> >
> > rick.collins@XYarius.com
> >
> > Ignore the reply address. To email me use the above address with the XY
> > removed.
> >
> > Arius - A Signal Processing Solutions Company
> > Specializing in DSP and FPGA design
> >
> > Arius
> > 4 King Ave
> > Frederick, MD 21701-3110
> > 301-682-7772 Voice
> > 301-682-7666 FAX
> >
> > Internet URL http://www.arius.com
>


Article: 25451
Subject: Re: Numerically-Controlled Crystal Oscillator (NCXO) or
From: rickman <spamgoeshere4@yahoo.com>
Date: Mon, 11 Sep 2000 23:41:04 -0400
Links: << >>  << T >>  << A >>
Except that for an NCO sine wave, you don't need a band pass filter at
the frequency of the signal, you use a low pass filter below the Nyquist
rate at the DAC. The goal is not to try to remove the 'jitter' noise
that was added by the fixed sample clock, but rather to eliminate the
aliased spectrum above the Nyquist rate. 

The end result is that you can use the same circuit for multiple
frequencies and normally have a simpler and smaller filter. 

So I can't say what would happen if you passed the MSB through the same
filter as it may do relatively little to remove the 'jitter'. But even
if you use the more complex bandpass filter and are left with the
fundamental, wouldn't that be a sine wave which will require a
comparator to shape it back into a low jitter square wave putting back
some of the noise you are referring to? 



Austin Lesea wrote:
> 
> You are correct in stating that a filter is required to reduce jitter,
> 
> A bandpass filter with high Q is what is needed.  The PLL with VCXO has a Q of
> millions.  A good tank circuit works also, but less well (Q ~100).
> 
> Guess what happens when you put the square wave MSB) into the same band pass
> filter?  Pop: out comes the fundamental (for less money).
> 
> I always get a kick out of all of those expensive sine wave lookups tables and
> A/D's doing nothing.
> 
> If a low Q filter is used, there is some tiny improvement in the lookup table
> conversion method due to the sideband power not adding to the overall phase
> noise.
> 
> Don't take my word for it, use a good spectrum analyzer to analyze the sidebands
> at each point in the circuit.  Take out the D/A and see what changes.  It
> usually makes the jitter less because of D/A noise issues, reference nosie
> issues, and comparator noise issues.
> 
> "The common wisdom is neither common, nor wise." anon.
> 
> Austin
> 
> rickman wrote:
> 
> > You are not totally correct Austin. If you want a square wave without a
> > lot of jitter, then you do need the sine wave which can be filtered to
> > produce a wave of just the fundamental. This is then compared to a fixed
> > voltage to produce a square wave with no jitter.
> >
> > If you don't do this, you will have a time jitter equal to your master
> > clock period as you noted. This is often not acceptable and the sine
> > wave lookup, DAC and filter can be less circuitry than the VCXO, phase
> > comparator and filter. In fact you can get the whole shebang in one chip
> > less the filter.
> >
> > Austin Lesea wrote:
> > >
> > > Nestor,
> > >
> > > A DDFS (direct digital frequency synthesizer) is an adder/accumulator.
> > > They have been around for perhaps 30 years now.  I have used them for
> > > years in FPGAs.  The sine look up table is only used if you want a sine
> > > wave.  I have seen people use a sine look up table, a D/A, and then follow
> > > that mess with a comparator -- TO GET A SQUARE WAVE!  Think about it.  The
> > > MSB of the DDFS was already the signal they wanted!
> > >
> > > So, if you don't want a sine wave, don't add all that junk.
> > >
> > > The p-p jitter is the clock period used, and the Fout < 1/2 Fclock.
> > >
> > > I would use the highest frequency I could get away with.  If you require
> > > even less jitter, the output can be passed through a single simple VCXO
> > > used in a PLL loop with an XOR phase detector and an external RC to remove
> > > practically all of the jitter if the frequency output range is narrow
> > > enough.
> > >
> > > Placing the DDFS in a locked loop, results in a complete digital locked
> > > loop (Patented -- look it up, under my name).
> > >
> > > There are many nice parts out there that package the whole thing, and are
> > > inexpensive, so you need to evaluate what it is going to be used for, and
> > > decide if you want to build it in, or not.
> > >
> > > Also look at:
> > >
> > >  http://www.xilinx.com/xcell/xl31/xl31_32.pdf
> > >
> > > for fractional synthesis,and other NCO's.
> > >
> > > Austin Lesea
> > >
> > > Nestor wrote:
> > >
> > > > Hi.
> > > >
> > > > Does anyone know any manufacturer who fabricates
> > > > numerically-controlled crystal oscillators (NCXO), also known as
> > > > digitally-controlled crystal oscillators (DCXO) which are suitable for
> > > > digital phase-locked loop designs in VHDL and FPGAs?
> > > >
> > > > Although these blocks resemble a numerically-controlled oscillator
> > > > (NCO), they differ in that the NCXO is not oversampled to generate the
> > > > required output signal (an NCO needs to be oversampled by at least
> > > > 8-times in order to have an acceptable low jitter output).  Rather, a
> > > > digital input word is fed to the NCXO and it synthesizes the required
> > > > output frequency using a standard, low-cost crystal oscillator.  The
> > > > output is also a square wave, just like the standard crystal.  In
> > > > general, the NCXO has a narrow tuning range similar to a
> > > > voltage-controlled crystal oscillator (VCXO), e.g. +/-150ppm relative
> > > > to a frequency in the MHz range.
> > > >
> > > > The NCXO technology is fairly recent from what I understand, but
> > > > allows one to replace a circuit composed of a digital-to-analog
> > > > converter (DAC) and a VCXO by one chip that performs the exact same
> > > > task will less design hassles.  The DCXO is ideal for custom-made
> > > > phase-locked loop (PLL) circuits using digital sections that can be
> > > > implemented in VHDL and FPGAs.
> > > >
> > > > Since I haven't been able to find any NCXO manufacturers over the web,
> > > > I am now looking to the knowledgeable engineers, designers and friends
> > > > that frequent these newsgroups for some potential referrals and/or
> > > > links.
> > > >
> > > > Thanks in advance for your help.
> > > >
> > > > Nestor
> >
> > --
> >
> > Rick Collins
> >
> > rick.collins@XYarius.com
> >
> > Ignore the reply address. To email me use the above address with the XY
> > removed.
> >
> > Arius - A Signal Processing Solutions Company
> > Specializing in DSP and FPGA design
> >
> > Arius
> > 4 King Ave
> > Frederick, MD 21701-3110
> > 301-682-7772 Voice
> > 301-682-7666 FAX
> >
> > Internet URL http://www.arius.com

-- 

Rick Collins

rick.collins@XYarius.com

Ignore the reply address. To email me use the above address with the XY
removed.



Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX

Internet URL http://www.arius.com
Article: 25452
Subject: computing difference between Gray values?
From: wzjohn@my-deja.com
Date: Tue, 12 Sep 2000 07:47:09 GMT
Links: << >>  << T >>  << A >>
Hi,

I've searched on deja for help but have to resort to posting:

What is the cheapest way to determine the difference between two gray-
coded values?  My application is a FIFO with different input and output
clocks.  I would like to know approximately how full the FIFO is at any
time:  this information is needed in the faster clock domain.

Or am I on the wrong track?

TIA,

wzjohn


Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 25453
Subject: Re: Clock skew in XILINX CPLD
From: "Pinhas Krengel" <bknpk@hotmail.com>
Date: Tue, 12 Sep 2000 00:55:07 -0700
Links: << >>  << T >>  << A >>
It is certainly scary. I don&#8217;t know about XILINX PLD devices. For FPGA devices, they write in application notes that there are no hold problems inside the chip. 
I don&#8217;t see how the _/- can solve a problem.
Do you have the post layout net-list (VHDL+SDF) before and after.
There is another issue with PLD devices that may be worth mentioning. Due to loading issues (very high fan-out nets) the fitter duplicates registers. They may reside in different blocks and have different timing. If timing is not met, some will work and some will go south. This is difficult to notice in the lab (a single FF failure will cause the system to malfunction differently than you would expect in RTL simulation should this very FF fail).
Article: 25454
Subject: Re: Clock skew in XILINX CPLD
From: falk@iee.et.tu-dresden.de (Thomas Falk )
Date: 12 Sep 2000 08:03:52 GMT
Links: << >>  << T >>  << A >>
Hi John,

and thanks for your experiences.

In article <39BD2DA3.D306E852@visicom.com>,
	"John L. Smith" <jsmith@visicom.com> writes:
>    We had exactly your problem (XC9500 circuit behaviour changed
> depending on inclusion of test points), but did not run timing
> simulation, assumed that using the global clock guaranteed no
> skew problems. (Why else would the part include global clocks
> if this is not the case?!!?!)
> 

I don't have answer from XILINX yet, but the design runs now just by 
changing the implementation options from 'Balanced' to 'Area' in the
design manager. 

Nonetheless the problem still stands and I will have an eye on it. For
the simulation I have used the simple siluator in the XILINX Foundation 
Framework. It showed the error clearly, but no way to prevent it.

The clock was routed to the global net GCK1 and the global clock 
optimisation was on. Not very satisfying.

There may be a strategy to prevent such nasty things using time constraints
on the critical nets, but there I'm missing the insight yet. 

Perhaps somebody may share his experiences?

Thanks,

Thomas
Article: 25455
Subject: Re: Clock skew in XILINX CPLD
From: falk@iee.et.tu-dresden.de (Thomas Falk )
Date: 12 Sep 2000 08:08:23 GMT
Links: << >>  << T >>  << A >>
Hi Rick,

I have checked it, the clock is mapped on GCK1
and the clock optimisation is on. Arghl.

I will have to check for the setup times, but at least the 
system is working now simply by changing the implementation options 
from 'Balanced' to 'Area'.

It is not very satisfying, I will have to look further into it.


Thanks for your help,

Thomas

In article <39BD6297.121188A1@algor.co.uk>,
	Rick Filipkiewicz <rick@algor.co.uk> writes:
> There's just one remote possibility that although you have your 
> clock connected
> to a global clock input the fitter isn't actually using the global 
> routing. You
> need to check at the fitting
> report to see if there's a line likek
> 
> Signall ``fooclk'' mapped onto global clock net GCK<n>
> 
> and this at the end
> 
> Global (GCLK) optimisation       :ON
> Also one other thing - a really unlucky setup time violation can 
> look like a hold
> time one if the Tco delay is just greater than a clock period.
Article: 25456
Subject: Re: Clock skew in XILINX CPLD
From: Klaus Falser <kfalser@durst.it>
Date: Tue, 12 Sep 2000 08:11:12 GMT
Links: << >>  << T >>  << A >>
In article <8pgf7q$kea$1@rks1.urz.tu-dresden.de>,
  falk@iee.et.tu-dresden.de (Thomas Falk ) wrote:
> Hi Everyone!
>
> I'm having a problem in a fully synchronous design in a XILINX
XC95108-10
> CPLD using the schematic entry. All Registers in the design are
driven by
> one clock over GCK1.
>
> The problems are spurious errors which depended on the existence of
test
> connections from the inner circuit connections to a pad. With the
> connections it workes, without not.
>
> Using the timing simulation I have narrowed down the problem to a hold
> violation on some of the D-FF. The simulation shows that in a simple
shift
> register structure containing two D-FF, the second one will not take
the
> right value, if the second one changes its output. It seems, the
clock of
> second D-FF is too late regarding the change of the data at the
output of
> the first D-FF, even if both D-FF are clocked by the same single via
> GCK1. From my point of view the same situation is given in each
> synchronous counter, ands that makes me a bit scary.
>
> I'm not sure how to handle this situation and have the following
questions:
> - In the beginning this design was not completely synchronous. After
the
>   first appearance of these problems I changed it to a complete
>   synchronous one, but as it seems, the situation got worse. Is it
better
>   to do such a design not completely in synchronous logic?
> - Is it possible to split up the clock net? One reason for the
problems
>   may be a high load on the clock net GCK1.
>
> Generally I would also like to know if there is a systematic way to
deal
> with such problems or to prevent their appearance.
>
> Thanks for any answer,
>
> Thomas Falk
>
>

Did you use timing constraints?
If your design is completely synchronous a single PERIOD statement in
your UCF-file like the following should be enough.

NET <clockname> PERIOD = 15 ns ;

Personally I doubt a little bit about your timing simulation, since
until now I never noticed any modelling of clock skew and/or loading
of the clock lines for a XC9500.
If you have two FF in sequence the output of the first reaches the
second only after about 6-7 ns (XC95108-10).
With setup time=2.5 ns and hold time = 3.5 ns this leaves a lot of
room for clock skew.
I agree, this is are the maximum delay values taken from the data
sheet and the the minimum values are missing, so it is impossible to
estimate how much clock skew is allowed.
But you can be shure that Xilinx grants the clock skew somehow by
design, otherwise (as you say in your posting) not even the simplest
counter would work correctly.

I would
a) add the timing constraint at mentioned above
b) check the equations with and without testpoints. Maybe something has
been optimized away.
c) try to disable Local feedback and pin feedback. Once there were
an error related to this features.
d) try a different fitter (some older or newer version of Webpack)

Greetings
   Klaus


--
Klaus Falser
Durst Phototechnik AG
I-39042 Brixen


Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 25457
Subject: Re: hardware compatibility and patent infringement
From: Peter Hanely <hanelyp@no-spam.calweb.com>
Date: Tue, 12 Sep 2000 09:15:35 +0100
Links: << >>  << T >>  << A >>
ABP wrote:

> Hi,
>
> I need some "light" on "hardware compatibility and patent infringement".
> Since Transmeta presented his Crusoe chip I've had a few doubts about
> this issue. I would much appreciate any information on the following
> points you could give:
>
> 1. Is Transmeta's SOFTWARE approach to the manipulation of x86
> instructions set what avoids the violation of patents' rights? If that's
> right, I understand that patent infringement is only possible when there
> is a hardware implementation.
>
> 2. In general (for any kind of processor), What's the way to design a
> hardware device compatible with the instruction set of another processor
> without infringement of patents?
>
> 3. If someone implements a processor compatible with the instruction set
> of another processor but without copying anyting else from that original
> processor
> a part from the original instruction set, will that be patent
> infringement?
>
> Although I've been looking quite thoroughly on the web for information
> on patents for electronics design (the technical side of the subject)
> I've had little success. Can anyone, please, point me to a good source
> of information on this subject.
>
> Thank you all very much for your time.
>
> A. Petit

My impression is that you can't patent an instruction set.  Then again,
a lot of patents have been granted that are plain stupid.
In your favor, there are several Intel clone chips, that Intel would love
to shut down if they could.

The implimentation of an instruction set probably can be patented.


Article: 25458
Subject: CPLD: Basic informations
From: "Mostafa Halas" <mos_halas@yahoo.com>
Date: Tue, 12 Sep 2000 01:49:15 -0700
Links: << >>  << T >>  << A >>
Hi,i want to know the number of registers and system gates for various CPLD products.
thanks
Article: 25459
Subject: Re: CPLD: Basic informations
From: "Mostafa Halas" <mos_halas@yahoo.com>
Date: Tue, 12 Sep 2000 01:50:30 -0700
Links: << >>  << T >>  << A >>
Hi,i want to know the number of registers and system gates for various CPLD products.
thanks
Article: 25460
Subject: OUTs after synthesis?
From: "Tomasz Brychcy" <T.Brychcy@pz.zgora.pl>
Date: Tue, 12 Sep 2000 11:14:58 +0200
Links: << >>  << T >>  << A >>
Hello,

I have a synthesizable model. What are initialized outputs of model after
synthesis?

My model consists a three outputs OUT0 OUT1 OUT2. When i simulate model
before synthesis outputs go to known state in right time (outputs are
initialized unknown state) and when i simulate model after synthesis outputs
go to known state from beginning of simulation. Results of simulation of
model before synthesis i write in to file (it's a pattern file). So file
with results of model after synthesis never will be the same as pattern file
before synthesis because outputs are different initialized before and after
synthesis (in simulation), it's truth?

With regards

Tomek

--
Department of Electrical Metrology
Technical University of Zielona Gora

T.Brychcy@ime.pz.zgora.pl



Article: 25461
Subject: Simulation problem
From: "Tomasz Brychcy" <T.Brychcy@pz.zgora.pl>
Date: Tue, 12 Sep 2000 11:24:33 +0200
Links: << >>  << T >>  << A >>
Hello,

Simulation of model before synthesis is correct. When i simulate the same
model but after synthesis during simulation in MTI 5.2c occur the problem:

iteration limit reached. Possilbe zero delay oscillation.

I do not know what do?

Please about help

I attach files:

file before synthesis: controllogic(synth).v
file after synthesis: controllogic.v
testbench: tb_controllogic.v

P.S I know that the problem occur exactly when signal ReadCn goes to high
state.

Tomek

--
Department of Electrical Metrology
Technical University of Zielona Gora

T.Brychcy@ime.pz.zgora.pl



Article: 25462
Subject: Accessing internal signals and ports for writing to a file using
From: Charles Gardiner <charles.gardiner@mchr2.siemens.de>
Date: Tue, 12 Sep 2000 11:46:45 +0200
Links: << >>  << T >>  << A >>
You can also do it in VHDL using an intermediate Package.

Library  IEEE;
Use IEEE.std_ logic_1164.all;
Package TracePkg
	signal test_point_1 : std_logic;
End TracePkg;

--	--	--	--

Library  IEEE;
Use IEEE.std_ logic_1164.all;
Use WORK.TracePkg;
Architecture Bhv of DUT
   signal signal_name_1	: std_logic;
begin
   TracePkg.test_point_1 <= signal_name_1;
end Bhv;

--	--	--	--

Library  IEEE;
Use IEEE.std_ logic_1164.all;
Use WORK.TracePkg;
Architecture Bhv of DUT_Testbench
  signal test_point_1 : std_logic;
begin
  test_point_1 <= TracePkg.test_point_1;

  I_DUT : DUT
      Port Map (
   etc.... 
End Bhv;

-- 
Charles Gardiner, B.E.
Program Manager, Silicon IP
Siemens AG
Dept: ATD IT PS 8 Mch
Otto-Hahn-Ring 6
D-81730 Muenchen

Email: mailto:charles.gardiner@mchr2.siemens.de
Phone: Office +49 89/636 42969, Mobile (0)171/867 2732
Fax  : Office +49 89/636 44595

Homepage    : http://eda-services.atd.siemens.de/gardiner (Siemens
Intranet only)
ATD Homepage: http://www.atd.siemens.de/it-dl/eda
Article: 25463
Subject: unexpanded XU macros
From: Charles Wagner <Charles.Wagner@irisa.fr>
Date: Tue, 12 Sep 2000 12:05:06 +0200
Links: << >>  << T >>  << A >>
When implementing a design in Xilinx Design Manager (M2.1), using an
EDIF netlist as input,  during design expansion  :
<< logical block "I0/I21/I2" of type "M2_1" is unexpanded.

M2_1 is a macro defined in the Xilinx Unified library.
Where are the netlist files for the XU macros defined ?

Thanks for your help,
Charles
Article: 25464
Subject: Odp: Simulation problem (attached files)
From: "Tomasz Brychcy" <T.Brychcy@pz.zgora.pl>
Date: Tue, 12 Sep 2000 12:05:20 +0200
Links: << >>  << T >>  << A >>
I apologize, I have forgotten attach the files to last letter. The file are
here in attachment

Tomek

--
Department of Electrical Metrology
Technical University of Zielona Gora

T.Brychcy@ime.pz.zgora.pl

Użytkownik Tomasz Brychcy <T.Brychcy@pz.zgora.pl> w wiadomości do grup
dyskusyjnych napisał:8pksot$9gl$1@okapi.ict.pwr.wroc.pl...
> Hello,
>
> Simulation of model before synthesis is correct. When i simulate the same
> model but after synthesis during simulation in MTI 5.2c occur the problem:
>
> iteration limit reached. Possilbe zero delay oscillation.
>
> I do not know what do?
>
> Please about help
>
> I attach files:
>
> file before synthesis: controllogic(synth).v
> file after synthesis: controllogic.v
> testbench: tb_controllogic.v
>
> P.S I know that the problem occur exactly when signal ReadCn goes to high
> state.
>
> Tomek
>
> --
> Department of Electrical Metrology
> Technical University of Zielona Gora
>
> T.Brychcy@ime.pz.zgora.pl
>
>
>


begin 666 tb_controllogic.v
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M+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2U$14-,05)!5$E/3B!O
M9B!)3E!55%,M+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM
M+2TM+0T*#0H-"G)E9R!;-SHP72!$7TE..PT*<F5G($=!5$4[#0IR96<@0TQ+
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M1#L-"G)E9R!#,%\P+"!#,%\Q+"!#,%\R+"!#,S(Q7S [#0IR96<@5W)I=&4R
M0VXL(%=R:71E,D-74CL-"G)E9R!296%D0VX[#0IR96<@0T]$13L-"G)E9R!2
M0CL)"0DO+U)E860@0F%C:PT*<F5G(%LR.C!=($U/1$4[#0IR96<@6S$Z,%T@
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M"@T*#0HO+RTM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2U$14-,
M05)!5$E/3B!O9B!/55105513+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM
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`
end

begin 666 ControlLogic.v
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`
end

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`
end

Article: 25465
Subject: Is this practical?
From: Michael Warner <mvw@ozemail.com.au>
Date: Tue, 12 Sep 2000 20:12:00 +0930
Links: << >>  << T >>  << A >>
Hi folks,

I've never used an FPGA, but I have a problem to which they may
provide the answer: I need to generate 64 simultaneous high-speed
8-bit PWM signals under micro control; space is at a premium.

Imagining it in plain logic, I'd have 64 8-bit latches loaded by data
& address buses. Each latch would pre-load an 8-bit counter on each
PWM cycle. The counters would count down, latching themselves at zero
- these latch signals would be the PWM outputs.

Is this practical to attempt in a single device? If so, any
recommendations of families suited to such a task would be
appreciated.

Thanks!
Article: 25466
Subject: Re: Is this practical?
From: korthner@hotmail.nospam.com (K. Orthner)
Date: 12 Sep 2000 11:29:54 GMT
Links: << >>  << T >>  << A >>
Hi, Michael.

It would be rather straight forward to implement your 64xPWM's in an FPGA. 

I/O Pin count (This is a bare minimum):  
  64 PWM O/P
  8  CPU I/O
  8  CPU Address
  3  CPU Control
  1  Clock
 ---
  84 pins minimum.  

So you could use a single TQ144 or PQ208 package.
That ought to be okay space-wise.  Add a 8-pin DIP PROM for programming, or 
program it with your micro.

>Is this practical to attempt in a single device? If so, any
>recommendations of families suited to such a task would be
>appreciated.

I know Xilinx well, so I would lean towards their Spartan-II family.  It's 
powerful, and it's cheap.  And, you could take advantage of the RAM blocks 
to fit it into one of the smaller members of the family.  (Look at the 
Spartan-II XC2S30).  Although some people seem to be having problems 
actually getting parts.

This sounds like a fun project, so if you like, I'll even volunteer to do 
the FPGA for you, if you give me a bit more details.

Kent
korthner@hotmail.nospam.com
Article: 25467
Subject: MEMORY
From: "psisabel" <psisabel@mii.zaz.com.br>
Date: Tue, 12 Sep 2000 08:39:01 -0300
Links: << >>  << T >>  << A >>
Somebody would have a schematic of memory ram or salary so that I can
accomplish a project

I thank

Failures




Article: 25468
Subject: Re: Is this practical?
From: Ray Andraka <ray@andraka.com>
Date: Tue, 12 Sep 2000 11:59:31 GMT
Links: << >>  << T >>  << A >>
what is the available clock and required sample rate?  If you can supply a
multiplied clock, you can reduce the size of the logic substantially.  That
said, the brute force design will need 2 luts per bit plus the control logic, so
with careful layout you could get it into a 4013/XCS30.  If you go with Virtex,
you'll ned an XCV50 or larger device to fit the brute force design.

Michael Warner wrote:
> 
> Hi folks,
> 
> I've never used an FPGA, but I have a problem to which they may
> provide the answer: I need to generate 64 simultaneous high-speed
> 8-bit PWM signals under micro control; space is at a premium.
> 
> Imagining it in plain logic, I'd have 64 8-bit latches loaded by data
> & address buses. Each latch would pre-load an 8-bit counter on each
> PWM cycle. The counters would count down, latching themselves at zero
> - these latch signals would be the PWM outputs.
> 
> Is this practical to attempt in a single device? If so, any
> recommendations of families suited to such a task would be
> appreciated.
> 
> Thanks!

-- 
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com  or http://www.fpga-guru.com
Article: 25469
Subject: Anybody receiving Spartan II?
From: Jerry English <jenglish@planetc.com>
Date: Tue, 12 Sep 2000 08:24:30 -0400
Links: << >>  << T >>  << A >>
We are looking at using a spartan II xc2s150 in a new design. Our
distributor is telling us Xilinx says 17 weeks delivery. Has anybody
received these parts in large quantities (1000 pc) and if so what was
your lead time? When I ask the distributor if the lead time can be
improved the response is "Place the order then we will work the problem"

Well why can't they tell me what the delivery time is for other orders?

Oh yes, I did search deja for this question and it was asked. I
followed
the thread but nobody mentioned actually receiving these parts.

I must say the new 3.1 release is fast. The verilog compiler is pretty
good also. Did find a construct it couldn't handle but that's a subject
for another thread.

regards
Jerry



Article: 25470
Subject: Re: Is this practical?
From: kolja@prowokulta.org
Date: Tue, 12 Sep 2000 12:39:54 GMT
Links: << >>  << T >>  << A >>
For many applications where a PWM is used a Delta-Sigma DAC gets even
better results. There is a Xilinx applications note XAPP154 on how to do
a 8-Bit S-D DAC in 10 LUTs plus 17 Registers => 9 Slices
This would result in 567+epsilon Slices and would fit in a XC2S50.

If all the PWMs are synchronous (They use the same PWM cycle)
one counter and 64 comparators with 8-Bit input register and
one bit output register should be sufficient.
This would reduce the hardware cost to one LUT per Bit or 5 Slices per
channel or 320+epsilon Slices total. (A loose fit in a XC2S30)

CU,
	Kolja Sulimma

In article <39BE1A34.92D42A47@andraka.com>,
  Ray Andraka <ray@andraka.com> wrote:
> what is the available clock and required sample rate?  If you can
supply a
> multiplied clock, you can reduce the size of the logic substantially.
That
> said, the brute force design will need 2 luts per bit plus the control
logic, so
> with careful layout you could get it into a 4013/XCS30.  If you go
with Virtex,
> you'll ned an XCV50 or larger device to fit the brute force design.
>
> Michael Warner wrote:
> >
> > Hi folks,
> >
> > I've never used an FPGA, but I have a problem to which they may
> > provide the answer: I need to generate 64 simultaneous high-speed
> > 8-bit PWM signals under micro control; space is at a premium.
> >
> > Imagining it in plain logic, I'd have 64 8-bit latches loaded by
data
> > & address buses. Each latch would pre-load an 8-bit counter on each
> > PWM cycle. The counters would count down, latching themselves at
zero
> > - these latch signals would be the PWM outputs.
> >
> > Is this practical to attempt in a single device? If so, any
> > recommendations of families suited to such a task would be
> > appreciated.
> >
> > Thanks!
>
> --
> -Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930     Fax 401/884-7950
> email ray@andraka.com
> http://www.andraka.com  or http://www.fpga-guru.com
>


Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 25471
Subject: hardware compatibility and patent infringement
From: ABP <ab@cataloniamail.com>
Date: Tue, 12 Sep 2000 15:58:43 +0100
Links: << >>  << T >>  << A >>
Hi,

I need some "light" on "hardware compatibility and patent infringement".
Since Transmeta presented his Crusoe chip I've had a few doubts about
this issue. I would much appreciate any information on the following
points you could give:

1. Is Transmeta's SOFTWARE approach to the manipulation of x86
instructions set what avoids the violation of patents' rights? If that's
right, I understand that patent infringement is only possible when there
is a hardware implementation.

2. In general (for any kind of processor), What's the way to design a
hardware device compatible with the instruction set of another processor
without infringement of patents?

3. If someone implements a processor compatible with the instruction set
of another processor but without copying anyting else from that original
processor    
a part from the original instruction set, will that be patent
infringement?

Although I've been looking quite thoroughly on the web for information
on patents for electronics design (the technical side of the subject)
I've had little success. Can anyone, please, point me to a good source
of information on this subject. 

Thank you all very much for your time.


A. Petit
Article: 25472
Subject: Re: DCT implementation using FPGA
From: Johan Petersson <Johan.Petersson@uab.ericsson.se>
Date: Tue, 12 Sep 2000 17:04:00 +0200
Links: << >>  << T >>  << A >>
Hi Kolja,

Well, that type of //ized arithmetic usually fits very well in FPGAs.
What kind of bandwidths are you looking for? How much time is allowed
for the calculation from the time you recieve the new sample?

I suppose you want it pipelined so that you feed one sample to the
pipeline
every clock cycle and get data on the other side. How much time is
allowed 
between data recieve and data output? 

What other demands do you have on your fpga? Cost? Power consumption?
Area?
InServicePerformance? 

What kind of volumes do you expect to ship of you fpga once the design
is 
finished? 

Do you have any favourite fpga provider? (Mine would be Xilinx :) 

Let me know some more - maybe I could help out with advise or
implementation.
I'm running a company that maybe could help you out :)

See ya,
Johan P, WDI ltd, Sweden

sulimma@my-deja.com wrote:
> 
> Right.
> I was thinking of doing all the y[k] in parallel.
> This will result in k instances of the circuit on your web page.
> 
> To do something like mpeg this shouldn't ne an overkill.
> 
> BTW: shouldn't it be ... sum_N(x[n]cos( ...
>                                  ^
> Otherwise the result is 0.
> 
> CU,
>         Kolja
> 
> In article <39B92A75.DA3C03A6@andraka.com>,
>   Ray Andraka <ray@andraka.com> wrote:
> > Well, not exactly.
> >
> > DCT is the summation   y[k]= c[k] sum_N(x[k]cos(pi*(2n+1)*k/2N))
> >
> > You can use distributed arithmetic, but it is a bit more complicated
> than just
> > setting the constants because the 'constant' is a function of k and n.
> >
> > kolja@prowokulta.org wrote:
> > >
> > > This is from Ray Andraka's web site:
> > > http://www.andraka.com/distribu.htm
> > >
> > > Choose the right C's and you got your DCT.
> > >
> > > CU,
> > >         Kolja
> 
> Sent via Deja.com http://www.deja.com/
> Before you buy.

-- 
APZ FOR MEN BECAUSE FIRST IMPRESSIONS LASTS
Article: 25473
Subject: Using U_SET/HU_SET in RPM's in Xilinx
From: Gary Cook <gc@sonyoxford.co.uk>
Date: Tue, 12 Sep 2000 16:06:15 +0100
Links: << >>  << T >>  << A >>
Hi,

No luck from Xilinx support on this yet so I thought I'd
throw it open to the floor ...

I'm using a flow which involves creating RPM modules
(such as large multipliers) by first synthesizing the block
on it's own with no i/o, place and routing and then from
Floorplanner, writing out the constraints as a UCF file. I
then change the LOCs and RLOCs (and remove the CLB_)
and rename it to an NCF file. I then have an EDF/NCF
pair constituting my RPM.

If this is then instantiated into my main design as a black-box
.... nothing happens! ie RLOCs are ignored.

...until I add U_SETs to the NCF file, which results in the RPM
being placed correctly in the main design and all's well ...

until I want to instantiate the same RPM twice ... can't use U_SETs
'cos they conflict across the hierarchy in this case. So, tried
HU_SETs ... now with HU_SETs I not only don't get the RPM
placed correctly using two blocks, but also if I only instantiate
1 block the RLOCs are ignored again.... ???

The format of the NCF file is

  INST <instance> RLOC="...";
  INST <instance> HU_SET="set1";

Anyone know of the correct way to instantiate the same RPM?

Thanks,

Gary Cook.
Oxford, UK.

Article: 25474
Subject: Re: How do I mix vhdl and verilog source files in Synplify?
From: Johan Petersson <Johan.Petersson@uab.ericsson.se>
Date: Tue, 12 Sep 2000 17:12:39 +0200
Links: << >>  << T >>  << A >>
Hi all,

I've not got around to check out Synplify yet :)
But I have used Leonardo a lot and in Leonardo it's very simple to
mix sources written in verilog and VHDL. Actually I was in exactly the
same situation as Thomas - I have worked a lot with Verilog but for
reasons
not belonging to this news-group I prefer to write my stuff in vhdl...
:)

If Leonardo is an option for you, Thomas, I'm happy to write a comment
on
how it's done!

Good luck with your old design :)
/Johan P  

Phil Hays wrote:
> 
> Thomas Karlsson wrote:
> 
> > I trying to synthesize an old design written in verilog (which is not my
> > cup of tea, I use VHDL). This design instantiate some module, but I want
> > to use a new version of this module, written in VHDL. How do I do this?
> > I am using Synplify 6.0, which should support mixed language source
> > files, but it complains that the referenced module can not be found.
> 
> It would be nice if Synplify would accept mixed language input like some
> simulators.  I suspect that there are some lovely issues at the boundaries
> between the languages...  Not holding my breath.
> 
> I have an idea that I hope to try at work soon.
> 
> What I have done was to compile a VHDL file and have Synplify write out a
> Verilog simulation file.  (Options menu).  I then renamed this file (foo.vm to
> foo2.v) and had Synplify compile foo2.v.  It compiled to exactly the same result
> after place and route as the original file (foo.vhd) compiled to.  This example
> was rather small, a hundred gates or so.
> 
> What I hope to try is to compile a similar module in VHDL to a Verilog
> "simulation file", and instantiate this in a larger Verilog design, and then
> compile the whole thing to a EDIF for building into a FPGA.
> 
> Synplicity's help file makes the point that "The Verilog and VHDL output files
> from Synplify are for functional simulation only."  As such, this method is
> probably(?) unsupported(!!).  A simulation to verify the whole procedure using a
> VHDL or Verilog netlist extracted from the placed and routed design would seem
> to be a very good idea.
> 
> --
> Phil Hays

-- 
APZ FOR MEN BECAUSE FIRST IMPRESSIONS LASTS


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