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Messages from 25550

Article: 25550
Subject: emma/dy ssn
From: Mark Coles <mark.coles@sabre.com>
Date: Wed, 13 Sep 2000 15:57:57 -0600
Links: << >>  << T >>  << A >>
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Article: 25551
Subject: Re: Virtex 1800 series ISP proms
From: "Alun" <alun101@DELETEtesco.net>
Date: Wed, 13 Sep 2000 23:06:21 +0100
Links: << >>  << T >>  << A >>
and even better you might have the 'special' 1804 parts that have an 1802
die.
Two faults in one PROM. Beat that Altera.

Alun

"Peter Schulz" <p.schulz@signaal.de> wrote in message
news:8pnsav$267$1@ezri.addix.net...
> If you have an engineering sample of the 1804
> the CF pin must be left unconnected
>
> Peter Schulz
>
> Tom Leacock schrieb in Nachricht <39BE4FFC.E100FA84@pavcal.com>...
> >Has anyone had any success programming the XC1804 ISP proms for Xilnx
> >virtex parts with the JTAG download? I am using the  XC1804-pc44 proms
> >and multi-linx downloader, but the JTAG interface does not even
> >recognize the proms.
> >-- Thanks,
> >--Tom
> >----------------------------------------------
> >Thomas Leacock
> >Panasonic AVC American Laboratories (PAVCAL)
> >311 Main Street
> >Westampton NJ 08060
> >Phone: 609-518-3700 ext. 3218
> >Fax:   609-518-3720
> >email: toml@pavcal.com
> >----------------------------------------------
>
>


Article: 25552
Subject: Re: Is this practical?
From: Lasse Langwadt Christensen <Langwadt@ieee.org>
Date: Thu, 14 Sep 2000 00:06:24 +0200
Links: << >>  << T >>  << A >>


Michael Warner wrote:
> 
> On Tue, 12 Sep 2000 11:59:31 GMT, Ray Andraka <ray@andraka.com> wrote:
> 
> >what is the available clock and required sample rate?  If you can supply a
> >multiplied clock, you can reduce the size of the logic substantially.
> 
> It's pretty slow - the PWM time-slice is probably no less than 1us.
> I'll have to read up on these "multiplied clocks", since they seem to
> be the key to success :-)
> 
> Thanks for your help, folks!

how about something like this: 

if you have a clock that is 16 times your data rate,  
the you could do 16 channels with 16*8bit RAM + one 12 bit counter, 
an 8bit comparetor and 16 FlipFlops     
  
then sequentially (at 16*datarate) each channels PWM value (choosen by
the 4LSB)
is compared to the counters 8bit MSB. If they are equal the output
flipflop is 
cleared, everytime the counters 8bit MSB is zero all the flipflops are
sequentially 
set. (you may have to treat a PWM value of 0 or 255 specially)    

For 64 channels you could just make four of these

if you make the input from the micro with a multiplexed data/address
you'd need 64 output pins + clock pin + WE + ALE + 8bit data/address  
that's 75 IOs 

since I have very little experience  with FPGAs  I have no idea how
small 
and FPGA it would fit in, but i know that you can get even a XCS05 in
100 pin 
package with 77 IOs   
 
--Lasse 
(+)--------------------------(+)
 | Lasse Langwadt Christensen |
 | Aalborg, Denmark           |  
(+)--------------------------(+)
Article: 25553
Subject: Re: hardware compatibility and patent infringement
From: Zoltan Kocsi <root@127.0.0.1>
Date: 14 Sep 2000 10:31:44 +1100
Links: << >>  << T >>  << A >>
"Martin Usher" <martinusher@earthlink.net> writes:

> 4) I've got a real 'thing' about people who patent bullshit things,
> especially if they really believe that they invented this stuff. It takes a
> special combination of arrogance and ignorance to believe that you have
> truly invented something basic in our trade. They need to humble up, learn a
> bit, and maybe work hard enough to actually invent something new.

I don't think they care about inventing anything. They care about making
money. The patent/copyright law is a good vehicle for making a quick
buck. Today neither has anything to do with creating something, apart
from wealth, of course, for the IP owners and the lawyers. 

Zoltan

-- 
+------------------------------------------------------------------+
| ** To reach me write to zoltan in the domain of bendor com au ** |
+--------------------------------+---------------------------------+
| Zoltan Kocsi                   |   I don't believe in miracles   |  
| Bendor Research Pty. Ltd.      |   but I rely on them.           |
+--------------------------------+---------------------------------+
Article: 25554
Subject: Re: Is this practical?
From: Ray Andraka <ray@andraka.com>
Date: Wed, 13 Sep 2000 23:42:15 GMT
Links: << >>  << T >>  << A >>
Basically what I was suggesting, although I also inferred using direct digital
synthesis rather than messing with loading up counters since it gives you more
flexiblity in the generated frequency.  In that case, you use an accumulator
with memory configured as a shift register as the stroage element.  If you are
in a 4000/spartan series part, you are looking at 2 16x1 RAMs and an accumulator
bit per bit per 16 channels, plus a little for the counters for the ram.  In
virtex, you can use the Block RAMs instead of the CLB RAM to get you into a pair
of block rams and a handful of LUTs, which will easily go into an XC2S15.

Lasse Langwadt Christensen wrote:
> 
> Michael Warner wrote:
> ?
> ? On Tue, 12 Sep 2000 11:59:31 GMT, Ray Andraka ?ray@andraka.com? wrote:
> ?
> ? ?what is the available clock and required sample rate?  If you can supply a
> ? ?multiplied clock, you can reduce the size of the logic substantially.
> ?
> ? It's pretty slow - the PWM time-slice is probably no less than 1us.
> ? I'll have to read up on these "multiplied clocks", since they seem to
> ? be the key to success :-)
> ?
> ? Thanks for your help, folks!
> 
> how about something like this:
> 
> if you have a clock that is 16 times your data rate,
> the you could do 16 channels with 16*8bit RAM + one 12 bit counter,
> an 8bit comparetor and 16 FlipFlops
> 
> then sequentially (at 16*datarate) each channels PWM value (choosen by
> the 4LSB)
> is compared to the counters 8bit MSB. If they are equal the output
> flipflop is
> cleared, everytime the counters 8bit MSB is zero all the flipflops are
> sequentially
> set. (you may have to treat a PWM value of 0 or 255 specially)
> 
> For 64 channels you could just make four of these
> 
> if you make the input from the micro with a multiplexed data/address
> you'd need 64 output pins + clock pin + WE + ALE + 8bit data/address
> that's 75 IOs
> 
> since I have very little experience  with FPGAs  I have no idea how
> small
> and FPGA it would fit in, but i know that you can get even a XCS05 in
> 100 pin
> package with 77 IOs
> 
> --Lasse
> (+)--------------------------(+)
>  | Lasse Langwadt Christensen |
>  | Aalborg, Denmark           |
> (+)--------------------------(+)

-- 
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com  or http://www.fpga-guru.com
Article: 25555
Subject: Re: Complaint: Xilinx functional simulation libraries
From: Andy Peters <"apeters <"@> n o a o [.] e d u>
Date: Wed, 13 Sep 2000 17:33:06 -0700
Links: << >>  << T >>  << A >>
eml@riverside-machines.com.NOSPAM wrote:

> Almost forgot - technically, it's illegal to run the sim with ns
> resolution, since the library contains ps delays (LRM 3.1.3.1).
> However, I suspect that most simulators can cope with this.

It's worse that you think.  The delays aren't given as 100 ps -- they're
given as 0.10 ns.  Simulating with the resolution set to ns doesn't
elicit a complaint.  A complaint is generated if I change the delay to
100 ps.  ModelSim's complaint of "Time unit 'ps' is less than the
simulator resolution set by '-t'," with an implicit assumption that the
user knows things are going to be rounded.  The complaint is a warning,
not an error.

I thought that fractional times were not allowed.  So, I thumbed through
my copy of Ashenden's book, and he mentions that you "can write
non-integral multiples of primary or secondary units."  The caveat is
that values smaller than the primary unit are rounded, which is the
mechanism that sets the 0.10 ns prop delay to zero.  It's a caveat
because there's no warning that the rounding is taking place.

-- andy
----------------------------
Andy Peters
Sr. Electrical Engineer
National Optical Astronomy Observatory
950 N Cherry Ave
Tucson, AZ 85719
apeters (at) n o a o [dot] e d u
Article: 25556
Subject: Re: Complaint: Xilinx functional simulation libraries
From: Andy Peters <"apeters <"@> n o a o [.] e d u>
Date: Wed, 13 Sep 2000 17:48:25 -0700
Links: << >>  << T >>  << A >>
eml@riverside-machines.com.NOSPAM wrote:
 
> You're right, it doesn't affect them. I've just checked and just about
> everything of any interest in the library has these delays. So, the
> question is, are there any circumstances in which addition of an
> arbitrary 100ps delay will screw up a functional sim? I can only think
> of two:
> 
> 1) If you instantiate lots of unisims components in a chain, such that
> the cumulative 100ps delays add up to more than a clock period, then
> the sim will fall over. Unlikely, but possible.

I my case, it was a simple screwup in state machine timing.  Things were
one tick off.  That one tick leads you to re-write the state machine,
which is "correct" in the functional simulation, but incorrect when you
do a post-P+R timing simulation!

Now I understand why I had major problems with a Xilinx FIFO core awhile
ago.  Broken model!  The hardware matched the post-route simulation
pretty much exactly, but the post-route logic was wrong.  I ended up
rolling my own FIFO using a logicore dualport.
 
> 2) More interesting: the Unisim clock elements (IBUFG/BUFG) also have
> the default 100ps delay. If you're into coding guidelines, you'll know
> that you shouldn't put a delta delay on a clock by doing something
> like
>  CLKA <= CLKB
> because of the potential for races. This is similar, just much worse -
> in fact, it's plain wrong, Mr. Patel, if you're reading this. 

A published model uses that construct to get a delay?  Oy!

To be fair to Xilinx: I'm sure they're not the only vendor with this
problem.  For my last design, I used a Micron SDRAM part, and used their
model in the test bench.  Of course, the model has timing checks and
prop delays, though it's not a VITAL model.  As you can imagine, those
delays wreaked all sorts of havoc with a functional sim.  The good thing
is that all of their prop delays (as well as other time specs) are all
generics, so it's easy to set 'em to zero.  I modified the model to add
a CHECK_TIMING generic that, if false, skips the setup/hold time/cycle
time checks.

I find VITAL models to be the most obfuscated things ever.

-- andy
----------------------------
Andy Peters
Sr. Electrical Engineer
National Optical Astronomy Observatory
950 N Cherry Ave
Tucson, AZ 85719
apeters (at) n o a o [dot] e d u
Article: 25557
Subject: Re: How do I mix vhdl and verilog source files in Synplify?
From: Phil Hays <spampostmaster@sprynet.com>
Date: Wed, 13 Sep 2000 19:01:57 -0700
Links: << >>  << T >>  << A >>
Johan Petersson wrote:

> I've not got around to check out Synplify yet :)

Perhaps you should.  I have tried Leonardo, it is a good tool,  but Synplify
gives smaller faster results.


> If Leonardo is an option for you, Thomas, I'm happy to write a comment
> on how it's done!

Would you please write a comment on how to do it?  A small example?  Syntax
suggestions?  What sorts of issues to watch for?  Simulation hints?  This is
something that I expect will be needed more often with increasing use of IP.


-- 
Phil Hays
Article: 25558
Subject: Re: hardware compatibility and patent infringement
From: "Austin Franklin" <austin@darkroom98.com>
Date: 14 Sep 2000 02:17:14 GMT
Links: << >>  << T >>  << A >>
> > 1. Is Transmeta's SOFTWARE approach to the manipulation of x86
> > instructions set what avoids the violation of patents' rights? If
that's
> > right, I understand that patent infringement is only possible when
there
> > is a hardware implementation.
> 
> This is not correct...  At least not according to MIPS's lawyers.

Completely different issue.  The instruction set is not patented, nor can
it be.

> MIPS is
> currently suing Lexra for doing software emulation of some patented
> instructions (LWL, LWR, SWL, and SWR to be exact).  Of course
> Lexra's lawyers would disagree.

Here is the patent:

http://patent.womplex.ibm.com/details?&pn=US04814976__

I have written code to do the same thing for over 20 years, and I know I
have seen other code before mine that did the same thing.  I even did a
microcode implementation similar to this in a 29203C some 20 or so years
ago for a vision processor.  There is sure to be plenty of prior art to
this...  I downloaded a copy of the patent in its' entirety, and perhaps
there is something really patentable here, but from my initial look, it
seems like this won't hold up.  Just my opinion...

Here are the 14 'claims':

What is claimed is: 
1. In a reduced instruction set computer with a memory holding m-bit words
separated by word boundaries, a device for retrieving an unaligned
reference from said memory comprising: 
a. a general register; 
b. means for retrieving a first word containing a first portion of said
unaligned reference in response to a nth instruction and a second word
containing a second portion of said unaligned reference from said memory in
response to an (n+k)th instruction; 
c. shifting means for shifting said first portion to a first position and
second portion to a second position; and 
d. combining means for combining said first and second portions in said
general register, wherein k and n are positive integers. 
2. In reduced instruction set computer, a device for storing an unaligned
reference into a memory with m-bit locations comprising: 
shifting means for shifting said unaligned reference in a first direction
in response to an nth instruction and in a second direction in response to
(n+k)th instruction, said means generating sequentially a first and second
portion each having less than m-bits; and 
means for storing said first and second portions sequentially into said
memory, wherein k and n are positive integers. 
3. In a reduced instruction set computer with a memory for holding m-bit
words, a device for loading a first unaligned reference having first and
second portions of less than m-bits, said first portion being stored into a
first section of said memory and said second portion being stored into a
second section of said memory, and for storing a second aligned reference
into said first and said second sections, comprising: 
a shift/merge unit having first and second inputs and being provided to
shift first data bytes received from said first input, said first input
being coupled to said memory unit to receive said first and second portions
sequentially, and merge said first data bytes with second data bytes from
said second input to form an m-bit word; 
a first latch means for storing said first and second data bytes, said
latch having an output coupled to said second input; 
an m-bit general register coupled to said first latch means and provided
for holding selectively one of said first or second unaligned references; 
a second latch means coupled to said register for storing said second
unaligned reference; 
shifting means for shifting said second unaligned references; and 
output means for storing said second unaligned reference after shifting by
said shifting means into said memory. 
4. The device of claim 3 wherein said shift/merge unit shifts bytes
received from said memory in a first direction in response to a first load
instruction, and in a second direction in response to a second load
instruction. 
5. The device of claim 3 wherein said shifting means shifts bytes received
from said second latch means in a first direction in response to a first
store instruction, and in a second direction in response to a second store
instruction. 
6. The device of claim 3 further comprising a bypass multiplexer for
selectively coupling to said second input one of the outputs of said first
and second latching means. 
7. The device of claim 4 wherein said first and second load instructions
are at least partially overlapped. 
8. The device of claim 5 wherein said first and second store instructions
are at least partially overlapped. 
9. A method of loading an m-bit unaligned reference from a memory, said
memory holding m-bit words separated by word boundaries, said m-bit
unaligned reference being divided into a first portion and a second portion
by a word boundary, comprising the steps of: 
a. retrieving a first word from said memory containing said first portion
during an (nth) instruction; 
b. shifting said first portion to a first position; 
c. retrieving a second word containing said second portion during an
(n+k)th instruction; 
d. shifting said second portion to a second position; and 
e. merging said first and second portions; 
wherein said k and n are positive integers and wherein said first and
second portions have less than m bits. 
10. The method of claim 9 wherein said first and second positions are
defined by said nth and (n+k)th instruction respectively. 
11. The method of claim 9 wherein said nth and (n+k)th instructions are
overlapped. 
12. A method of storing an unaligned reference into a computer memory, said
computer memory holding m-bit locations separated by word boundaries,
comprising the steps of: 
a. shifting a first portion of said reference to a first portion; 
b. storing said first portion in one location within an nth instruction; 
c. shifting a second portion of second portion of said reference to a
second position; and 
d. storing said second portion to a second location within an (n+k)th
instruction, wherein n and k are positive integers and wherein said first
and second portions have less than m bits. 
13. The method of claim 12 wherein said first and second position are
defined by said nth and (n+k)th instruction respectively. 
14. The method of claim 12 wherein said nth and (n+k)th instructions are
overlapped. 




 
Article: 25559
Subject: MAPLD 2000 - Schedule Released and Final Registration
From: "Richard B. Katz" <rich.katz@nospamplease.gsfc.nasa.gov>
Date: Wed, 13 Sep 2000 23:00:53 -0400
Links: << >>  << T >>  << A >>

                Schedule Released and Final Registration

                 2000 MAPLD International Conference

                     Kossiakoff Conference Center
      The Johns Hopkins Univerisity- Applied Physics Laboratory
                      Laurel, Maryland 20723-6099

                         September 26-28, 2000

The 3rd annual Military and Aerospace Applications of Programmable
Devices and Technologies International Conference will address devices,
technologies, usage, reliability, fault tolerance, radiation
susceptibility, encryption, and applications of programmable devices
and adaptive computing systems in military and aerospace systems. The
program will consist of oral and poster technical presentations and
industrial exhibits.  This conference is open to US and foreign
participation and is unclassified.

   http://rk.gsfc.nasa.gov/richcontent/MAPLDCon00/MAPLDCon00.html

Invited Speakers
================

   Keynote Address: Henry Spencer - SP Systems
        "Faster, Better, but Most Important, Much Much Cheaper"

   History Invited Talk: Eldon Hall, MIT Instrumentation Lab
        "The Apollo Guidance Computer - A Designer's View"
        Introduction by Dr. Roger Launius, NASA Historian

   Dinner Speaker: Dr. Thomas Jones, NASA Astronaut Office
        "ISS: The Exploration Proving Ground"

   Lloyd Massengill, Vanderbilt University
        "Single Event Modeling on Emerging Commercial Technologies"

   Dr. Mark Jones, Virginia Tech
        "High-Level Programming Issues for Large Reconfigurable
         Computing Systems"

   AIAA Invited Talk: James Kinnison, Applied Physics Lab
        "System Level Radiation Tolerance"


Technical Sessions
==================
   A. Military & Aerospace Applications
      Session Chair: Ralph Kohler - Air Force Research Laboratory

   B. Devices, Elements, and Technologies
      Session Chair: Rich Katz - NASA Goddard Space Flight Center

   C. Radiation Environments and Effects
      Session Chair: Ken LaBel - NASA Goddard Space Flight Center

   D. SoC, Synthsis, and IP
      Session Chair: Hans Tiggeler - University of Surrey

   E. Adaptive Computing
      Session Chair: John McHenry - National Security Agency


Sponsored By
============
   NASA Goddard Space Flight Center
   JHU/Applied Physics Laboratory
   National Security Agency
   NASA Electronics Radiation Characterization Project
   Military & Aerospace Programmable Logic Users Group
   American Institute of Aeronautics and Astronautics
   IEEE Aerospace & Electronic Systems Society (AESS)

Article: 25560
Subject: Re: Xilinx and CD databooks (rant)
From: murray@pa.dec.com (Hal Murray)
Date: 14 Sep 2000 06:35:38 GMT
Links: << >>  << T >>  << A >>

In article <39AD86F8.3AC16C8F@xilinx.com>,
 Marc Baker <marc.baker@xilinx.com> writes:
> Thanks for your comments (and I'm sure the thread will continue for a while) on
> the Xilinx DataSource CD.  Based on the feedback, we will avoid having the CD
> automatically start anything, and we'll strive to make the viewing and
> installation options clearer.  In the meantime, you can hit <esc> after inserting
> the current CD, or select Exit once the initial presentation ends.


Thanks for listening AND acting.  (Thought I admit it still blows me
away that you didn't catch that singing/dancing crap internally.  Perhaps
you need to make a few of your internal people use the CD?)

I have suggestion for making web/CD documents easier to use.

What fraction of the Virtex-E doc is pinout details?  (In my copy,
it's over half.)

How about splitting that info out to a separate document?  Most of the
time that I'm scanning the main document, the pinouts are just clutter.
I'd be a lot happier printing my own copy from the web or CD if it
used only half as much paper.

Note that we also need the pinout info in some easy to process format,
probably raw text, so I/we can write some scripts to automate some
pinout processing rather than having to do it manually.  Maybe you
could kill two birds with one stone?



-- 
These are my opinions, not necessarily my employers.  I hate spam.

Article: 25561
Subject: Re: Guide to useing Atmel FPGA (at40k)
From: Ben Franchuk <bfranchuk@jetnet.ab.ca>
Date: Thu, 14 Sep 2000 06:42:02 +0000
Links: << >>  << T >>  << A >>
Paul Maddox wrote:
> 
> Dear NG,
> 
>   Im new to this group so please excuse me for asking daft questions.
> Are there any resources out there for ATMEL FPGAs?
> I just got the atmel fpga evaulation board and I have an application
> for which I think an FPGA like this would suited. Im a hobbiest so I do
> this stuff for fun, so lots of time, but no money ! :-)

One thing I found useful is to print out a copy of
data sheet of the family of FPGA's you are using and any data
libraries and data macro function descriptions.
Also if your software is time limited it might be wise to
wait until you got back and you install the software on a virgin
PC.

>   I wondered if anyone knows any usefull resources and/or URLs that
> I can look at? I am going on holiday and Im taking the books that came with
> it with me so I can read them and learn a bit about the structure of the
> thing.
> 
>   Many thanks
>  Paul Maddox

Many FPGA's are similar in design so general design ideas apply
to many devices. FPGA's in general don't map well to wide simple
gates like a 12 input NAND gate but map better to functions of 3
or 4 variables like a 2 input multiplexer or ripple carry adder
cell.Registers are often free with every logic cell as well.
Small ram like 16xN may have to synthesized taking up a large
number of logic blocks.
The other thing is to understand the design you are creating
well in advance.Some logic layouts don't work well and others do
often with re thinking of the layout. KISS allways works best.
(Keep It Simple Stupid ). Good luck on your project.

Ben.
-- 
"We do not inherit our time on this planet from our parents...
 We borrow it from our children."
"Luna family of Octal Computers" http://www.jetnet.ab.ca/users/bfranchuk
Article: 25562
Subject: Re: hardware compatibility and patent infringement
From: Ben Franchuk <bfranchuk@jetnet.ab.ca>
Date: Thu, 14 Sep 2000 07:06:16 +0000
Links: << >>  << T >>  << A >>
Al Arduengo wrote:
> 
> Easy big fella... I am one of those ones who made some 'C's in college
> but I turned out fairly decent. Dang, now I have a complex!

Well most programers program at the  C level... some even make it
to C++ :)
-- 
"We do not inherit our time on this planet from our parents...
 We borrow it from our children."
"Luna family of Octal Computers" http://www.jetnet.ab.ca/users/bfranchuk
Article: 25563
Subject: Re: Clock skew in XILINX CPLD
From: falk@iee.et.tu-dresden.de (Thomas Falk )
Date: 14 Sep 2000 08:23:47 GMT
Links: << >>  << T >>  << A >>
Hi Simon,

thanks for the answer. What you describe is exatly what I have done
in my design. The timing simulation showed that there is a problem
in the timing, preventing the detection of the edge. 

I'm not sure if I can trust in the simulation, but I can't observe the
effect in the hardware, it disappears if I have my test connections 
included into the design.

What is the timing simulation for if I can't trust in it?

I used asynchronous set and reset inputs in the beginning, but since
the problems appeared I have changed it. In doing this the load on the
clock line got higher. Regarding this and the timing simulation I still
have the suspect, there may be something wrong with the clock itself.
I will try using the PERIOD constraint on the clock net (is this of use,
if the clock is routed via the special GCK net?) and in the next 
revision of the circuit board we will split up the clock into three 
nets, each over one pin and its own GCK net. Then we can experiment
further with this effect simply by changing the loads on the clock 
nets.


Thomas Falk

In article <VVPv5.50696$58.6223724@typhoon.tampabay.rr.com>,
	"S. Ramirez" <sramirez@deleet.cfl.rr.com> writes:
> Thomas,
>      There is an easy way to do what you describe below.  I call it digital
> differentiation, where the job is to detect an edge, leading or otherwise.
>      All you have to do is create a process that delays the signal A by one
> clock cycle.  Assuming signal_A is active high, this is easy to do:
>            signal_A_delayed <= signal_A;
>      Then you simply do the following to create a combinatorial pulse
> (signal_A_diff) that is generated at the edge:
>           assign signal_A_diff = signal_A & ~signal_A_delayed;   // detect
> rising edge
>           assign signal_A_diff = ~signal_A & signal_A_Delayed;  // detect
> falling edge
> 
>      Assuming that you are doing the above, I see no reason why you should
> have any problem with timing.  signal_A_diff is a combinatorial signal that
> is generated to be used by other flip flops, and its prop delay is part of
> the timing between flip flops in a Xilinx net PERIOD constraint.  Thus the
> whole design is still synchronous.
>      Do you have any causal signals that are going to resets or presets of
> flip flops?
> -Simon Ramirez, Consultant
> -Synchronous Design, Inc.
Article: 25564
Subject: Advertisement of a new e-Group/mailing list --
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Date: Thu, 14 Sep 2000 18:26:15 +1000
Links: << >>  << T >>  << A >>
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Article: 25565
Subject: Re: Virtex 'shutdown' phenomenon
From: news@rtrussell.co.uk
Date: 14 Sep 2000 08:39:12 GMT
Links: << >>  << T >>  << A >>
Hawker <Hawker@connriver.net> wrote:

: Are you going into some sort of boundary scan mode?
: I had a similar problem with a XCS05.  I found some
: sort of app note about adding some pull-ups and 2 small caps
: to the JTAG pins and it fixed the problem. Basically random noise
: was putting me an a boundary scan or JTAG programing mode of some sort

That's exactly what it was!  Tying the unused JTAG pins
high has fixed the problem.  Many thanks for your
suggestion.

Richard.
http://www.rtrussell.co.uk/

Article: 25566
Subject: Re: Complaint: Xilinx functional simulation libraries
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Thu, 14 Sep 2000 09:41:40 +0100
Links: << >>  << T >>  << A >>
>

This error/misconception is not exclusive to Xilinx. The post-synth Verilog
netlists produced by Synpilfy don't require the Unisims since they embed
their own models of the Unisims components. These models also use #1 delays
with the timescale set to 100ps/100ps. As a result I've habitually always
added #1 delays to all the assignments in my testbench models.

Of course the other issue, at least with the Verilog Unisims lib, is that
some of them are just plain broken. Take this code from the 2.1i model of a
sync set FF.

 always @(posedge C)
     if (S)
  q_out <= 1;
     else
  q_out <= D;

The problem is that if S = `x' or `z' then the LRM says this it counts as
false & so the data will be clocked through. The previous 1.5i models did it
right since they had something like

assign d_in = D | S;

feeding the input of a UDP used by all the FF models. In effect Synplify
still use this sort of model. For this reason I generally avoid the Unisims
& push through to NGDBUILD/NGD2VER to get a simprims based netlist. These
are still semi-broken since the FFs are over-paranoid but, since they still
use a couple of common UDPs, its much easier to fix. Also since there are
far fewer models its relatively easy to write a generic 0-delay SDF [if the
lisp style haze-of-parentheses doesn't drive you mad].

I was told that the 1.5i -> 2.1i change was done to satisfy some requirement
of the Cadence Concept simulator.


Article: 25567
Subject: Ethernet MII + bit ordering
From: Michael Boehnel <boehnel@iti.tu-graz.ac.at>
Date: Thu, 14 Sep 2000 11:01:45 +0200
Links: << >>  << T >>  << A >>
Hi!

What is the bit ordering of a frame (source, dest, ..., CRC) sent via
Ethernet NIC (3COM 905, 100Mbit)? I suppose it's the following (preamble
neglected):

fields transmitted top to bottom, within bytes least significant bit
first.

source
   byte 5   bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7
   byte 4            :
   byte 3            :
   byte 2            :
   byte 1
   byte 0
destination
   byte 5
   byte 4
   byte 3
   byte 2
   byte 1
   byte 0
:
CRC
   byte 3
   byte 2      :
   byte 1      :
   byte 0  bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7


First bit: source - byte 5 - bit0
Last bit: CRC - byte 0 - bit7

Is above correct?

I am developing a switch with a MII-transceiver chip and a subsequent
FPGA. The transceiver chip delivers data via MII interface to the FPGA
nibble by nibble. The FPGA calculates a CRC. As the FPGA sends data back
to the MII the same ordering as it receives it, there is no problem with
bit ordering. But for the calculation of the CRC bit ordering has to be
taken into account. Since the CRC calculation is done via a LFSR (linear
feedback shift register) bit7 of each byte is shifted in first (high
nibble is needed before low nibble).

Is the only way to solve this problem to use a FIFO to reorder the
nibbles (which results in an additional delay)?

Does a MII transceiver chip reorder the 8 bits in the way that the first
nibble contains bit7-bit 4 and the second (later delivered) nibble
contains bit3-bit0?

Thank you.

Michael



Article: 25568
Subject: Re: Xilinx and CD databooks (rant)
From: "Bill Blyth" <bb@alphadata.co.uk>
Date: Thu, 14 Sep 2000 10:57:51 +0100
Links: << >>  << T >>  << A >>
I would second the point on raw pinout data. This would beat copying the
stuff from the pdf, reformatting it and subsequent symbol generation and
checking.

"Hal Murray" <murray@pa.dec.com> wrote in message
news:8pprjq$9ju@src-news.pa.dec.com...
>
> In article <39AD86F8.3AC16C8F@xilinx.com>,
>  Marc Baker <marc.baker@xilinx.com> writes:
> > Thanks for your comments (and I'm sure the thread will continue for a
while) on
> > the Xilinx DataSource CD.  Based on the feedback, we will avoid having
the CD
> > automatically start anything, and we'll strive to make the viewing and
> > installation options clearer.  In the meantime, you can hit <esc> after
inserting
> > the current CD, or select Exit once the initial presentation ends.
>
>
> Thanks for listening AND acting.  (Thought I admit it still blows me
> away that you didn't catch that singing/dancing crap internally.  Perhaps
> you need to make a few of your internal people use the CD?)
>
> I have suggestion for making web/CD documents easier to use.
>
> What fraction of the Virtex-E doc is pinout details?  (In my copy,
> it's over half.)
>
> How about splitting that info out to a separate document?  Most of the
> time that I'm scanning the main document, the pinouts are just clutter.
> I'd be a lot happier printing my own copy from the web or CD if it
> used only half as much paper.
>
> Note that we also need the pinout info in some easy to process format,
> probably raw text, so I/we can write some scripts to automate some
> pinout processing rather than having to do it manually.  Maybe you
> could kill two birds with one stone?
>
>
>
> --
> These are my opinions, not necessarily my employers.  I hate spam.


Article: 25569
Subject: Re: Clock skew in XILINX CPLD
From: "S. Ramirez" <sramirez@deleet.cfl.rr.com>
Date: Thu, 14 Sep 2000 10:53:45 GMT
Links: << >>  << T >>  << A >>

"Thomas Falk " <falk@iee.et.tu-dresden.de> wrote in message
news:8pq1uj$h1k$1@rks1.urz.tu-dresden.de...

> What is the timing simulation for if I can't trust in it?

--Timing simulations are done in discrete quantities.  The real world isn't
quite as discrete.

> I used asynchronous set and reset inputs in the beginning, but since
> the problems appeared I have changed it. In doing this the load on the
> clock line got higher. Regarding this and the timing simulation I still
> have the suspect, there may be something wrong with the clock itself.
> I will try using the PERIOD constraint on the clock net (is this of use,
> if the clock is routed via the special GCK net?) and in the next
> revision of the circuit board we will split up the clock into three
> nets, each over one pin and its own GCK net. Then we can experiment
> further with this effect simply by changing the loads on the clock
> nets.

--Supplying three clocks into one CPLD/FPGA will result in three clock
domains, even though all of the flip flops should be synchronous to each
other (assuming very careful skew control).  Your timing report will reflect
this division of flip flops and will not report timing relative to the three
clocks' flip flops, unless you do something special.
--What does your singular clock look like going into the pin of the device?
What is its rise and fall times?  What is the Vih and Vil?
-Simon Ramirez, Consultant
 Synchronous Design, Inc.


Article: 25570
Subject: Re: Xilinx and CD databooks (rant)
From: "Tobias F. Garde" <tobias.garde@tellabs.com>
Date: Thu, 14 Sep 2000 13:42:57 +0200
Links: << >>  << T >>  << A >>
Bill Blyth wrote:
> 
> I would second the point on raw pinout data. This would beat copying the
> stuff from the pdf, reformatting it and subsequent symbol generation and
> checking.
> 
> "Hal Murray" <murray@pa.dec.com> wrote in message
> news:8pprjq$9ju@src-news.pa.dec.com...
> >
> > Note that we also need the pinout info in some easy to process format,
> > probably raw text, so I/we can write some scripts to automate some
> > pinout processing rather than having to do it manually.  Maybe you
> > could kill two birds with one stone?
> >

It would be quite useful if Xilinx could provide the raw pinouts
in some readable format. Meanwhile, some information seems to be
available (though not directly) in the BSDL files residing in:

    $XILINX$\device_name\data

For example, I have found pinout information about the XCV300E in
a BG432 package in the file:

    $XILINX$\virtexe\data\xcv300e_bg432.bsd

Regards,

Tobias F. Garde
ASIC Development Engineer
Tellabs Denmark A/S

Article: 25571
Subject: Re: Simon , decoupling caps
From: Ben Franchuk <bfranchuk@jetnet.ab.ca>
Date: Thu, 14 Sep 2000 12:30:15 +0000
Links: << >>  << T >>  << A >>
Dan wrote:
> 
> Simon,
> 
> I would bug anyone until I make a four layer board. If the problem is still
> there, I'll post details.
> 
> I once heard the both a .01 and a .1 cap should be used at each power pin.
> Is that correct. My limited knowledge tells me they would be equal to one
> cap of .11. However I realize there behaviour is more complex than that.
> 
> Is such a recomendation useful ?
> 
> Dan

That is true, it is better than a cap of .11 uf?
For the high frequencies the .01 cap has less
inductance and is able to respond power supply fluctuations quickly until
the .1 cap can catch up. With transistors switching in ps range you need
very good high freq response on the power supplies.

-- 
"We do not inherit our time on this planet from our parents...
 We borrow it from our children."
"Luna family of Octal Computers" http://www.jetnet.ab.ca/users/bfranchuk
Article: 25572
Subject: Re: How do I mix vhdl and verilog source files in Synplify?
From: Thomas Karlsson <thomas.karlsson@emw.ericsson.se>
Date: Thu, 14 Sep 2000 14:38:43 +0200
Links: << >>  << T >>  << A >>
Hello again!

I have found out that I was wrong about the mixed language support in
Synplify v6.0.
However, it is now possible to evaluate the new 6.1 beta release of
Synplify, which do have
the mixed language support. I will try that and see how it works.

Thanks for your help and suggestions.

/Thomas
Article: 25573
Subject: Re: MAX PLUS 2
From: Ben Franchuk <bfranchuk@jetnet.ab.ca>
Date: Thu, 14 Sep 2000 12:50:18 +0000
Links: << >>  << T >>  << A >>
gk7eong wrote:
> 
> Hi,
> 
> I'm a final year electrical electronics engineering student. I'm using
> Max Plus 2 Baseline 9.6 to do my final year project. Is there anyone out
> there with full licences? Can you send me a copy of your license.dat or
> can anybody tell me how to get the partitioner features from it. Thanks
> in advance.
> 
I think the best partitioner is still the old brain cells.I am also
using the Free version of Baseline in a home computer project.With what
little design I have done,I can route about 75% of the LCB's in FPGA.
The licence.dat is only for a specific hard drive, thus you need a
new license if your HD fails, preventing transferring between machines.

Ben.
-- 
"We do not inherit our time on this planet from our parents...
 We borrow it from our children."
"Luna family of Octal Computers" http://www.jetnet.ab.ca/users/bfranchuk
Article: 25574
Subject: Re: Virtex 'shutdown' phenomenon
From: Hawker <Hawker@connriver.net>
Date: Thu, 14 Sep 2000 08:53:08 -0400
Links: << >>  << T >>  << A >>

You may want to hunt for that app note.
There is some exact proper configuration which consisted
of two pull-ups and two small caps (think they were in the 330pF range)
that were involved.  Apparently one of the other engineers tried just pulling
up and that mostly fixed.. but until we got it EXACTLY correct we still had some
problems.

Hawker

news@rtrussell.co.uk wrote:
> 
> Hawker <Hawker@connriver.net> wrote:
> 
> : Are you going into some sort of boundary scan mode?
> : I had a similar problem with a XCS05.  I found some
> : sort of app note about adding some pull-ups and 2 small caps
> : to the JTAG pins and it fixed the problem. Basically random noise
> : was putting me an a boundary scan or JTAG programing mode of some sort
> 
> That's exactly what it was!  Tying the unused JTAG pins
> high has fixed the problem.  Many thanks for your
> suggestion.


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