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Messages from 25775

Article: 25775
Subject: Re: PCI-Tip? (for Xilinx Virtex/-E)
From: yuryws@my-deja.com
Date: Wed, 20 Sep 2000 04:31:48 GMT
Links: << >>  << T >>  << A >>
My experience envolves a design based on PCI 32/33 on Spartan family.
You have to be careful sizing your device. For example, when Xilinx
states that PCI 32/33 should take up only 55% of Spartan 30 XL, what
they really mean that in order to get PCI Master/Slave functional you
need to add some 15%-20% of additional logic on top of the core. That
required logic is extensively described in PCI Logicore Implementation
Guide. Obviously, Xilinx's marketing team minimizes the device
utilization of PCI logicore to make the product more attractive.

-- Yury



In article <39C1EB9F.196D852E@ti.uni-mannheim.de>,
  Lars Rzymianowicz <larsrzy@ti.uni-mannheim.de> wrote:
> Marc Reinert wrote:
> > I'm going to develop a PCI board (33Mhz/32Bit) on one of these
devices.
> > My idea is to have a lot of space left in my FPGA beside the
> > PCI-Interface.
> > Is there a core (or better a complete VHDL-Programming) aviable from
> > Xilinx (or anybody else)? Does it work well and are any features of
the
> > PCI-Bus not supported? Is there a free version aviable on the
internet?
>
> Hi Marc,
>
> Xilinx has the logiCORE PCI macrocell, which is a customizable
> 33/66/32/64 PCI interface. Check the Xilinx website for it, it's
> price is around $5000, i guess.
> Since you are a University, you might consider to join the Xilinx
> Univ. Prg. XUP. There you can also apply for a donation of the core.
> I tried that, but never got any reply on several emails/faxes.
> But maybe you have more luck ;-)
>
> Lars
> --
> Address:  University of Mannheim; B6, 26; 68159 Mannheim, Germany
> Tel:      +(49) 621 181-2716, Fax: -2713
> email:    larsrzy@{ti.uni-mannheim.de, atoll-net.de, computer.org}
> Homepage: http://mufasa.informatik.uni-mannheim.de/lsra/persons/lars/
>


Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 25776
Subject: Re: Complaint: Xilinx functional simulation libraries
From: "Joel Kolstad" <Joel.Kolstad@USA.Net>
Date: Wed, 20 Sep 2000 05:09:14 GMT
Links: << >>  << T >>  << A >>
"K. Orthner" <korthner@hotmail.nospam.com> wrote in message
news:8FAEA273Dkorthnerhotmailcom@158.202.232.7...
> Joel, I'm not sure about this, but won't turning off the "timing checks
on"
> generic only disable the timing checks?  What it won't do is prevent the
> instantiated components from having delays.
>
> Or am I mistaken here?

Ummm... that's a very good question.  I'm off in this nasty place known as
San Jose at the moment, but from recollection... I think you're right that
the instantiated components will still have delays, but I also think that
turning timing checks off will solve Andy's original problem in that it's
the timing check that's causing everything to be one clock off in the first
place.

Hopefully someone else can chime in to confirm this.  With my design,
turning timing checks off made everything "work," but there definitely is
still a 100ps delay on a ClkBufGDLL that is instantiated.

---Joel Kolstad




Article: 25777
Subject: unexpanded XU macros
From: Charles Wagner <Charles.Wagner@irisa.fr>
Date: Wed, 20 Sep 2000 09:34:52 +0200
Links: << >>  << T >>  << A >>
When implementing a design in Xilinx Design Manager (M2.1), using an
EDIF netlist as input,  during design expansion  :
<< logical block "I0/I21/I2" of type "M2_1" is unexpanded.

M2_1 is a macro defined in the Xilinx Unified library.
Where are the netlist files for the XU macros defined ?

Thanks for your help,
Charles
Article: 25778
Subject: Re: Complaint: Xilinx functional simulation libraries
From: korthner@hotmail.nospam.com (K. Orthner)
Date: 20 Sep 2000 07:37:02 GMT
Links: << >>  << T >>  << A >>
Joel.Kolstad@USA.Net (Joel Kolstad) wrote:

>I think you're right
>that the instantiated components will still have delays, but I also
>think that turning timing checks off will solve Andy's original problem
>in that it's the timing check that's causing everything to be one clock
>off in the first place.

Will turning off the timing checks change the simulation results?  That's 
kind of a scary situation if it does; if checking for a problem causes the 
problem?  


I imagine that turning off the timing checks gets rid of the three million 
messages (give or take) that you get, but doesn't actually change the sim. 
results.

Unless that generic is passed to the function (procedure? entity?) that 
performs the delay(s), and insturcts it not to do them.

>Hopefully someone else can chime in to confirm this.  With my design,
>turning timing checks off made everything "work," but there definitely
>is still a 100ps delay on a ClkBufGDLL that is instantiated.

With your design, did the simulation results change before and after 
changing that generic?

-kent

Article: 25779
Subject: Re: Freelance Designer Needed: Protel & FPGA
From: korthner@hotmail.nospam.com (K. Orthner)
Date: 20 Sep 2000 07:40:54 GMT
Links: << >>  << T >>  << A >>
sramirez@deleet.cfl.rr.com (S. Ramirez) wrote in
<COVx5.1515$W45.173731@typhoon.tampabay.rr.com>: 

>Not to mention that you would have to trust this company to tell you
>their sales and pay you accordingly.  I wouldn't trust a company unless
>I knew the principles personally.  I've had to police companies in the
>past, and it isn't fun.  Besides, policing adds to the 30-40 hours that
>they defined. -Simon Ramirez, Consultant
> Synchronous Design, Inc.


<tongue in cheek>

Maybe follow Xilinx's example . . . do the first 40 hours of work, and then 
stop working until they pay you for another 40 hours of work.

Hmm.  And have different options, too.
If they buy the gold package, you even check over your work.  (Which you 
wouldn't normally accomplish in the first 40 hours.)

<tongue out of cheek>

-Kent
Article: 25780
Subject: Re: An Online Course for CPLD and FPGA design
From: Philip Freidin <philip@fliptronics.com>
Date: Wed, 20 Sep 2000 00:50:07 -0700
Links: << >>  << T >>  << A >>
Sometimes the BS alarm goes off, and I just ignore it because life
is short. Sometimes it is so egregious, or I have too much time on
my hands (or just insomnia), so some flames occur.

While I could be generous, as a friend of mine suggested, and just
comment that the following excellent article could only be improved
by having "ADVERTISEMENT" at the top, I feel like going a little
further:

On Tue, 19 Sep 2000 11:36:10 -0700, "Shai Gilat" <shai@chalknet.com> wrote:
>Hey, I just found this cool course for CPLD and FPGA design. It's online and
>self-paced. It provides an excellent foundation for experienced engineers
>who want to start their first CPLD or FPGA design. Also, engineers who have
>done several designs in the past can get valuable knowledge for their
>current design methodologies. The name of the course is "Introduction to
>CPLD and FPGA Design," and if it sounds interesting, you can find it on
>www.chalknet.com. The instructor is an IEEE award winning engineer and
>sounds like he knows what he is talking about.
>Shai

So let's see --- shai @ chalknet.com --- has just "found" this cool course
at none other than at --- www .chalknet .com --- . I guess internal
communications at the company must be poor, since he wasn't advised about
it through normal channels. Maybe he was just cruising his company's web
site and tripped over it. It could happen. His title is "Chief Head-Butter"
(see the President's Column page).

"It's online and self-paced." so I guess you paid the $195 for it. Do you get
a company discount? By the way, navigating you site sucks. None of the links
in the column to the left will get you to the course you mentioned. In fact
the "Hot Courses" drops you into a dead page.

"The instructor is an IEEE award winning engineer", sure enough!, and he's
your boss too! ,  "and sounds like he knows what he is talking about." I
guess you are tryingfor a raise as well!

Two years ago, someone else posted an article about how wonderful his
company's products were, as a pretty pathetically disguised product
evaluation. To quote Steve Knapp:

"I haven't tried the product and it may be _just_ that good but until then,
if you are a marketing guy, please don't try to kid the kidders."

Hopefully you wont be annoying us with announcements of this type again.

Article: 25781
Subject: Re: Safe voltage regulator for Xilinx XC2S150 part?
From: "Gary Watson" <gary2@nexsan.com>
Date: Wed, 20 Sep 2000 09:31:13 +0100
Links: << >>  << T >>  << A >>

OK, does 1300 mW of 2.5 volts sound about right for a XC2S150 which is
pretty much filled up with a 8 bit microprocessor and its software, plus a
bunch of glue logic, running at 20 MHz?  That's the output of the Xilinx
power estimator program, if I understand how to use it.

--

Gary Watson
gary2@nexsan.com
Nexsan Technologies Ltd.
Derby DE21 7BF  ENGLAND
http://www.nexsan.com


"Austin Lesea" <austin.lesea@xilinx.com> wrote in message
news:39C69C1B.AD13EF81@xilinx.com...
> Gary,
>
> It is trivial, really.
>
> Go to the power estimator page, and fill out the estimator with as many
educated
> guesses as you can for a V150.  Be really over conservative (more IO's,
more
> CLB's, higher percentage of switching, etc).
>
> Look at how much current is predicted.
>
>  http://www.xilinx.com/cgi-bin/powerweb.pl
>
> Make sure you are not exceeding the power dissipation for the device.
>
> The XC2S150 will be less current that the 150 due to the process
improvements.
> We will have more data on that it the future.
>
> The estimator is based on actual lab measurments of designs.  It is a vast
> improvement over any power estimation for FPGAs I have seen before.  We
> correlate its results against a number of customer reference designs,
>
> Austin
>
> Gary Watson wrote:
>
> > I know it's difficult to predict the power requirements of Xilinx parts,
but
> > what's a safe 2.5V regulator to use for the internal supply of a
XC2S150?
> > The data sheet is most unhelpful in figuring this out.  Since I plan to
roll
> > out this product in phases over the next year, I can't say what all my
> > internal logic might be doing down the road, so I'm happy to over-spec
the
> > regulator to a reasonable degree.
> >
> > By the way, I'm getting quoted over 10 UK pounds ($14) for the config
prom
> > for this puppy (XC18V01S20C).  Is there a cheaper way to do this?  This
prom
> > increases the cost of using a Spartan II by 50%!
> >
> > --
> >
> > Gary Watson
> > gary2@nexsan.com
> > Nexsan Technologies Ltd.
> > Derby DE21 7BF  ENGLAND
> > http://www.nexsan.com
>
>




Article: 25782
Subject: FPGA compiler abort 219
From: Reynald Pireyre <r-pireyre@ti.com>
Date: Wed, 20 Sep 2000 10:32:02 +0200
Links: << >>  << T >>  << A >>
HI
I use FPGA compiler II, (target xilinx)
All VHDL source has been compiled.
But during  elaborating on Xilinx target, the soft crash.
And report file is not available , only "abort at 219" !!!!
You know this problem
thanks
reynald


Article: 25783
Subject: Re: Simon , decoupling caps
From: eml@riverside-machines.com.NOSPAM
Date: Wed, 20 Sep 2000 09:27:12 GMT
Links: << >>  << T >>  << A >>
On Sat, 16 Sep 2000 12:44:52 -0700, Bob Perlman
<bobperl@best_no_spam_thanks.com> wrote:

>Hi - 
>
>Some good papers on decoupling can be found at:
>
>http://www.qsl.net/wb6tpu/si_documents/docs.html

Thanks for the link. The fourth paper in the list is "Decoupling
capacitor calculations", and its one that I read a couple of years
ago; I haven't read the others.

However, without wishing to be offensive, I have to say that this
paper is just plain wrong. The recommendations the author arrives at
are way too low. The basic problem is that he's taking an *average*
power consumption for his boards, and then deriving the charge
required per clock cycle, and giving the capacitor size required to
supply this charge. This completely ignores the fundamental reason for
using capacitors to supply 'instantaneous' current to a device. There
will be times when a device suddenly needs current because, for
example, an unusually large number of internal nodes are charging,
several outputs are switching simultaneously, an internal clock edge
has just occurred, or whatever. These requirements are not necessarily
directly related to the devices clock frequency and may, for example,
occur 5ns after every 10th input clock, in a 2ns window. The point of
having local reservoir capacitors is to supply these instaneous
current requirements, which can't be supplied by the PSU since the
main supply inductances don't allow charge to be supplied 'quickly'.
Sure, you can average everything up and come up with a time-averaged
requirement, but it doesn't help. You need to know what the worst-case
instantaneous requirement is, and you have to calculate the required
capacitor which will supply this requirement, with an acceptable
voltage droop, and with a low enough inductance to allow it to be
supplied while it's still useful.

It would be interesting to hear from anyone else who's read this paper
and has a view on it.

Evan  
Article: 25784
Subject: Re: Virtex clock fanout
From: eml@riverside-machines.com.NOSPAM
Date: Wed, 20 Sep 2000 09:27:44 GMT
Links: << >>  << T >>  << A >>
On Mon, 18 Sep 2000 19:58:50 +0100, "Alun" <alun101@DELETEtesco.net>
wrote:

>There is an article on how to get low skew with non-clocked outputs which I
>can't lay my hands on right now. I got it from the Xilinx web site and
>covers the use of MAXSKEW (Xilinx P&R) and placement out outputs for low
>skew.

http://www.xilinx.com/xcell/xl32/xl32_53.pdf

Maybe next time you copy it you should keep one for yourself...  :)

Evan
Article: 25785
Subject: Re: Freelance Designer Needed: Protel & FPGA
From: eml@riverside-machines.com.NOSPAM
Date: Wed, 20 Sep 2000 09:30:54 GMT
Links: << >>  << T >>  << A >>
On Mon, 18 Sep 2000 20:48:09 GMT, "S. Ramirez"
<sramirez@deleet.cfl.rr.com> wrote:

>     Does anyone in this newsgroup realistically think that they can do the
>work below in 30-40 hours?  

Yup, this is crazy. In case anyone in this NG is thinking of
responding, my back-of-the-stamp calculation, assuming a cast-iron and
simple spec, is that you shouldn't even think about this unless the
price is at least 8000 UKP, or $12000. Also, (1) don't even think
about taking a share of board sales, (2) make sure you get him to sign
*your* contract, in which you keep your own IP, (3) make sure your
contract specifies a staged payment scheme, and that you're never in a
situation in which you've done *any* work without being paid for it,
(4) make sure you get paid more if the spec changes, (5) if he wants
you to use Protel, then he should supply it, and so on.

Evan
Article: 25786
Subject: Synthesiser comparisons (was: FPGA Express strikes again)
From: eml@riverside-machines.com.NOSPAM
Date: Wed, 20 Sep 2000 09:32:29 GMT
Links: << >>  << T >>  << A >>
Thanks for the corrections on Synplify sync reset. What I should have
said was that there was a problem with coding up both a clock enable
and a sync reset on a F/F; I had a meeting with a rep in May who told
me this (haven't tried it myself), which means that you can't code up
6-in functions on a Virtex F/F. On the other hand, you can do this
with Spectrum, and it can be very useful.

This type of issue comes up fairly frequently, but there's no simple
way to find out if a particular synthesiser supports feature X on
family Y, or if it messes up a particular code template, or generates
twice as much hardware as required, or whatever, short of trying it
for yourself.

It occurs to me that it would be useful to pool the information that
we do have, and to find a structured way of getting the information
that we don't have, so that this information gets into the public
domain. This would involve, as a starting point, writing or collecting
various code templates, passing them around to anyone who has the
appropriate tools and is willing to help (possibly anonymously), and
collecting the results on a website.

Is anyone interested in doing this? If there's a critical mass, I
could try setting up a mailing list and a web site and repository,
hopefully using existing resources from eda.org, seul.org,
sourceforge, or whatever.

The sort of information that I think would be useful would be, for a
given synth and a given family:

* support of global resources such as resets and clocks
* support for architecture features such as clock enables, (a)sync
resets, extra CLB muxes, carry chains
* language-specific features: language conformance, user-defined and
vendor-specific attributes, standard and unusual templates,
initialisation functions
* support for low-level design constraints
* whatever you can think of

There's a potential issue with vendors, who may believe that
publishing this information contravenes an individual licence
agreement. However, these tend to explicitly prohibit "benchmarking"
operations, rather than anything else. Benchmarking, as such, wouldn't
necessarily be covered. Most of the issues covered above are simply
functionality issues.

What do you all think? Anyone willing to help?

Evan
Article: 25787
Subject: Placement and routing of Xilinx physical macro can't be locked
From: "Josef Däubler" <josef.daeubler@vs.dasa.de>
Date: Wed, 20 Sep 2000 13:39:00 +0200
Links: << >>  << T >>  << A >>
I have the following problem:

One module of my design is entered as a physical macro in Xilinx FPGA
Editor, the rest of the design is entered with VHDL and synthesised with
Leonardo Spectrum.

During implementation  the macro file (.nmc file) is read in by the Xilinx
Alliance 3.1i tools (ngdbuild, map, par), but after that the original
placement and routing of the macro is destroyed.

Is there any possibility of locking the placement and routing?

Thanks
Seppi


Article: 25788
Subject: Re: Complaint: Xilinx functional simulation libraries
From: Ray Andraka <ray@andraka.com>
Date: Wed, 20 Sep 2000 13:17:38 GMT
Links: << >>  << T >>  << A >>
It has been a while since I started turning off that generic unconditionally. 
As far as I can recall though, turning it off did change the sim results which
is why I started leaving it off.   I haven't taken the time to figure out the
vital code for the unisim parts, but I am suspecting turning it off might change
some of the delays.  Anyway, since I got in the habit of turning it off I have
not encountered the problem.  As a refresh, the problem was that when I mixed
instantiated primitives with RTL code, the instantiated stuff essentially had
some delta delays on the clock so data that was changing on a clock edge in the
RTL code was getting clocked into clocked primitives on the same clock edge. 
Like I said, I haven't seen that since I started turning the generic off over a
year ago.  I don't remember what prompted me to do that...I think it might have
been a suggestion from Aldec's tech support though

"K. Orthner" wrote:
> 
> Joel.Kolstad@USA.Net (Joel Kolstad) wrote:
> 
> ?I think you're right
> ?that the instantiated components will still have delays, but I also
> ?think that turning timing checks off will solve Andy's original problem
> ?in that it's the timing check that's causing everything to be one clock
> ?off in the first place.
> 
> Will turning off the timing checks change the simulation results?  That's
> kind of a scary situation if it does; if checking for a problem causes the
> problem?
> 
> I imagine that turning off the timing checks gets rid of the three million
> messages (give or take) that you get, but doesn't actually change the sim.
> results.
> 
> Unless that generic is passed to the function (procedure? entity?) that
> performs the delay(s), and insturcts it not to do them.
> 
> ?Hopefully someone else can chime in to confirm this.  With my design,
> ?turning timing checks off made everything "work," but there definitely
> ?is still a 100ps delay on a ClkBufGDLL that is instantiated.
> 
> With your design, did the simulation results change before and after
> changing that generic?
> 
> -kent

-- 
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com  or http://www.fpga-guru.com
Article: 25789
Subject: Re: hardware compatibility and patent infringement
From: Brian Drummond <brian@shapes.demon.co.uk>
Date: Wed, 20 Sep 2000 14:44:08 +0100
Links: << >>  << T >>  << A >>
On 14 Sep 2000 10:31:44 +1100, Zoltan Kocsi <root@127.0.0.1> wrote:

>"Martin Usher" <martinusher@earthlink.net> writes:
>
>> 4) I've got a real 'thing' about people who patent bullshit things,
>> especially if they really believe that they invented this stuff. It takes a
>> special combination of arrogance and ignorance to believe that you have
>> truly invented something basic in our trade. They need to humble up, learn a
>> bit, and maybe work hard enough to actually invent something new.
>
>I don't think they care about inventing anything. They care about making
>money. The patent/copyright law is a good vehicle for making a quick
>buck. Today neither has anything to do with creating something, apart
>from wealth, of course, for the IP owners and the lawyers. 
>
There may be reasons for a patent application, completely independent of
the merits or otherwise of the patent itself.

Try selling a project proposal to investors without the comforting
protection of a patent or at least a patent application behind it. 

- Brian
Article: 25790
Subject: Re: VHDL to SCHEMATIC
From: "Eric Pearson" <ecp@focus-systems.nospam.on.ca>
Date: Wed, 20 Sep 2000 10:38:21 -0400
Links: << >>  << T >>  << A >>
Hi Erika...

I've used Viewgen (came with Viewdraw) to do this.
Not the most pretty schematics, but helpful.

Eric

erika_uk@my-deja.com wrote in message <8q8luu$j7o$1@nnrp1.deja.com>...
>sorry, i wanted to say edif .
>
>In article <8q8lqb$iu3$1@nnrp1.deja.com>,
>  erika_uk@my-deja.com wrote:
>> hi,
>>
>> can F2.1i generate the schematic from vhdl (or edif) entry.
>> If no, is there any tool which does so
>>
>> Regards
>>
>> --Erika
>>
>> Sent via Deja.com http://www.deja.com/
>> Before you buy.
>>
>
>
>Sent via Deja.com http://www.deja.com/
>Before you buy.


Article: 25791
Subject: Re: Simon , decoupling caps
From: Bob Perlman <bobperl@best_no_spam_thanks.com>
Date: Wed, 20 Sep 2000 07:40:26 -0700
Links: << >>  << T >>  << A >>
Hi - 

On Wed, 20 Sep 2000 09:27:12 GMT, eml@riverside-machines.com.NOSPAM
wrote:

>On Sat, 16 Sep 2000 12:44:52 -0700, Bob Perlman
><bobperl@best_no_spam_thanks.com> wrote:
>
>>Hi - 
>>
>>Some good papers on decoupling can be found at:
>>
>>http://www.qsl.net/wb6tpu/si_documents/docs.html
>
>Thanks for the link. The fourth paper in the list is "Decoupling
>capacitor calculations", and its one that I read a couple of years
>ago; I haven't read the others.
>
>However, without wishing to be offensive, I have to say that this
>paper is just plain wrong. 

<technical discussion deleted>

>It would be interesting to hear from anyone else who's read this paper
>and has a view on it.
>
>Evan  

Or you could go to the signal integrity reflector and ask Larry Smith
directly.  He's been very willing to discuss the things he's written
and posted.  Post your critique of his article...and stand back.  

To subscribe to the  si-list, send e-mail to
majordomo@silab.eng.sun.com. In the BODY of message put: SUBSCRIBE
si-list

Bob Perlman

Article: 25792
Subject: Re: VHDL to SCHEMATIC
From: Phil James-Roxby <phil.james-roxby@xilinx.com>
Date: Wed, 20 Sep 2000 09:03:45 -0600
Links: << >>  << T >>  << A >>
erika_uk@my-deja.com wrote:
> 
> hi,
> 
> can F2.1i generate the schematic from vhdl (or edif) entry.
> If no, is there any tool which does so

Yes, but a guarded yes.  Its in the schematic entry tool, File ->
Generate schematic from netlist.  It accepts a variety of netlist
formats, one of which is EDIF.  The schematics it produces are not
particularly easy on the eye.
Generating the schematic from vhdl directly is a little more difficult. 
After synthesis of course you can perform the same trick as above, as
you now have an EDIF netlist.  However, many of the names will be
mangled/computer generated.
Synplify will also give you a circuit view and something they call a
technology view from the VHDL.  I used to use this tool a lot when I
taught courses, as its possible to interactively probe the circuit,
which then highlights the line(s) of VHDL which gave rise to the
inference of that part of the circuit.  Great for newbies.
Phil
-- 
---------------------------------------------------------------------
 __
/ /\/  Dr Phil James-Roxby         Direct Dial: 303-544-5545
\ \    Staff Software Engineer     Fax: Unreliable use email :-)
/ /    Loki/DARPA                  Email: phil.james-roxby@xilinx.com
\_\/\  Xilinx Boulder                 
---------------------------------------------------------------------
Article: 25793
Subject: Re: Virtex 'shutdown' phenomenon
From: "Martin.J Thompson" <Martin.J.Thompson@trw.com>
Date: Wed, 20 Sep 2000 08:22:11 -0700
Links: << >>  << T >>  << A >>
If you have enough positive or negative overshoot on a signal, I think you can forward bias the substrate diodes enough to latch the whole chip up.  I've certainly seen something like this happen to an Altera device, which was fixed by making its outputs slow slew-rate.  Soundsl ike that might not be an option for you!
It only takes one I/O to do this, so maybe you have some marginal termination problem?  Sounds like you'll have a great time tracking it down if that is the problem!

Hope that helps,
Martin



TRW Automotive Advanced Product Development,         
Stratford Road, Solihull, B90 4GW. UK
Tel: +44 (0)121-627-3569 
mailto:martin.j.thompson@trw.com


>>> news@rtrussell.co.uk 13 September 2000 12:20:12 >>>
 Message from the Deja.com forum: 
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We are experiencing a peculiar phenomenon with a Virtex
part (XCV600) which has us stumped.  Initially,
following configuration, all is well and the part works
exactly as it should.  However, a variable amount of
time later (sometimes as little as a fraction of a
second, sometimes as much as half an hour) the part
stops working, the current drawn drops considerably
(as if the clock has stopped, or there are no data
transitions) and all the outputs stick at logic '0',
although the DONE line remains high.  Even outputs
which are complementary in normal operation go low
together.

The time it takes before the failure occurs is very
data-dependent.  We can influence this period by
changing the input data (digital video) from having
few transitions - in which case it survives longer -
to having many transitions - in which case it runs
for only a short time.  Cooling the chip increases
the time for which it runs with a given input.

All the inputs and power supplies seem to be OK, and
there is good decoupling on the power rails.  Once the
fault has occurred the only way of restoring correct
operation is to re-configure the chip.  Is this effect
consistent with the chip losing its configuration data,
and if so why should this be happening?  Are there any
other stable, but non-functioning, states which can
be activated by ground-bounce or other data-dependent
triggers ? 

Richard Russell
http://www.rtrussell.co.uk/ 



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Article: 25794
Subject: Re: VHDL to SCHEMATIC
From: "Jamie Sanderson" <jamie@nortelnetworks.com>
Date: Wed, 20 Sep 2000 12:24:51 -0400
Links: << >>  << T >>  << A >>
"Phil James-Roxby" <phil.james-roxby@xilinx.com> wrote in message
news:39C8D1D1.1FA8D97D@xilinx.com...
> Synplify will also give you a circuit view and something they call a
> technology view from the VHDL.  I used to use this tool a lot when I
> taught courses, as its possible to interactively probe the circuit,
> which then highlights the line(s) of VHDL which gave rise to the
> inference of that part of the circuit.  Great for newbies.

I'd have to disagree with you there/add something. These tools are great
when you're trying to coax specific synthesis results from your code (i.e.
you want particular FPGA resources to be used). It's much easier to view
this in a schematic than parsing an EDIF file.

It's also of major use when you take on someone else's design with a complex
hierarchical structure.

So, it's not only good for newbies!

Cheers,
Jamie


Article: 25795
Subject: Re: FPGA Express Strikes Again!
From: Andy Peters <"apeters <"@> n o a o [.] e d u>
Date: Wed, 20 Sep 2000 09:46:20 -0700
Links: << >>  << T >>  << A >>
Vikram Pasham wrote:
> 
> Andy,
> 
> I just wanted to update you on this FPGA Express bug.
> We already filed a CR (Change Request) and Synopsys is looking into this
> issue.
> 
> If a Spartan/ 4K design is using both rising  and falling edge clocks, the
> clock must be inverted using CLB clock muxes CLKX or CLKY. In IOBs, it is
> supposed to use OKMUX. Unfortunately
> FPGA Express isn't using these muxes, its using a LUT to invert the clock. A
> workaround would be to
> instantiate negative edge flops like FDC_1, FDCE_1 etc.
> 
> This will be fixed in the future versions of the software.

Does that mean a patch is "imminent," or is this Microsoft Parlance for
"maņana"?  Took 'em quite awhile to go from FPGA Express v3.3 to 3.4, as
I recall...
-- 
----------------------------
Andy Peters
Sr. Electrical Engineer
National Optical Astronomy Observatory
950 N Cherry Ave
Tucson, AZ 85719
apeters (at) n o a o [dot] e d u
Article: 25796
Subject: Re: Complaint: Xilinx functional simulation libraries
From: Andy Peters <"apeters <"@> n o a o [.] e d u>
Date: Wed, 20 Sep 2000 09:49:35 -0700
Links: << >>  << T >>  << A >>
Joel Kolstad wrote:
> 
> "K. Orthner" <korthner@hotmail.nospam.com> wrote in message
> news:8FAEA273Dkorthnerhotmailcom@158.202.232.7...
> > Joel, I'm not sure about this, but won't turning off the "timing checks
> on"
> > generic only disable the timing checks?  What it won't do is prevent the
> > instantiated components from having delays.
> >
> > Or am I mistaken here?
> 
> Ummm... that's a very good question.  I'm off in this nasty place known as
> San Jose at the moment, but from recollection... I think you're right that
> the instantiated components will still have delays, but I also think that
> turning timing checks off will solve Andy's original problem in that it's
> the timing check that's causing everything to be one clock off in the first
> place.
> 
> Hopefully someone else can chime in to confirm this.  With my design,
> turning timing checks off made everything "work," but there definitely is
> still a 100ps delay on a ClkBufGDLL that is instantiated.

Joel,

Disabling the timing checks does NOT eliminate the 100 ps (actually,
0.10 ns, which you might think would be the same thing, but you'd be
wrong) delay.  If you look closely at the model, there's a wire delay
for all of the input signals (but not the clock); that delay does not go
away if you disable timing checks.

-- a
----------------------------
Andy Peters
Sr. Electrical Engineer
National Optical Astronomy Observatory
950 N Cherry Ave
Tucson, AZ 85719
apeters (at) n o a o [dot] e d u
Article: 25797
Subject: Re: FPGA compiler abort 219
From: Vikram Pasham <Vikram.Pasham@xilinx.com>
Date: Wed, 20 Sep 2000 10:11:36 -0700
Links: << >>  << T >>  << A >>
Reynald,

These abort  errors are typically due to out of memory issues.  If the
design has multiple
HDL modules, compile each separately to see if one in particular causes
the problem.

Often, the cause is a looping construct within the HDL source.  If a
design contains
nested or complex FOR loops or GENERATE statements, expand these
constructs
manually and resynthesize.

Synopsys has fixed most of these  memory issues in FPGA Compiler-II
v3.4. Are you using the latest
FC-II 3.4?


-Vikram Pasham
Xilinx Applications



Reynald Pireyre wrote:

> HI
> I use FPGA compiler II, (target xilinx)
> All VHDL source has been compiled.
> But during  elaborating on Xilinx target, the soft crash.
> And report file is not available , only "abort at 219" !!!!
> You know this problem
> thanks
> reynald

Article: 25798
Subject: Re: Boundary scan
From: "Alain Cloet" <alaincloet@hotmail.com>
Date: Wed, 20 Sep 2000 19:25:15 +0200
Links: << >>  << T >>  << A >>

"sergio oyaga" <larrion@euskalnet.net> wrote in message
news:39C1514E.5375BBD2@euskalnet.net...
>
> I'm a student of Mondragon University and Iīm working with Xilinx
> Foundation. I want to practice boundary scan, and I donīt know if I can
> do it with a Paralle Download III cable.

I don't think the cable will be the problem.  I'm not sure the Foundation-SW
gives you the flexibility you might need (I only used it to program, for
which it's good, but it depends on what you need to do).
Like Dave Miller already said, TI has a simulation tool (comes with some
other educational software to learn the basics in a theoretical way).  I can
only recommend this tool, it's something really usefull...

HTH,
Alain




Article: 25799
Subject: Re: VHDL to SCHEMATIC
From: erika_uk@my-deja.com
Date: Wed, 20 Sep 2000 18:58:25 GMT
Links: << >>  << T >>  << A >>
Hi,

Thanks to you all.
I have tried with F2.1. But it was really bad. even for very small
design, it has been splitted in many schematic pages.Also it does not
show the hierarchy Is there any setting that i may be missing ?

I have not heared before about viewgen, but is there any free viewer

Regards

--Erika


In article <xU3y5.27856$Z2.397003@nnrp1.uunet.ca>,
  "Eric Pearson" <ecp@focus-systems.nospam.on.ca> wrote:
> Hi Erika...
>
> I've used Viewgen (came with Viewdraw) to do this.
> Not the most pretty schematics, but helpful.
>
> Eric
>
> erika_uk@my-deja.com wrote in message <8q8luu$j7o$1@nnrp1.deja.com>...
> >sorry, i wanted to say edif .
> >
> >In article <8q8lqb$iu3$1@nnrp1.deja.com>,
> >  erika_uk@my-deja.com wrote:
> >> hi,
> >>
> >> can F2.1i generate the schematic from vhdl (or edif) entry.
> >> If no, is there any tool which does so
> >>
> >> Regards
> >>
> >> --Erika
> >>
> >> Sent via Deja.com http://www.deja.com/
> >> Before you buy.
> >>
> >
> >
> >Sent via Deja.com http://www.deja.com/
> >Before you buy.
>
>


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