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Messages from 25975

Article: 25975
Subject: Re: Synplicity vs Xilinx FPGA Express
From: Muzaffer Kal <muzaffer@dspia.com>
Date: Thu, 28 Sep 2000 15:52:01 GMT
Links: << >>  << T >>  << A >>
On Wed, 27 Sep 2000 21:56:00 -0700, Netscape User
<your_email@here.net> wrote:

>I'll soon be working on a Xilinx Virtex-300 prototyping board (I huge
>step up from my Xess XS40-010XL!) 
>
>I know that Xilinx's Foundation Express 2.x/3.x uses a licensed version
>of Synopsys FPGA Expresss to handle HDL synthesis.  I'm also aware that
>designers can optionally configure their own software tools for
>synthesis.  For example, use Synplicity to do synthesis, then let
>Xilinx's place/route software deal with the resulting gate netlist. 
>
>What advantages does a third-party (Synplicity or other) HDL synthesis
>tool offer over the 'stock' Xilinx FPGA-Express?  I really don't have a
>need for optimal synthesis, as I'm using the FPGA board to simulate the
>functionality of ASIC design.  (The final code is headed to a ASIC
>standard-cell process.)  
>
>but still, just for my enlightenment...

Are you also using the Avnet board ? I am using it to help a customer
verify a processor before ASIC. Nice system.

If you are doing ASIC prototyping, Synplicity is more important than
ever. It has much better capacity and speed. Also if you want to get
any fpga speed near your ASIC constraint, you have to use the best
fpga synthesis tool. It's has been quite a while since I evaluated all
three tools, (synplify, exemplar leonardo and fpga express) but I
still run the other two every once in  a while. I think synplify is
still the best tool both in QOR and speed terms.

Muzaffer

Article: 25976
Subject: Re: FPGA Express pb
From: Klaus Falser <kfalser@durst.it>
Date: Thu, 28 Sep 2000 15:58:05 GMT
Links: << >>  << T >>  << A >>
In article <8qv3i5$l9k$1@reader1.fr.uu.net>,
  "Marc Battyani" <Marc.Battyani@fractalconcept.com> wrote:
> I have this :
> entity US1 is port (
> ...
>     DDSFSK        : out std_logic;
> ...
> ); end US1;
>
> and then
>
> DDSFSK <= '1';
>
> Seems easy for me, but FPGA Express gives me :
>
> Error: Cannot isolate ports with direction 'INOUT' on net 'DDSFSK'.
> (FPGA-DRCFIX-1)
>
> If I put DDSFSK <= '0'; instead of DDSFSK <= '1'; it works.
>
> Any clue ? I don't have any other use of this signal in the design.
>
> Thanks
>
> Marc Battyani
>
>

The error is related to the net '1' not to the net DDSFSK.
You must have assigned '1' to both an OUT port as to an INOUT port.

In my opinion this is a (small) bug in FPGA Express,
since the following example will not be accepted.

 entity test is

     port (
         O1  : out    std_logic;
         O2  : out    std_logic;
         O3   : inout std_logic);

 end entity test;

 architecture Test_arch of test is

 begin  -- architecture Test_arch

      O1 <= '1';
      O2 <= O3;
      O3 <= '1';

 end architecture Test_arch;


--
Klaus Falser
Durst Phototechnik AG
I-39042 Brixen


Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 25977
Subject: Re: FPGA Express pb
From: "Marc Battyani" <Marc.Battyani@fractalconcept.com>
Date: Thu, 28 Sep 2000 19:29:40 +0200
Links: << >>  << T >>  << A >>

"Klaus Falser" <kfalser@durst.it> wrote in message
news:8qvpq8$7rd$1@nnrp1.deja.com...
> The error is related to the net '1' not to the net DDSFSK.
> You must have assigned '1' to both an OUT port as to an INOUT port.
>
> In my opinion this is a (small) bug in FPGA Express,
> since the following example will not be accepted.
>
>  entity test is
>
>      port (
>          O1  : out    std_logic;
>          O2  : out    std_logic;
>          O3   : inout std_logic);
>
>  end entity test;
>
>  architecture Test_arch of test is
>
>  begin  -- architecture Test_arch
>
>       O1 <= '1';
>       O2 <= O3;
>       O3 <= '1';
>
>  end architecture Test_arch;

Very good explanation!
As I've told in another post I've found that it appened when setting another
signat to '1' and I couldn't figure out why.

Are there other small bugs like this in FPGA Express ?

Thanks

Marc Battyani



Article: 25978
Subject: Re: Difference between Foundation Base and Foundation ISE Base Express?
From: Carl Rohrer <carl.rohrer@xilinx.com>
Date: Thu, 28 Sep 2000 13:34:04 -0600
Links: << >>  << T >>  << A >>
Eric,

Anything with the word Express in it includes FPGA Express, which is
Synopsys' synthesizer.  Unless you have a different synthesizer, you'll want
to get Base Express.  There are a number of different software packages
available; they all come with the xilinx implementation tools but here the
basic differences:

Alliance - back end tool only.  You can use a 3rd party synthesizer of your
choice but it is not provided.
Foundation (Base, Standard, Elite) -  Alliance plus aldec schematic front
end tool.
Foundation (Base, Standard, Elite) Express - Same as Foundation but includes
FPGA Express.
Foundation ISE - Different gui, XST synthesizer, FPGA Express.  Has the look
and feel of Webpack.

Carl


Eric Smith wrote:

> Does anyone have a simple explanation of the differences between
> Foundation Base ($1090) and Foundation ISE Base Express ($695)?
> They both seem to support the same devices (except for the XC3000 and
> XC5200 series)?  Does Foundation Base not support VHDL?
>
> And how do those packages compare to the student edition 2.1i, which
> Amazon lists for $55?  I can't even *find* a supported device list
> for the student edition.
>
> The Xilinx marketing people must have worked long hours and legal
> holidays to make sure that it's difficult to get useful information from
> their web site.  They reference comparison charts that are "currently
> not available."
>
> I want to do VHDL design using Spartan and Spartan II parts, and I'd
> like to get started as cheaply as possible.

Article: 25979
Subject: Re: ABEL truth table for 8-1 Mux (The solution)
From: Jim Granville <jim.granville@designtools.co.nz>
Date: Fri, 29 Sep 2000 07:55:19 +1200
Links: << >>  << T >>  << A >>
Alan Horton wrote:
> 
> I found out that all I needed to do was expand the inputs and to enter the
> "dont cares" in my truth table as .X. instead of just X
> 

Abel code often has this alias included:

        H,L,C,X         = 1,0,.C.,.X.;  "test vector charactors

try this with your original code.

> The truth table is:-
> 
> TRUTH_TABLE
> ([C2,C1,C0,A7,A6,A5,A4,A3,A2,A1,A0] -> [D])
> [0,0,0,.X.,.X.,.X.,.X.,.X.,.X.,.X.,0] -> [0];
> [0,0,0,.X.,.X.,.X.,.X.,.X.,.X.,.X.,1] -> [1];

-jg
Article: 25980
Subject: Re: hdl
From: "Alun" <alun101@DELETEtesco.net>
Date: Thu, 28 Sep 2000 22:01:05 +0100
Links: << >>  << T >>  << A >>
> so if I only do a small
> design it makes more sense for me to put it in discrete logic. I also
wonder
> if anyone has knowledge of putting part of the logic outside the fpga to
> reduce fpga size? (counters, shift-registers)

If your design is small what's wrong with CPLDs eg xc95XX or Altera 7000
series etc. etc.? That would be a hell of a lot more convenient than TTL.


Alun
Camdigital


Article: 25981
Subject: some question about synplify tool
From: "緡_YLKIM" <kyl1214@netian.com>
Date: Fri, 29 Sep 2000 09:18:13 +0900
Links: << >>  << T >>  << A >>

I have r600 & r531. but I need r514 version.

If you problem to send mail, let me know where is it.

Thank you.

PS: I tried for find r514 in synplicity web-site but i can't find.


Article: 25982
Subject: Re: some question about synplify tool
From: "S. Ramirez" <sramirez@deleet.cfl.rr.com>
Date: Fri, 29 Sep 2000 02:10:11 GMT
Links: << >>  << T >>  << A >>
     Why can't you just email Synplicity directly, since they are the keeper
of their software?
-Simon Ramirez, Consultant
 Synchronous Design, Inc.



"緡_YLKIM" <kyl1214@netian.com> wrote in message
news:8r0m5q$n7g$1@news1.kornet.net...
>
> I have r600 & r531. but I need r514 version.
>
> If you problem to send mail, let me know where is it.
>
> Thank you.
>
> PS: I tried for find r514 in synplicity web-site but i can't find.
>
>
>


Article: 25983
Subject: FPGA development on the cheap?
From: snyderkena@my-deja.com
Date: Fri, 29 Sep 2000 02:55:00 GMT
Links: << >>  << T >>  << A >>
I am interested in teaching myself how to implement digital systems
using FPGAs.  The idea is to make this a home project where I would
convert my schematic to the appropriate bit stream to be downloaded to
a development board.

I realize that I will have to spend $$ for a board and FPGA, but are
there any free software tools?  I realize the tradeoff between $$ and
ease.  I am not committed to a particular FPGA, and free tools would
weigh heavily.

Any comments or suggestions?

-Ken


Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 25984
Subject: Re: FPGA development on the cheap?
From: Dave Vanden Bout <devb@xess.com>
Date: Thu, 28 Sep 2000 23:28:41 -0400
Links: << >>  << T >>  << A >>
> I am interested in teaching myself how to implement digital systems
> using FPGAs.  The idea is to make this a home project where I would
> convert my schematic to the appropriate bit stream to be downloaded to
> a development board.
>
> I realize that I will have to spend $$ for a board and FPGA, but are
> there any free software tools?  I realize the tradeoff between $$ and
> ease.  I am not committed to a particular FPGA, and free tools would
> weigh heavily.
>
> Any comments or suggestions?

You can try the Xilinx WebPACK software.  It is free and lets you create
designs for XC9500 CPLDs and CoolRunner CPLDs.  You can enter designs in
VHDL, Verilog, as schematics, or use the state machine editor.  My company
has a tutorial that will show you how to download, install, and use
WebPACK at http://www.xess.com/manuals/webpack-3_1.pdf.

You can also check http://www.optimagic.com for lists of free design
software, programmable logic tutorials, and FPGA/CPLD board vendors.

--
|| Dr. Dave Van den Bout   XESS Corp.               (919) 387-0076 ||
|| devb@xess.com           2608 Sweetgum Dr.        (800) 549-9377 ||
|| http://www.xess.com     Apex, NC 27502 USA   FAX:(919) 387-1302 ||


Article: 25985
Subject: Re: FPGA development on the cheap?
From: "Wolfgang Loewer" <wolfgang.loewer@elca.de>
Date: Fri, 29 Sep 2000 10:06:26 +0200
Links: << >>  << T >>  << A >>
Ken,
check out the DIGILAB 10K10 at
http://www.elca.de/Products/prod%20d10k10e.html. It's got everything you
need, including download hardware and a free, yet powerful and popular
version of MAX+plus II from Altera. There are many Universities using this
platform for their courses.
Should be affordable ouside Europe, given the current weakness of the EURO
;-)

You might also want to check the boards sections that most PLD manufacturers
have on their web sites:
Xilinx: http://www.xilinx.com/products/protoboards/protoboards.htm
Altera: http://www.altera.com/html/mega/boards.html

- Wolfgang

_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/
Wolfgang Loewer - El Camino GmbH
Your Programmable Logic Design House
http://www.elca.de
_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/

<snyderkena@my-deja.com> wrote in message
news:8r10a2$7ms$1@nnrp1.deja.com...
> I am interested in teaching myself how to implement digital systems
> using FPGAs.  The idea is to make this a home project where I would
> convert my schematic to the appropriate bit stream to be downloaded to
> a development board.
>
> I realize that I will have to spend $$ for a board and FPGA, but are
> there any free software tools?  I realize the tradeoff between $$ and
> ease.  I am not committed to a particular FPGA, and free tools would
> weigh heavily.
>
> Any comments or suggestions?
>
> -Ken
>
>
> Sent via Deja.com http://www.deja.com/
> Before you buy.


Article: 25986
Subject: Re: FPGA development on the cheap?
From: "Ulf Samuelsson" <ulf@atmel.spammenot.com>
Date: Fri, 29 Sep 2000 13:21:14 +0200
Links: << >>  << T >>  << A >>
Or you may want to check out the Atmel STK40.
It has a 20 k gate FPGA and a socket for an AVR uP.
There is a complete toolkit included (except for simulator)
You may be able to get hold of a Veriwell verilog simulator
(which somewhat works in a <1000 lines) or someting else here.


--
Best regards,
ulf at atmel dot com
The contents of this message is intended to be my private opinion and
may or may not be shared by my employer Atmel Sweden

<snyderkena@my-deja.com> wrote in message
news:8r10a2$7ms$1@nnrp1.deja.com...
> I am interested in teaching myself how to implement digital systems
> using FPGAs.  The idea is to make this a home project where I would
> convert my schematic to the appropriate bit stream to be downloaded to
> a development board.
>
> I realize that I will have to spend $$ for a board and FPGA, but are
> there any free software tools?  I realize the tradeoff between $$ and
> ease.  I am not committed to a particular FPGA, and free tools would
> weigh heavily.
>
> Any comments or suggestions?
>
> -Ken
>
>
> Sent via Deja.com http://www.deja.com/
> Before you buy.


Article: 25987
Subject: Re: FPGA development on the cheap?
From: "Ulf Samuelsson" <ulf@atmel.spammenot.com>
Date: Fri, 29 Sep 2000 13:31:18 +0200
Links: << >>  << T >>  << A >>
Or you may want to check out the Atmel STK40.
It has a 20 k gate FPGA and a socket for an AVR uP.
There is a complete toolkit included (except for simulator)
You may be able to get hold of a Veriwell verilog simulator
(which somewhat works in a <1000 lines) or someting else here.


--
Best regards,
ulf at atmel dot com
The contents of this message is intended to be my private opinion and
may or may not be shared by my employer Atmel Sweden

<snyderkena@my-deja.com> wrote in message
news:8r10a2$7ms$1@nnrp1.deja.com...
> I am interested in teaching myself how to implement digital systems
> using FPGAs.  The idea is to make this a home project where I would
> convert my schematic to the appropriate bit stream to be downloaded to
> a development board.
>
> I realize that I will have to spend $$ for a board and FPGA, but are
> there any free software tools?  I realize the tradeoff between $$ and
> ease.  I am not committed to a particular FPGA, and free tools would
> weigh heavily.
>
> Any comments or suggestions?
>
> -Ken
>
>
> Sent via Deja.com http://www.deja.com/
> Before you buy.




Article: 25988
Subject: Re: FPGA development on the cheap?
From: "Ulf Samuelsson" <ulf@atmel.spammenot.com>
Date: Fri, 29 Sep 2000 13:31:24 +0200
Links: << >>  << T >>  << A >>
Or you may want to check out the Atmel STK40.
It has a 20 k gate FPGA and a socket for an AVR uP.
There is a complete toolkit included (except for simulator)
You may be able to get hold of a Veriwell verilog simulator
(which somewhat works in a <1000 lines) or someting else here.


--
Best regards,
ulf at atmel dot com
The contents of this message is intended to be my private opinion and
may or may not be shared by my employer Atmel Sweden

<snyderkena@my-deja.com> wrote in message
news:8r10a2$7ms$1@nnrp1.deja.com...
> I am interested in teaching myself how to implement digital systems
> using FPGAs.  The idea is to make this a home project where I would
> convert my schematic to the appropriate bit stream to be downloaded to
> a development board.
>
> I realize that I will have to spend $$ for a board and FPGA, but are
> there any free software tools?  I realize the tradeoff between $$ and
> ease.  I am not committed to a particular FPGA, and free tools would
> weigh heavily.
>
> Any comments or suggestions?
>
> -Ken
>
>
> Sent via Deja.com http://www.deja.com/
> Before you buy.




Article: 25989
Subject: Re: FPGA development on the cheap?
From: "Ulf Samuelsson" <ulf@atmel.spammenot.com>
Date: Fri, 29 Sep 2000 13:31:53 +0200
Links: << >>  << T >>  << A >>
Or you may want to check out the Atmel STK40.
It has a 20 k gate FPGA and a socket for an AVR uP.
There is a complete toolkit included (except for simulator)
You may be able to get hold of a Veriwell verilog simulator
(which somewhat works in a <1000 lines) or someting else here.


--
Best regards,
ulf at atmel dot com
The contents of this message is intended to be my private opinion and
may or may not be shared by my employer Atmel Sweden

<snyderkena@my-deja.com> wrote in message
news:8r10a2$7ms$1@nnrp1.deja.com...
> I am interested in teaching myself how to implement digital systems
> using FPGAs.  The idea is to make this a home project where I would
> convert my schematic to the appropriate bit stream to be downloaded to
> a development board.
>
> I realize that I will have to spend $$ for a board and FPGA, but are
> there any free software tools?  I realize the tradeoff between $$ and
> ease.  I am not committed to a particular FPGA, and free tools would
> weigh heavily.
>
> Any comments or suggestions?
>
> -Ken
>
>
> Sent via Deja.com http://www.deja.com/
> Before you buy.




Article: 25990
Subject: Re: atmel verses altera
From: "Ulf Samuelsson" <ulf@atmel.spammenot.com>
Date: Fri, 29 Sep 2000 13:38:17 +0200
Links: << >>  << T >>  << A >>

<graham_moss@my-deja.com> wrote in message
news:8qub1g$3me$1@nnrp1.deja.com...
> Hello,
> My current project requires the use of a fpga to achieve all the
> associated logic functionality. Simply put the peripherals will
> communicate via a bus internal to the fpga, therefore the fpga will
> contains busses and muxes, registers (may use fpga ram), and contain
> some complex random logic and sequencers.
>
> I have investigated both the Atmel AT40 and the Altera Flex 10K family.
>
> This has left me confused as their architectures seem quite different,
> yet both could ultimately do the job.
>
> Have I missed the point? My question is how to determine which family
> will be better suited to my particular application.


You need to specify your needs.
Key to efficient use of the AT40K is to use the SRAM.
SRAM can be used to implement logic in many different ways.

If you have a design, which has some volume, Atmel can certainly
Place and Route it for you. Send a mail to fpga@atmel.com and ask the
question.

Otherwise you can get the toolset for free at the Atmel website, do a P&R.
The toolset supports timing analysis so you can find out if you
will meet timing spec.

If you need a controller in the design, then the new FPSLIC may
be of interest to you. AVR RISC+ memory + 40K gates FPGA.


--
Best regards,
ulf at atmel dot com
The contents of this message is intended to be my private opinion and
may or may not be shared by my employer Atmel Sweden






Article: 25991
Subject: Re: Synopsys FPGA Compiler II on Solaris
From: =?iso-8859-1?Q?J=F6rg?= Ritter <ritter@informatik.uni-halle.de>
Date: Fri, 29 Sep 2000 17:27:25 +0200
Links: << >>  << T >>  << A >>
Hi Lars,
I'm using the fc2 under solaris2.6 and 2.7 (SunOS 5.6 and 5.7).
No such problems with online help.

Do you get window decorations when using KDE as the window manager ?

ciao
J=F6rg


> Hi folks!
>
> We are using FC2 on SunOS5.8, with either CDE or KDE/Openwin.
> Everything works fine, except the Online Help. When clicking
> the Help -> Topics button, a winhelp process is started, but
> never shows up on the screen. FC2 then stalls forever...
> Has anyone seen this behavior? Workarounds?
>
> The README mentions some problems with the Online Help,
> but the -t or -f switches don't solve it.
>
> Any ideas?
>
> Lars
> --
> Address:  University of Mannheim; B6, 26; 68159 Mannheim, Germany
> Tel:      +(49) 621 181-2716, Fax: -2713
> email:    larsrzy@{ti.uni-mannheim.de, atoll-net.de, computer.org}
> Homepage: http://mufasa.informatik.uni-mannheim.de/lsra/persons/lars/

Article: 25992
Subject: Re: FPGA development on the cheap?
From: "Tony Burch" <tony@BurchED.com.au>
Date: Sat, 30 Sep 2000 01:39:29 +1000
Links: << >>  << T >>  << A >>
Burch Electronic Designs sells some low cost, easy to use
FPGA Prototyping Kits.  Xilinx, Altera, Atmel, Lucent and
Actel kits are available.  www.BurchED.com.au
Kit prices start at US$66.  International orders are welcome.

The Altera Max+PlusII Baseline software, which works
with the BED-ALTERA-BASE+ Kit, is free.  Great tool.
You can download it from the Altera website at
www.altera.com

Best regards
Tony Burch
www.BurchED.com.au

snyderkena@my-deja.com wrote in message <8r10a2$7ms$1@nnrp1.deja.com>...
>I am interested in teaching myself how to implement digital systems
>using FPGAs.  The idea is to make this a home project where I would
>convert my schematic to the appropriate bit stream to be downloaded to
>a development board.
>
>I realize that I will have to spend $$ for a board and FPGA, but are
>there any free software tools?  I realize the tradeoff between $$ and
>ease.  I am not committed to a particular FPGA, and free tools would
>weigh heavily.
>
>Any comments or suggestions?
>
>-Ken
>
>
>Sent via Deja.com http://www.deja.com/
>Before you buy.


Article: 25993
Subject: Xilinx Logicore Generator
From: "Manfred Kraus" <newsreply@cesys.com>
Date: Fri, 29 Sep 2000 17:43:05 +0200
Links: << >>  << T >>  << A >>
Implementation of a design( F3.1i SP3) using LogiCore-generated asynchronous
FIFOs (V2.0) fail with error messages like this:

"WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOA0 of
comp
H2/U1/BU0 is not connected."

The Fifos are using Block-Ram and are generated as RPMs.
The target device is Spartan II

Has anybody tried to use LogiCore generated Fifos in Spartan devices ?
Did it work ?



--
Manfred Kraus



Article: 25994
Subject: Re: Xilinx Logicore Generator
From: Muzaffer Kal <muzaffer@dspia.com>
Date: Fri, 29 Sep 2000 16:13:05 GMT
Links: << >>  << T >>  << A >>
On Fri, 29 Sep 2000 17:43:05 +0200, "Manfred Kraus"
<newsreply@cesys.com> wrote:

>Implementation of a design( F3.1i SP3) using LogiCore-generated asynchronous
>FIFOs (V2.0) fail with error messages like this:
>
>"WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOA0 of
>comp
>H2/U1/BU0 is not connected."
>
>The Fifos are using Block-Ram and are generated as RPMs.
>The target device is Spartan II
>
>Has anybody tried to use LogiCore generated Fifos in Spartan devices ?
>Did it work ?

that is a warning and shouldn't cause a failure in implementation. The
warning is normal. Blockrams have two output ports and if in the fifo
you are using one input (write), and one output (read) port, some
ports will be left unconnected. I think there must be something else
to account for the implementation failure.

Muzaffer

Article: 25995
Subject: Xilinx 2.1 to 3.1 pb
From: "Marc Battyani" <Marc.Battyani@fractalconcept.com>
Date: Fri, 29 Sep 2000 18:48:01 +0200
Links: << >>  << T >>  << A >>
I switched from foundation express 2.1 to 3.1 and I my design which was OK
under 2.1 is almost completely optimized out in 3.1 by the map stage.

Section 4 - Removed Logic Summary
---------------------------------
 787 block(s) removed
   2 block(s) optimized away
 765 signal(s) removed

It begins by removing the clock and then almost all the signals and pads in
the design.

Any idea?

Thanks

Marc Battyani



Article: 25996
Subject: Re: Xilinx Logicore Generator
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Fri, 29 Sep 2000 17:55:16 +0100
Links: << >>  << T >>  << A >>


Muzaffer Kal wrote:

> On Fri, 29 Sep 2000 17:43:05 +0200, "Manfred Kraus"
> <newsreply@cesys.com> wrote:
>
> >Implementation of a design( F3.1i SP3) using LogiCore-generated asynchronous
> >FIFOs (V2.0) fail with error messages like this:
> >
> >"WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOA0 of
> >comp
> >H2/U1/BU0 is not connected."
> >
> >The Fifos are using Block-Ram and are generated as RPMs.
> >The target device is Spartan II
> >
> >Has anybody tried to use LogiCore generated Fifos in Spartan devices ?
> >Did it work ?
>
> that is a warning and shouldn't cause a failure in implementation. The
> warning is normal. Blockrams have two output ports and if in the fifo
> you are using one input (write), and one output (read) port, some
> ports will be left unconnected. I think there must be something else
> to account for the implementation failure.
>
> Muzaffer

Or even with both data ports if you need a data width that's not a power of 2.
I've been successfully ignoring these warnings for a long time using 2.1i. Of
coure 3.1i might have uprated the error severity but I would count that as a bug.



Article: 25997
Subject: Re: Xilinx and CD databooks (rant)
From: Joe <ja.NOgallegosSPAM@boeing.com>
Date: Fri, 29 Sep 2000 17:22:36 GMT
Links: << >>  << T >>  << A >>
I've been down that road many time with various tools. What frustrated me the
most was that various tools used various means for documenting their tools or
devices-some used html, some used PDF, some used interleaf(worldview), some use
plain ascii, some used a proprietary database(such as Mentor Graphics Bold
Browser) etc...

Fortunately, years later, most vendors are using PDF to document their tools /
devices. This isn't a panacea, but it does allow one to print the documentation
without wasting much paper. Adobe has ps drivers for most printers that allow you
to print 2 pages up, 4 pages up etc. and on both sides(duplex).

http://www.adobe.com/products/printerdrivers/main.html

Hence a 100 page report would require 13 pages(4 pages up with both sides
printed).

I too like databooks, but PDFs aren't all that bad.

Victor the Cleaner wrote:

> Rant or not, this is the right forum for it, and I can't believe
> that this isn't a bigger issue across our industry.  What scares
> me to death is the possibility that otherwise-intelligent people
> who agree with me are keeping quiet because they're afraid of
> being seen as "resistant to new technology", regardless of how
> misplaced or misapplied that technology might be.  If you agree,
> please circulate freely.
>
> jl
>
> (sent yesterday to databook@xilinx.com and Xilinx's CEO)
>
> I don't know which semi-literate, multimedia-infatuated moron is
> responsible for the so-called "databook on CD" I'm forced to deal
> with right now, but you people had better get over it and get back
> to paper.
>
> I'm a career engineer, and having been in design for 20 years.  If
> you think that makes me some kind of old fart who can't deal with
> the Internet and new media, think again.  I was away from design for
> a couple of years while starting an Internet company, which I still
> operate, and we do work for some pretty big companies with pretty
> modern content.  We also do some pretty challenging software R+D -
> ask around and see if anyone you know has ever heard of an "Internet
> company" with a Cray.
>
> I got back into design a couple of years ago, though, and was disgusted
> to discover the extent to which actual hard-copy data books had been
> replaced by CD distributions, most of them so badly implemented as to
> be unusable.  I understand the positive motivations:  cheaper to produce
> and distribute, more "environmentally friendly", etc., etc.
>
> However, the downside is not worth it.
>
> I started designing with FPGAs (and learning VHDL) about a year ago,
> choosing to use Xilinx because the quality of both the local support
> (via Insight) and the data book were top-notch, and especially helpful
> to a beginning user.  My first design (in Spartan) is now in production
> and I'm working on new designs under Spartan II and Virtex that will
> be in production before the end of the year.
>
> The problem, though, is that your 2000 "data book" is making it
> increasingly difficult and frustrating to use your products.  Imagine
> this:  You go to the tap to get a glass of water.  When you turn the
> handle, though, you have to listen to a fifteen-second fanfare *before*
> any water will come out the spigot.  It might be mildly amusing *once*,
> but EVERY SINGLE TIME?  With no apparent way to disable it?  That's
> how I look at the stupid blinking-boxes screen that opens your CD.
>
> But that's just the beginning.  Your nagware then asks me (every single
> time) whether I want to install your viewer, which I don't now, and likely
> will never wish to.  I tried it once, and installing it took me down more
> useless tangents than I wish to recall.  It asked me whether I wanted to
> use the Internet.  Even though I indicated "No", it screwed with my
> network settings anyway, turning off my modem and switching my connection
> to a LAN, which I don't have at the location where I'm presently working -
> that's why I'm using the modem.  Then it told me the databook was out of
> date.  Then it told me my acrobat reader was out of date.  Then, when I
> pretty much decided "fuck it" and wanted to start up my mailer to send you
> this mail, I had to go screw with the network settings to restore the
> modem connection broken by your viewer application.
>
> In other words, the whole experience SUCKED, taking minutes to fail to
> deliver the information that a real book would have delivered in SECONDS.
>
> Now, it would be easy for you to misinterpret this mail and send my
> complaints, out of context, to your Macromedia-happy multimedia developers
> so that they might tweak and adjust out the the offending behaviours.  That
> would be completely missing the point.  The point is that databooks on CD
> DO NOT, and CAN NOT work as well as paper books.
>
> "So", you say, "just print out the parts you want and don't use the CD."
> That's just a really dumb thing to do, isn't it?  First, being a printer
> isn't my job.  Printing your databook on an average laser printer would
> result in a book on the order of 10 times the size of the paper version
> you should be delivering.  My paper is 8.5x11, yours is 9x7.  My printer
> is single-sided, you print double-sided.  I use heavy, thick bond paper,
> you use much lighter stock.  All of which assumes, of course, that acroread,
> the printer, and whatever other bits happen to be in the path, work properly
> on every page and don't force me to go screw with resolution, etc.  But at
> the end of the day, I'm a design engineer, and I shouldn't be wasting my
> time printing an inferior version of the book it's your responsibility to
> supply me with.
>
> Are you starting to get the message?  I don't want blinking flashing splash
> screens.  I don't want messages from the president.  I don't want propaganda
> on your product line, and I sure as hell don't want spinning logos.  I was
> in the virtual reality business in 91/92 when SIGGRAPH banned spinning logos,
> so you can be sure there's nothing clever about them in the year 2000.
>
> So how about getting with the ticket here, folks?  Intelligent, literate
> designers don't want this crap.  They want books.  Books they can read in
> bed and on the john.  Books they can scribble notes in.  Books they can take
> along for a weekend *away* from the computers.  Books whose pages they can
> flip back and forth between *infinitely* faster than they can with a
> remarkably useless application like acroread (PDF?  Around here that stands
> for "pedofiles").  Books for smart people.
>
> I look forward to your reply.
>
> Jonathan Levine
> Canada Connect Corp.
> Calgary

Article: 25998
Subject: Re: Xilinx 2.1 to 3.1 pb
From: "Marc Battyani" <Marc.Battyani@fractalconcept.com>
Date: Fri, 29 Sep 2000 21:40:42 +0200
Links: << >>  << T >>  << A >>
"Marc Battyani" <Marc.Battyani@fractalconcept.com> wrote in message
news:8r2hti$6gn$1@reader1.fr.uu.net...
> I switched from foundation express 2.1 to 3.1 and I my design which was OK
> under 2.1 is almost completely optimized out in 3.1 by the map stage.
>
Ok, I found out that I was creating a buffer that did not exist in a Spartan
XL => No clock => No design...
It could warn a little bit more anyway.

Marc Battyani





Article: 25999
Subject: Look MOM ... No Hardware
From: Ben Franchuk <bfranchuk@jetnet.ab.ca>
Date: Fri, 29 Sep 2000 22:17:32 +0000
Links: << >>  << T >>  << A >>
Since my Newsgroups have been out for the last few days I missed the first part
> > Daniel Nilsson wrote:
> >
> > > I mean a schematic that tells you how to build the design using ordinary 74
> > > logic. I am a student, and fpga's cost me very much, so if I only do a small
> > > design it makes more sense for me to put it in discrete logic. I also wonder
> > > if anyone has knowledge of putting part of the logic outside the fpga to
> > > reduce fpga size? (counters, shift-registers)

I was planning to do a large project (CPU) in TTL but why I decided against that
was cost of the prototype boards and sockets. $200 for Sockets and prototype
boards. $90 for a FPGA prototype board. I just spent $20 for a small prototype
card from Radio-shack (Stupid store.. they don't carry any Tube radios anymore
:))
and other parts to add on some external memory (64KB)to the prototype card.

Still I like Schematics over other design methods as you can see what
gets connected (Mostly) inside the FPGA.

> >
> > Daniel,
> >     A small FPGA (5000 equivalent gates) circuit can be done for about $15 (US)
> > in parts in single piece quantities.  This assumes a Xilinx XCS05XL and a serial
> > configuration prom.  You do however need a prom programmer.  I happen to like
> > the Atmel reprogrammable proms.  Atmel even has a simple prom programmer circuit
> > on thier web site.  You would be wasting money even in small quantities to pull
> > gates out from the FPGA unless there is some other reason than to cut gate
> > count.
> 
> Xilinx provides a similar very simple circuit for their JTAG parts (such
> as the XC18V serial PROMs), to program them via a parallel port with
> only a couple of very inexpensive components. It looks like a very easy
> way to go.
> 
> http://www.xilinx.com/support/programr/jtag_cable.pdf
> 
> I doubt Xilinx will give away the software, but this should not be too
> difficult to write. I plan to put a similar interface and a parallel
> port connector onto a board I am working on, and will write the software
> (under Linux - at least at first). It may be a couple of months before I
> get to it, but I plan to give away the software when I am finished.
> 

Don't forget Altera, they have a nice FPGA chip and the software is
free and they have cable schematic too.
But if you want to go NO..COST, pickup the Altera or any other free
software and design using TTL macros. Then simulate the the FPGA.
Once you have a design you like then you can build in TTL or a FPGA
chip or just run it as a simulation ."Look Mom...No hardware"
Ben.

-- 
"We do not inherit our time on this planet from our parents...
 We borrow it from our children."
"Luna family of Octal Computers" http://www.jetnet.ab.ca/users/bfranchuk


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