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Messages from 26800

Article: 26800
Subject: Undergraduate PLD Studies
From: "Quin" <NOSPAM@DONTSPAM11235.COM>
Date: Mon, 30 Oct 2000 04:42:26 GMT
Links: << >>  << T >>  << A >>
    I am currently a senior in high school and I am in the process of
applying to universities. My top three choices are (1) Stanford; (2) MIT;
(3) CMU School of Computer Science
    I have just mailed in my application to Stanford for early decision.

    I have been monitoring this group for quite some time and I have been
using the XC4000-series development boards from Xess to develop a real-time
controller for a robot navigation system. I am using two XC4000 FPGA's along
with a PIC to monitor an array of ultrasonic transducers; to implement the
PID control algorithm for the motors; and to compute waypoints to allow the
mobile robot to autonomously traverse the voronoi diagram.

    I am wondering if some of the FPGA gurus out there could express their
views on which colleges are best at educating FPGA engineers. Or,
alternatively, how you were able to acquire your FPGA design know-how. I
know that the FPGA design process is unlike that traditionally followed by
software engineers and programmers; I am wondering whether a program in
Computer Science would provide me with the skills needed to design PLD-based
systems.

Thanks,
---
---
Eser Chamoglu
www.quinnet.com/Personal

If you would like to e-mail me, replace AT with @ and DOT with . from the
following pseudo-address:
quin AT quinnet DOT com



Article: 26801
Subject: Re: Undergraduate PLD Studies
From: David Forbes <dforbes@azspamnet.com>
Date: Sun, 29 Oct 2000 23:50:00 -0700
Links: << >>  << T >>  << A >>
"Quin" <NOSPAM@DONTSPAM11235.COM> wrote:

>     I am currently a senior in high school and I am in the process of
> applying to universities. My top three choices are (1) Stanford; (2) MIT;
> (3) CMU School of Computer Science
>     I have just mailed in my application to Stanford for early decision.
> 
>     I have been monitoring this group for quite some time and I have been
> using the XC4000-series development boards from Xess to develop a 
> real-time
> controller for a robot navigation system. I am using two XC4000 FPGA's 
> along
> with a PIC to monitor an array of ultrasonic transducers; to implement 
> the
> PID control algorithm for the motors; and to compute waypoints to allow 
> the
> mobile robot to autonomously traverse the voronoi diagram.
> 
>     I am wondering if some of the FPGA gurus out there could express 
>     their
> views on which colleges are best at educating FPGA engineers. Or,
> alternatively, how you were able to acquire your FPGA design know-how. I
> know that the FPGA design process is unlike that traditionally followed 
> by
> software engineers and programmers; I am wondering whether a program in
> Computer Science would provide me with the skills needed to design 
> PLD-based
> systems.
> 
> Thanks,
> ---
> ---
> Eser Chamoglu
> www.quinnet.com/Personal
> 
> If you would like to e-mail me, replace AT with @ and DOT with . from the
> following pseudo-address:
> quin AT quinnet DOT com
> 
> 

Eser,

Ahh, youth.

Most of us seasoned FPGA/CPLD/whatever designers weren't privileged to 
have seen FPGAs in college - they didn't exist yet. We had to learn by 
such classics as Designing With TTL Integrated Circuits. The principles 
of digital logic design are the same as back then; it's just the level 
of integration and the clock speed that has changed. Oh, and you had to  
know wire-wrapping to build a prototype in the old days.

If you want to learn about hardware design, you'll need to study 
Electrical and/or Computer Engineering, as that's where hardware is 
taught. Those Computer Science folks don't know which end of a soldering 
iron to pick up (at least they didn't when I was a lad in college).

The best of luck to you wherever you go - looks like you've got quite a 
head start on a degree or two already!

PS. Stanford doesn't get much snow, but I hear that the Rockies are good 
for skiing if you don't mind driving a few hours.

--David Forbes
Tucson AZ

Change spamnet to starnet before replying.

Article: 26802
Subject: Re: Webpack Error?
From: "Tadaaki Koyama" <basaro@fa2.so-net.ne.jp>
Date: Mon, 30 Oct 2000 18:22:16 +0900
Links: << >>  << T >>  << A >>
Thank you, Alex.

I cannot se   XILINX AnswerDatabase #10233, so
I send mail to Japanese XILINX office.
And Patch file is returned.

I can use Webpack.

Thank you very much.

                T.Koyama


"Alex Sherstuk" <sherstuk@iname.com> wrote in message
news:8thmii$n530e$1@ID-27424.news.dfncis.de...
>
> This is a known XILINX software bug, related to Windows "International
> Settings".
> XILINX AnswerDatabase record #10223
> http://support.xilinx.com/techdocs/10223.htm recommends to submit support
> request and to obtain a patch.
> I've done that, and obtained bug fix.
>
> Regards,
>    Alex Sherstuk



Article: 26803
Subject: why?
From: chsw <chen.songwei@mail.zte.com.cn>
Date: Mon, 30 Oct 2000 03:19:53 -0700
Links: << >>  << T >>  << A >>
hello: when i am doing timing simulator(using the reference design xapp205.zip :fifoctlr_ccmw1.v/fifoctlr_ccmw2.v) for a project,the follwoing message occures: "P1/U1/U11/BU0/INTERNAL_BLOCKRAM--READ Violation.Attempt to read from cell that is also being written to." the capacity of the dual block ram i mentioned is 16x1024--64x256,but i replace it with 16x2048---64x512,it is right,and the phenomena of the warning is not . why?

Article: 26804
Subject: Re: Very Lucrative FPGA Jobs
From: Magnus Homann <d0asta@licia.dtek.chalmers.se>
Date: 30 Oct 2000 15:25:06 +0100
Links: << >>  << T >>  << A >>
"S. Ramirez" <sramirez@deleet.cfl.rr.com> writes:

> Come on Magnus, don't you now that he knew this?
> This is part of his poking fun at the guy!
> -Simon Ramirez, Consultant
>  Synchronous Design, Inc.

Bummer, I've been had....

Homann
-- 
Magnus Homann, M.Sc. CS & E
d0asta@dtek.chalmers.se

Article: 26805
Subject: ChipScope, MultiLINX and NT
From: "Mark Hillers" <Mark.Hillers@Informatik.Uni-Oldenburg.DE>
Date: Mon, 30 Oct 2000 18:07:18 +0100
Links: << >>  << T >>  << A >>
Hi all,

I am trying to use XILINX ChipScope with the MultiLINX-Cable. My OS is
Windows NT (SP6), MultiLINX is connected with VCC and GND of the Board
under test and the LED of MultiLINX is turned on. My problem is  I can
not get a serial (COMx) connection to the MultiLINX (even with differend
Baud-rates).
The only answer I get from ChipScope is "Failed to open communication
port".

Has anyone practice using MultiLINX with NT (which I blame at the
moment)?

Thanks
Mark



Article: 26806
Subject: Re: xilinx floor planner issues
From: Kate Meilicke <katem@xilinx.com>
Date: Mon, 30 Oct 2000 13:06:24 -0500
Links: << >>  << T >>  << A >>
There is a way to see the failing paths in FPGA Editor.  If you open the
design
with FPGA Editor, click on Tools, Trace, Setup and Run to get a list
of the worst paths in the constraint.  You can then highlight any of the
paths in the list.

We are working on easier ways showing the critical path.

Kate Meilicke
Xilinx Software Technical Marketing

Muzaffer Kal wrote:

> hi everyone,
> Today I spent a couple of hours looking at placement of
> micro-controller occupying almost 50% of a virtex 800. One thing I
> couldn't figure out how to do is to annotate a critical path from the
> timing analyzer onto the floorplan. I looked at the online help and
> the online description I could find was to open a timing file and add
> individual nets by using the Find command in the floorplan tool. Is
> this really the only way ? I was expecting a much more automated way
> to do this. Basically selecting a number of paths in the timing
> analyzer would just select all the nets involved in the placement by
> unique colors.
> Another problem is that some of the nets in the path have multiple
> destinations, i.e. one register output seems to go to 3 different FGs
> but only one of these paths is on the critical path so after
> ctrl-selecting a couple of lines in the critical path, you are really
> not sure what is the critical path anymore. Is there way to get around
> this ?
> I think Altera's way of linking critical paths to placement is much
> nicer.
>
> Muzaffer
>
> http://www.dspia.com


Article: 26807
Subject: Re: Undergraduate PLD Studies
From: "Austin Franklin" <austin@darkroom89.com>
Date: 30 Oct 2000 19:03:36 GMT
Links: << >>  << T >>  << A >>
If you are Turkish, I believe your name (Eser) means 'masterpiece'?

Anyway, you need to learn digital design, which is basically taught in
computer/electrical engineering programs.  I worked with all three of the
schools you mentioned, and attended one 1/2 of them...and can vouch that
they have excellent mobile robotics programs, which is what my undergrad
and graduate work was in.

Taking a number of advanced programming courses, such as data structures,
compiler design, AI and something dealing with OS architectures would be
beneficial.  I would also recommend crossing over to some ME (Mechanical
Engineering) courses too.  Mobile robotics is one of the most
multidisciplined fields...so just stopping at CS or CE won't really give
you a complete set of disciplines for this field.

One thing to remember, is FPGAs are just a tool...as well as programming
languages, CPUs etc. are...there are underlying disciplines that will let
you become adept at most any engineering 'tool' out there, so don't get
caught up in learning 'one' way of doing things...



Article: 26808
Subject: WebPACK ISE V3.2i is available for immediate download!
From: Richard Chidester <richardc@xilinx.com>
Date: Mon, 30 Oct 2000 13:07:55 -0700
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.
--------------78A790531B2653C89156DE2B
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

Just wanted to make everyone aware that the new WebPACK ISE which adds
support for FPGAs (Spartan II and Virtex 300E) is now available.

Go to http://www.xilinx.com/products/software/webpowered.htm

--------------78A790531B2653C89156DE2B
Content-Type: text/x-vcard; charset=us-ascii;
 name="richardc.vcf"
Content-Transfer-Encoding: 7bit
Content-Description: Card for Richard Chidester
Content-Disposition: attachment;
 filename="richardc.vcf"

begin:vcard 
n:Chidester;Richard
tel;cell:303-882-9077
tel;fax:303-442-9124
tel;home:303-972-8649
tel;work:303-544-5558
x-mozilla-html:TRUE
org:CPLD Software Group;Xilinx, Inc.     <br><img SRC="http://www.xilinx.com/sxpresso/images/webpack_ise_logo.jpg" height=70 width=104><font size=-1><a href=""></a> "The empires of the future are the empires of the mind." <BR><CENTER><I>  ... Winston Churchill</I></font></CENTER>
adr:;;2300 55th Street;Boulder;Colorado;80301;USA
version:2.1
email;internet:richardc@xilinx.com
title:Sr. Technical Marketing Engineer
note;quoted-printable:<br><img SRC=3D"http://webster/images/button.gif" height=3D74 width=3D184><font size=3D-1><a href=3D""></a>"    Yeah.  Free my mind.  Right.  No problem.=0D=0A   "  <BR><CENTER><I>   ...  (Neo -  in The Matrix)</I>=0D=0A</font></CENTER> 
fn:Richard Chidester
end:vcard

--------------78A790531B2653C89156DE2B--


Article: 26809
Subject: Re: Undergraduate PLD Studies
From: Petter Gustad <spam@gustad.com>
Date: 30 Oct 2000 21:47:51 +0100
Links: << >>  << T >>  << A >>
David Forbes <dforbes@azspamnet.com> writes:

> PS. Stanford doesn't get much snow, but I hear that the Rockies are good 
> for skiing if you don't mind driving a few hours.

A little off topic - but you can always go to Tahoe or Mammoth...

Petter
-- 
________________________________________________________________________
Petter Gustad            8'h2B | ~8'h2B            http://www.gustad.com
#include <stdio.h>/* compile/run this program to get my email address */
int main(void) {printf ("petter\100gustad\056com\nmy opinions only\n");}

Article: 26810
Subject: Re: High fan out CE signal.
From: Ray Andraka <ray@andraka.com>
Date: Mon, 30 Oct 2000 20:59:39 GMT
Links: << >>  << T >>  << A >>


Rick Filipkiewicz wrote:
> 
> Ray Andraka wrote:
> 
> > Nope,  That's one of the problems with the VIrtex architecture.  They tell you
> > to use the "low skew routing resource" ie secondary clock network for this, but
> > I find it is way too slow compared to the speed of designs I can do in the
> > part.  The only viable solution I have found is to pipeline the CE's in a
> > distribution tree.
> >
> > Steven Derrien wrote:
> > >
> > > Hello,
> > >
> > > I was wondering if it is possible to use a Virtex BUFG buffer to drive a
> > > non clock signal  ( in my case it is a CE signal with a very heavy
> > > fan-out (all DFF CE ports))
> > >
> > > Steven
> 
> Unusually Ray's no quite right here. I was using this trick to make the domain
> crossing between the main system clock and a 1/2 speed clock formed by a divide by
> 2 FF followed by a BUFG [The ASIC Vendor coudn't emulate Virtex's div2 DLL output].
> What happens is that you get a warning in MAP and the delay from the BUFG output to
> the CE inputs is very much longer than the delay to the clock inputs BUT

True, you can make a kludged connection by connecting through a LUT. I don't
think that it is any faster than using the 'low skew' network, and has a higher
skew.  The low skew network has a pretty good distribution with well controlled
delays.  The problem with it is that it is slow compared to the potential clock
speeds of the device.  As a result, you need many parallel (duplicated) CE
flip-flops, which generally are sourced by a register tree (or by parallel state
machines as someone else pointed out here).

> 
> o Its still not huge. I've just knocked up a test case that shows it to be 1.8-2.6
> nsec against the CLK input delay of 0.59 nsec.
> 
> o Its still bounded in that most of the routing is along the global clock lines so
> that even CE inputs a long way from the global buffer have well controlled delays.
> 
> In the end I had to remove this for the ASIC since the Vendor couldn't [... or
> wouldn't - I'm still not sure which] allow clock tree connections to CE inputs. I
> then used Synplify's automatic register replication mechanism to do the fanout from
> a duplicate of the BUFG input but it was still a lot more hassle.
> 
> Of course even though it works at present Xilinx might always, in their infinite
> wisdom, change it from a warning to an error.

-- 
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com  or http://www.fpga-guru.com

Article: 26811
Subject: Re: Long Island Verilog and VHDL people wanted!!
From: Ray Andraka <ray@andraka.com>
Date: Mon, 30 Oct 2000 21:04:43 GMT
Links: << >>  << T >>  << A >>


Barry Schneider wrote:
> 
> Andy,
>             I'm sorry if your situation makes you so skeptical. This is job
> is real and the work environment is great.  Sometimes we do have deadlines
> so some of us put in extra time. (paid)  We use either Verilog and VHDL
> whichever is dictated by our customer at the time.  We feel if you only know
> one language we can help you learn the other fast enough. Lastly, Synthesis
> is only part of the job we do.  We have synthesis knowledge and will teach a
> worthwhile candidate.  At this point in time good engineers with limited
> experience with ASICS need to be grown from good FPGA design engineers.

!!!! From my perspective, there are a heckuva lot more good ASIC designers than
good FPGA designers out there.  IMHO, design to an ASIC is considerably easier
because you are not constrained by the underlying structure of the device if you
want performance/density or even just efficiency.  Good FPGA designers, if you
can shake them loose, should have no problem at all adjusting to ASICs...the
hardest part being learning all the hoops to jump through for design signoff.

> 
>                 Best of Luck,
>                                     Barry
> 
> "Andy Peters n o a o [.] e d u>" <"apeters <"@> wrote in message
> news:8tcqfk$177a$1@noao.edu...
> > Barry Schneider wrote:
> > >
> > > I am presently working at a ASIC consulting company and we have a huge
> > > backlog of
> > > work.  We need help and will pay well.  We have a great office and have
> > > very flexible hours.   We are looking for Verilog and/or VHDL
> experience.
> > > Synthesis and/or Mixed Signal a plus. If you are interested in a Good
> Job
> > > e-mail me at barry61s@optonline.com
> >
> > Waitaminit.
> >
> > "Flexible hours"?  I guess that means, "arrive at dawn, leave sometime
> > before 9 pm."
> >
> > "Verilog and/or VHDL experience"?  Which one?  Does that mean I get to
> > use VHDL, even if every other engineer in the place is a Verilogger?
> >
> > "Synthesis and/or Mixed Signal a plus"?  Seems to me that an ASIC
> > position would REQUIRE synthesis experience.
> >
> > -- a
> > ----------------------------
> > Andy Peters
> > Sr. Electrical Engineer
> > National Optical Astronomy Observatory
> > 950 N Cherry Ave
> > Tucson, AZ 85719
> > apeters (at) n o a o [dot] e d u
> >
> > "It is better to be silent and thought a fool,
> >  than to send an e-mail to the entire company
> >  and remove all doubt."

-- 
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com  or http://www.fpga-guru.com

Article: 26812
Subject: Re: High fan out CE signal.
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Mon, 30 Oct 2000 23:15:11 +0000
Links: << >>  << T >>  << A >>


Ray Andraka wrote:

> RicTrue, you can make a kludged connection by connecting through a LUT. I don't
> think that it is any faster than using the 'low skew' network, and has a higher
> skew.  The low skew network has a pretty good distribution with well controlled
> delays.  The problem with it is that it is slow compared to the potential clock
> speeds of the device.  As a result, you need many parallel (duplicated) CE
> flip-flops, which generally are sourced by a register tree (or by parallel state
> machines as someone else pointed out here).

Yes but of course when I was doing it in the first half of last year there was no way of
getting at the low skew networks with M1.5. We'd signed off the ASIC before we poor
bloody Europeans got access to 2.1i at the end of September & could use the ``MAXSKEW''
constraint. Anyway IMHO using MAXSKEW or whatever the 3.1 incantation is is a
ridiculously indirect way of getting at such important resources. Why can't Xilinx add a
primitive like the old BUFGS.


Article: 26813
Subject: Xilinix Foundation Question
From: "Qian Zhang" <qianz@cae.wisc.edu>
Date: Mon, 30 Oct 2000 17:51:48 -0600
Links: << >>  << T >>  << A >>
Hi There

When I try to synthesis VHDL file,
when I check check syntax, it always
show me Error, cannot generate report file.
What is wrong with Foundation?

Thank you very much!

Qian



Article: 26814
Subject: Re: How safe is the algorithm implemented with FPGA?
From: Reinoud <dus@casema.net>
Date: Tue, 31 Oct 2000 01:06:08 +0100
Links: << >>  << T >>  << A >>
Peter Alfke wrote:
> 
> eml@riverside-machines.com.NOSPAM wrote:
> 
> > Funny thing is, though, that I was at a seminar two weeks ago, and
> > this wasn't mentioned. I've got 29 pages of slides on Virtex-II, and
> > not one of them mentions a triple-DES block, which isn't the sort of
> > thing you'd accidentally leave out of a presentation.
> >
> 
> It wasn't accidental, it was deliberate. And there are other "goodies"
> that have not yet been divulged (publicly). Give us a some time to file
> all the patents, orchestrate the product introduction, and, last not
> least, characterize the silicon.
> Virtex-II has many novel and exciting features !

Like...  A bitstream specification?  The DES feature will
invalidate the last remaining argument that it is in the user's
interest to keep bitstream details secret. (The old argument being
that secret bitstreams provide for some design protection.)

With the release of Virtex-II documentation, we will finally see who
was right about the motivation of Xilinx for keeping the bitstream
formats secret (see http://www.opencollector.org/news/Bitstream/
(thanks again Graham)).

- Reinoud

Article: 26815
Subject: Re: High fan out CE signal.
From: Ray Andraka <ray@andraka.com>
Date: Tue, 31 Oct 2000 00:59:49 GMT
Links: << >>  << T >>  << A >>
sure would be nice, wouldn't it!

Rick Filipkiewicz wrote:
> 
> Ray Andraka wrote:
> 
> ? RicTrue, you can make a kludged connection by connecting through a LUT. I don't
> ? think that it is any faster than using the 'low skew' network, and has a higher
> ? skew.  The low skew network has a pretty good distribution with well controlled
> ? delays.  The problem with it is that it is slow compared to the potential clock
> ? speeds of the device.  As a result, you need many parallel (duplicated) CE
> ? flip-flops, which generally are sourced by a register tree (or by parallel state
> ? machines as someone else pointed out here).
> 
> Yes but of course when I was doing it in the first half of last year there was no way of
> getting at the low skew networks with M1.5. We'd signed off the ASIC before we poor
> bloody Europeans got access to 2.1i at the end of September ? could use the ``MAXSKEW''
> constraint. Anyway IMHO using MAXSKEW or whatever the 3.1 incantation is is a
> ridiculously indirect way of getting at such important resources. Why can't Xilinx add a
> primitive like the old BUFGS.

-- 
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com  or http://www.fpga-guru.com

Article: 26816
Subject: Re: Undergraduate PLD Studies
From: "S. Ramirez" <sramirez@deleet.cfl.rr.com>
Date: Tue, 31 Oct 2000 03:31:09 GMT
Links: << >>  << T >>  << A >>
-Somewhat off-topic, but the closest mountain range to Stanford that offers
dynamite skiing is the Sierra Nevadas.  The Rockies are a lot of hours away!
-Simon Ramirez, Consultant
 Synchronous Design, Inc.

*****************************************************************
> PS. Stanford doesn't get much snow, but I hear that the Rockies are good
> for skiing if you don't mind driving a few hours.
>
> --David Forbes
> Tucson AZ




Article: 26817
Subject: Re: Long Island Verilog and VHDL people wanted!!
From: "Barry Schneider" <barry61s@optonline.com>
Date: Tue, 31 Oct 2000 03:35:34 GMT
Links: << >>  << T >>  << A >>
Ray,
        I agree FPGA's have many restrictions which make them harder to work
with than ASIC's in some ways. ASICS also have there challenges.  The size
and speed of ASIC's also present interesting problems.  The other point is
that most ASIC's they are NOT reprogramable.  We have had luck with
engineers who are FPGA designers doing ASICS.(me included)  I do feel,
synthesis is more involved with ASIC's than FPGA's due to the speed and
testability issues.
            Barry

"Ray Andraka" <ray@andraka.com> wrote in message
news:39FDE26E.8A9A2413@andraka.com...
>
>
> Barry Schneider wrote:
> >
> > Andy,
> >             I'm sorry if your situation makes you so skeptical. This is
job
> > is real and the work environment is great.  Sometimes we do have
deadlines
> > so some of us put in extra time. (paid)  We use either Verilog and VHDL
> > whichever is dictated by our customer at the time.  We feel if you only
know
> > one language we can help you learn the other fast enough. Lastly,
Synthesis
> > is only part of the job we do.  We have synthesis knowledge and will
teach a
> > worthwhile candidate.  At this point in time good engineers with limited
> > experience with ASICS need to be grown from good FPGA design engineers.
>
> !!!! From my perspective, there are a heckuva lot more good ASIC designers
than
> good FPGA designers out there.  IMHO, design to an ASIC is considerably
easier
> because you are not constrained by the underlying structure of the device
if you
> want performance/density or even just efficiency.  Good FPGA designers, if
you
> can shake them loose, should have no problem at all adjusting to
ASICs...the
> hardest part being learning all the hoops to jump through for design
signoff.
>
> >
> >                 Best of Luck,
> >                                     Barry
> >
> > "Andy Peters n o a o [.] e d u>" <"apeters <"@> wrote in message
> > news:8tcqfk$177a$1@noao.edu...
> > > Barry Schneider wrote:
> > > >
> > > > I am presently working at a ASIC consulting company and we have a
huge
> > > > backlog of
> > > > work.  We need help and will pay well.  We have a great office and
have
> > > > very flexible hours.   We are looking for Verilog and/or VHDL
> > experience.
> > > > Synthesis and/or Mixed Signal a plus. If you are interested in a
Good
> > Job
> > > > e-mail me at barry61s@optonline.com
> > >
> > > Waitaminit.
> > >
> > > "Flexible hours"?  I guess that means, "arrive at dawn, leave sometime
> > > before 9 pm."
> > >
> > > "Verilog and/or VHDL experience"?  Which one?  Does that mean I get to
> > > use VHDL, even if every other engineer in the place is a Verilogger?
> > >
> > > "Synthesis and/or Mixed Signal a plus"?  Seems to me that an ASIC
> > > position would REQUIRE synthesis experience.
> > >
> > > -- a
> > > ----------------------------
> > > Andy Peters
> > > Sr. Electrical Engineer
> > > National Optical Astronomy Observatory
> > > 950 N Cherry Ave
> > > Tucson, AZ 85719
> > > apeters (at) n o a o [dot] e d u
> > >
> > > "It is better to be silent and thought a fool,
> > >  than to send an e-mail to the entire company
> > >  and remove all doubt."
>
> --
> -Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930     Fax 401/884-7950
> email ray@andraka.com
> http://www.andraka.com  or http://www.fpga-guru.com



Article: 26818
Subject: Re: Long Island Verilog and VHDL people wanted!!
From: Ray Andraka <ray@andraka.com>
Date: Tue, 31 Oct 2000 03:54:38 GMT
Links: << >>  << T >>  << A >>
Speed is relative.  A 133 MHz design in a Virtex -4 is considerably more
challenging than a 133 MHz design in an ASIC.  Design for test is admittedly
more of a challenge in ASICs where you don't have the ability to just load in a
test image.  Verification in ASICs is more critical because it can't be changed
later if something comes up wrong, where in an FPGA you can get away with less. 
My point was that the larger granularity of the FPGA architecture makes it more
difficult than an ASIC to do a design that is to perform at some given
percentage of the maximum clock a part is capable of.  Granted, there are issues
in ASICs that you just don't have to deal with in FPGAs such as buffer sizes,
clock tree balancing and the like.  As to the size of the designs, these days
some of the FPGAs are quite capable of designs larger than many of the ASIC
designs going to foundry.  A designer can move either way successfully.  My read
on it is that FPGA designers are in pretty hot demand right now, so I wouldn't
count them as a limitless resource to be diverted to ASCI design.

Barry Schneider wrote:
> 
> Ray,
>         I agree FPGA's have many restrictions which make them harder to work
> with than ASIC's in some ways. ASICS also have there challenges.  The size
> and speed of ASIC's also present interesting problems.  The other point is
> that most ASIC's they are NOT reprogramable.  We have had luck with
> engineers who are FPGA designers doing ASICS.(me included)  I do feel,
> synthesis is more involved with ASIC's than FPGA's due to the speed and
> testability issues.
>             Barry
> 
p://www.andraka.com  or http://www.fpga-guru.com

-- 
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com  or http://www.fpga-guru.com

Article: 26819
Subject: Re: Long Island Verilog and VHDL people wanted!!
From: "Barry Schneider" <barry61s@optonline.com>
Date: Tue, 31 Oct 2000 04:45:23 GMT
Links: << >>  << T >>  << A >>
Ray,
            Thanks for your input.  I enjoyed your feedback.
                        Barry


"Ray Andraka" <ray@andraka.com> wrote in message
news:39FE4282.45BB2F24@andraka.com...
> Speed is relative.  A 133 MHz design in a Virtex -4 is considerably more
> challenging than a 133 MHz design in an ASIC.  Design for test is
admittedly
> more of a challenge in ASICs where you don't have the ability to just load
in a
> test image.  Verification in ASICs is more critical because it can't be
changed
> later if something comes up wrong, where in an FPGA you can get away with
less.
> My point was that the larger granularity of the FPGA architecture makes it
more
> difficult than an ASIC to do a design that is to perform at some given
> percentage of the maximum clock a part is capable of.  Granted, there are
issues
> in ASICs that you just don't have to deal with in FPGAs such as buffer
sizes,
> clock tree balancing and the like.  As to the size of the designs, these
days
> some of the FPGAs are quite capable of designs larger than many of the
ASIC
> designs going to foundry.  A designer can move either way successfully.
My read
> on it is that FPGA designers are in pretty hot demand right now, so I
wouldn't
> count them as a limitless resource to be diverted to ASCI design.
>
> Barry Schneider wrote:
> >
> > Ray,
> >         I agree FPGA's have many restrictions which make them harder to
work
> > with than ASIC's in some ways. ASICS also have there challenges.  The
size
> > and speed of ASIC's also present interesting problems.  The other point
is
> > that most ASIC's they are NOT reprogramable.  We have had luck with
> > engineers who are FPGA designers doing ASICS.(me included)  I do feel,
> > synthesis is more involved with ASIC's than FPGA's due to the speed and
> > testability issues.
> >             Barry
> >
> p://www.andraka.com  or http://www.fpga-guru.com
>
> --
> -Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930     Fax 401/884-7950
> email ray@andraka.com
> http://www.andraka.com  or http://www.fpga-guru.com



Article: 26820
Subject: Virtex Hardware Verification
From: Matthew Fettke <Matthew.Fettke@flinders.edu.au>
Date: Tue, 31 Oct 2000 14:51:01 +0930
Links: << >>  << T >>  << A >>
Hello All,

When I try to program an XCV150 using the JTAG programmer, the 
software is unable to "Initialise Chain".  It says to check the cable
etc, which I have done and found no problems with it.  I can 
successfully program another XCV150 on a completely different board 
using JTAG, so I think that my method is correct.

I would like to verify that the chip is in a working condition, but I 
have no idea how to do this.  It is in the PQ240 package, so I have
relatively easy access to all pins.

What tests are there, if any, that I can run to determine whether the
FPGA has been damaged in any way?

Thanks,

Matt

-- 
------------------------------------------------------
        Matthew Fettke
        PhD Student
        Engineering Building
        School of Informatics and Engineering
        
        Flinders University of South Australia
        GPO Box 2100
        Adelaide S.A. 5001
        Australia

        Email:  Matthew.Fettke@flinders.edu.au
        WWW:  http://www.flinders.edu.au
------------------------------------------------------

Article: 26821
Subject: The Xilinx Design tools for the customly designed SRAM-based FPGA
From: "Bong-Jin Seo" <bjseo@vslab.kaist.ac.kr>
Date: Tue, 31 Oct 2000 15:38:36 +0900
Links: << >>  << T >>  << A >>
Hi all.

I'm novice in the FPGA based design.

In the ASIC approach, by the library setup (by describing the timing , the
logical function, and the power dissipation of customly designed cells in
the some file format), we can use the customly designed library cell in the
synthesis tool(i.g. synopsis).

Similarily, if I have customly designed SRAM-based FPGA block, is there any
possibility to use the Xilinx design tools for technology mapping, P&R, and
timing simulation for the block ?

Thanks in advance.



Article: 26822
Subject: Re: Using previous version as floorplan (2.1i vs 3.1i)
From: news@rtrussell.co.uk
Date: 31 Oct 2000 11:41:57 GMT
Links: << >>  << T >>  << A >>
Ray Andraka <ray@andraka.com> wrote:

: Open the floorplanner on the old design, do a replace all with placement and
: save it. That makes a floorplan file from the automatic place and route
: solution.  

: Then, when you start with a new design, select your saved floorplan as the
: floorplan file for the new design.  As long as hierarchical names are not
: changed, it will work fine in 3.1

I tried that, but it doesn't seem to work.  Even if I
make *no changes at all* to the design, 'map' reports
a large number of "not matched to a frag - ignoring
constraint" warnings, and the resulting build has a
very poor performance compared to the original one 
from which the floorplan was generated.  Some of the
warnings seem to be related to MUXCYs which are used
to generate local logic 0's (as suggested in an earlier
thread).

Richard.
http://www.rtrussell.co.uk/

Article: 26823
Subject: Re: High fan out CE signal.
From: erika_uk@my-deja.com
Date: Tue, 31 Oct 2000 11:43:35 GMT
Links: << >>  << T >>  << A >>
HI RAY,

I am sorry but still having problem

<< As a result, you need many parallel (duplicated) CE flip-flops,
which generally are sourced by a register tree (or by parallel state
machines as someone else pointed out here)>>


what do you mean by register TREE, parallel stae machine..I DON'T SEE
WHY U R USING THE TERM TREE

--Erika




In article <39FDE13E.CA37ADD3@andraka.com>,
  Ray Andraka <ray@andraka.com> wrote:
>
>
> Rick Filipkiewicz wrote:
> >
> > Ray Andraka wrote:
> >
> > > Nope,  That's one of the problems with the VIrtex architecture.
They tell you
> > > to use the "low skew routing resource" ie secondary clock network
for this, but
> > > I find it is way too slow compared to the speed of designs I can
do in the
> > > part.  The only viable solution I have found is to pipeline the
CE's in a
> > > distribution tree.
> > >
> > > Steven Derrien wrote:
> > > >
> > > > Hello,
> > > >
> > > > I was wondering if it is possible to use a Virtex BUFG buffer
to drive a
> > > > non clock signal  ( in my case it is a CE signal with a very
heavy
> > > > fan-out (all DFF CE ports))
> > > >
> > > > Steven
> >
> > Unusually Ray's no quite right here. I was using this trick to make
the domain
> > crossing between the main system clock and a 1/2 speed clock formed
by a divide by
> > 2 FF followed by a BUFG [The ASIC Vendor coudn't emulate Virtex's
div2 DLL output].
> > What happens is that you get a warning in MAP and the delay from
the BUFG output to
> > the CE inputs is very much longer than the delay to the clock
inputs BUT
>
> True, you can make a kludged connection by connecting through a LUT.
I don't
> think that it is any faster than using the 'low skew' network, and
has a higher
> skew.  The low skew network has a pretty good distribution with well
controlled
> delays.  The problem with it is that it is slow compared to the
potential clock
> speeds of the device.  As a result, you need many parallel
(duplicated) CE
> flip-flops, which generally are sourced by a register tree (or by
parallel state
> machines as someone else pointed out here).
>
> >
> > o Its still not huge. I've just knocked up a test case that shows
it to be 1.8-2.6
> > nsec against the CLK input delay of 0.59 nsec.
> >
> > o Its still bounded in that most of the routing is along the global
clock lines so
> > that even CE inputs a long way from the global buffer have well
controlled delays.
> >
> > In the end I had to remove this for the ASIC since the Vendor
couldn't [... or
> > wouldn't - I'm still not sure which] allow clock tree connections
to CE inputs. I
> > then used Synplify's automatic register replication mechanism to do
the fanout from
> > a duplicate of the BUFG input but it was still a lot more hassle.
> >
> > Of course even though it works at present Xilinx might always, in
their infinite
> > wisdom, change it from a warning to an error.
>
> --
> -Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930     Fax 401/884-7950
> email ray@andraka.com
> http://www.andraka.com  or http://www.fpga-guru.com
>


Sent via Deja.com http://www.deja.com/
Before you buy.

Article: 26824
Subject: Re: WebPACK ISE V3.2i is available for immediate download!
From: Santiago de Pablo <sanpab@eis.uva.es>
Date: Tue, 31 Oct 2000 13:07:52 +0100
Links: << >>  << T >>  << A >>
Richard Chidester escribió:
> 
> Just wanted to make everyone aware that the new WebPACK ISE which adds
> support for FPGAs (Spartan II and Virtex 300E) is now available.
> 
> Go to http://www.xilinx.com/products/software/webpowered.htm

Hi folks,

  I've downloaded the WebPACK ISE for PLDs, trying to find a development
environment using VHDL for my students. When I use it I've found a lot
of limits: no more than 21 transitions on the bencher, ...

  I want to know which are the complete *list of limits* of these (free)
products. Hey, Xilinx guys, give our students a really *free* set of
software! (Currently we are using Max+Plus II 7.21 and 9.23).

  Cheers, Santiago.



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