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Messages from 27300

Article: 27300
Subject: Re: Can FPGA perform float point calculation?
From: Ben Franchuk <bfranchuk@jetnet.ab.ca>
Date: Fri, 17 Nov 2000 15:54:43 +0000
Links: << >>  << T >>  << A >>
glen herrmannsfeldt wrote:
> 
> Ray Andraka <ray@andraka.com> writes:
> 
> >My comment that it costs area is in comparison to fixed point.  The driver is
> >mainly the denormalizing and normalizing barrel shifts needed for
> >addition/subtraction.  Multiplication is not much more complex than a fixed
> >point multiplier.  Fortunately, floating point is not really needed in most DSP
> >applications, and where it is needed, you can usually get a way with block
> >floating point or a partial floating point where the operation is done in fixed
> >point with an exponent that is carried around the fixed point part and modified
> >at the output by normalizing the fixed point result.
> 
> If you don't need so many bits for mantissa or exponent, it might not
> be too bad.  Multiply is big in an FPGA, either fixed or floating.
> Divide is even worse, fixed or floating.
> 
> If you did it base 16 (like IBM S/360 and S/370), it would take less
> barrel shift logic.

But the round off errors kill you. Why not just go back to DECIMAL Floating
point.
Ben. 
> -- glen

-- 
"We do not inherit our time on this planet from our parents...
 We borrow it from our children."
"Luna family of Octal Computers" http://www.jetnet.ab.ca/users/bfranchuk

Article: 27301
Subject: Re: Basic question on PLD & FPGA
From: cadmanager@my-deja.com
Date: Fri, 17 Nov 2000 15:58:33 GMT
Links: << >>  << T >>  << A >>
Hi,

PLD (Programmable Logic Device) are generaly use for little application
like adress decoding, little state machine... who don't need many I/Os.
For example you can Use PAL 22V10 to decode ISA adress bus. The
advantage of this technology is : Speed, no Flash EEPROM, very low
cost.

CPLD : Complex Plogrammable Logic Device, are use to design much more,
more complex state machine etc ... Ideal to replace some classic
digital device like 74LS244, 74LS74, multiple adress decoder etc ...
the advantage are : Speed , no FLASH EEPROM. but Low density, poor in
register if we compare to FPGA.

FPGA : Field Programmable Gate Array are the top to do all you want (if
you can afford it) You can do : Very big state machine, bigger Decoder,
CPU Coprocessor, etc ...

So, To retarget a design, you must have some experience about
retargetting. It's not easy to say You can use that or that componant.
It depends on the design.

best regards





In article <3A1438D9.F9C7A7B3@sheffield.ac.uk>,
  "J.Niu" <COP00JN@sheffield.ac.uk> wrote:
> Daniel Hanczewski wrote:
> >
> > Hi all,
> >
> > I am rookie in programmable logic and I have just started getting in
> > this subject.
> > My question is: what is the difference between PLD, CPLD and FPGA?
If I
> > have a logical circuit and want to implement it in programmable chip
> > what circumstances should I consider to choose a proper kind of
chip? Is
> > it so that PLD and CPLD are used for large combinational projects
while
> > FPGA are used for register-based circuits?
> >
> > Thank you in advance.
> > Daniel
>


Sent via Deja.com http://www.deja.com/
Before you buy.

Article: 27302
Subject: XC95288 : Problem using 16 bits counters
From: "Simon Bilodeau" <simon.bilodeau@htrc.com>
Date: Fri, 17 Nov 2000 16:21:04 GMT
Links: << >>  << T >>  << A >>
I use 16 bits counters (CR16CE) macro.  I connected a 1k pull-up at the
counter input.

The problem is when I tie this pin to GND (at the end of a flat ribbon
(5")), the counter begin to increment and when there's activity on this
ribbon the counter increment is greater.

This looks like noise inducted in my counters.


Any idea of what cause that mess?




Article: 27303
Subject: Xilinx config bits
From: John Larkin <jjlarkin@highlandSNIPTHIStechnology.com>
Date: Fri, 17 Nov 2000 08:22:34 -0800
Links: << >>  << T >>  << A >>
Hi,

I have a gadget that uses two XC4010XLs, configured by an MC68332 uP.
The design was done using Foundation 2.1 or something like that; we
build a ROM image with the uP code and two config blocks, which are
themselves built from the .RBT files generated by the Foundation
software. OK so far.

We recently made a small change to one of the FPGAs, and it wouldn't
configure. It turns out that the older .RBT files had 283,424 config
bits, and the new ones (from F3.1 software) have 283,432.

We changed the Xilinx-load subroutine in the uP code, and everything
works fine now.

But why would the number of config bits change?

Go configure!

John


ps: the board is...

http://www.HIGHLANDTECHNOLOGY.com/DSS/V880DS.html

(this is not spam, because the chance of anybody else ever wanting to
buy something this weird is essentially nil.)


Article: 27304
Subject: Re: COREGEN ROM in VHDL... How do I use it?
From: "Olivier Regnault" <olivier.regnault@avnet.com>
Date: Fri, 17 Nov 2000 09:33:28 -0700
Links: << >>  << T >>  << A >>
Have a look to Xilinx Answer Database :
http://support.xilinx.com/support/support.htm
number : 9329 and 8552
You will find examples.

Regards

Olivier
Avnet France

Article: 27305
Subject: Re: Can FPGA perform float point calculation?
From: Ray Andraka <ray@andraka.com>
Date: Fri, 17 Nov 2000 16:36:11 GMT
Links: << >>  << T >>  << A >>
My comment that it costs area is in comparison to fixed point.  The driver is
mainly the denormalizing and normalizing barrel shifts needed for
addition/subtraction.  Multiplication is not much more complex than a fixed
point multiplier.  Fortunately, floating point is not really needed in most DSP
applications, and where it is needed, you can usually get a way with block
floating point or a partial floating point where the operation is done in fixed
point with an exponent that is carried around the fixed point part and modified
at the output by normalizing the fixed point result.  Modern FPGAs have plenty
of room for floating point operations, but it does cost more area so you won't
get as much in as you would with a fixed point implementation. As for the
speeds, if the design is pipelined, the floating point can be as fast as fixed
point except with more clock latency.  Many DSP applications can tolerate very
deep pipelining.  The place where pipelining gets you in trouble is in tight
feedback loops.

Michael Strothjohann wrote:
> 
> Hi,
>     yes, fp is like any other arithmetic.
>     Have in mind, it will be costly in terms of area
>     and speed will be slow, compared to
>     full custom logic
>     ( pentium or any floating-point dsp ).
>     Some applicalions can use piplining.
>     It is worth to do as much as possible
>     in integer arithmetic. It depends on your
>     application, but if it realy needs floating-point,
>     try to use a low-cost floatingpoint dsp
>     ( like 67xx, .. ).
> regards
> michael
> 
> "J.Niu" schrieb:
> 
> > I post a question here... anybody know if fpga support float point
> > calculation? thanx.
> >
> > jy

-- 
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com  or http://www.fpga-guru.com

Article: 27306
Subject: COREGEN ROM in VHDL... How do I use it?
From: Theron Hicks <hicksthe@egr.msu.edu>
Date: Fri, 17 Nov 2000 12:26:08 -0500
Links: << >>  << T >>  << A >>
I have a ROM generated in coregen that I would like to place in my
system.  How do I use the coregen template from the language tools?
Several places in the instructions in the template are not especially
clear.  For example what is the intent of the
-- synopsys translate_off
and
-- synopsys translate_on
comments in the template.

Where exactly do I place the configuration snippet?

-- synopsys translate_off

 for all : rom256x8 use entity
XilinxCoreLib.C_MEM_SP_BLOCK_V1_0(behavioral)
  generic map(
   c_has_en => 0,
   c_rst_polarity => 1,
   c_clk_polarity => 1,
   c_width => 8,
   c_has_do => 1,
   c_has_di => 0,
   c_en_polarity => 1,
   c_has_we => 0,
   c_has_rst => 0,
   c_address_width => 8,
   c_read_mif => 1,
   c_depth => 256,
   c_pipe_stages => 0,
   c_mem_init_radix => 16,
   c_default_data => "FF",
   c_mem_init_file => "rom256x8.mif",
   c_we_polarity => 1,
   c_generate_mif => 0);
 end for;

-- synopsys translate_on

What is the intent of these lines?

--
-- <Insert LIBRARY Declaration here>
--
-- configuration <cfg_my_design> of <my_design> is
--     for <my_arch_name>
--         <Insert CONFIGURATION Declaration here>
--     end for;
-- end <cfg_my_design>;
--
-- If this is not the top-level design then in the next level up, the
following text
-- should appear at the end of that file:
--
-- configuration <cfg> of <next_level> is
--     for <arch_name>
--           for all : <my_design> use configuration <cfg_my_design>;
--           end for;
--     end for;
-- end <cfg>;
--
How do I fill in the various blanks?

Does anyone have an example of code with a functioning coregen part in
it?

Thanks,
Theron Hicks


Article: 27307
Subject: Re: reset pulse ?
From: Ray Andraka <ray@andraka.com>
Date: Fri, 17 Nov 2000 17:41:43 GMT
Links: << >>  << T >>  << A >>
Erika,  

My newreader didn't get your original post.  The flip-flops are all at the
initial value at the end of reconfiguration (generally '0' unless explicity set
to '1' by an init="S", although the FDS, FDSE etc have that init='S' already on
them).  This is basically as if the global reset was applied even though you
don't have the start-up block in your design.  So in answer to your question,
yes the flip-flops do get set to a known state by configuration, and no you
don't need an explicit reset signal to do it.  Note that even though this
methodology works well and is one I subscribe to, it is likely to get any ASCI
designers reviewing your design to scream and jump up and down.

erika_uk@my-deja.com wrote:
> 
> ooh experts, any input here ?
> ray,  where are you hidding !!!!???
> 
> In article <8usdpl$qbl$1@nnrp1.deja.com>,
>   erika_uk@my-deja.com wrote:
> > I forget to add, is there any prefixed from where i can drive it ?
> >
> > In article <8usd7d$pqh$1@nnrp1.deja.com>,
> >   erika_uk@my-deja.com wrote:
> > > hey,
> > >
> > > just basic question. will the reset pulse be
> generated "automatically"
> > > after configuration? can i use this pulse to clear some counters
> > > synchrnously. i don't want to infer the startup because of...(the
> > > famous story)
> > >
> > > thanks
> > >
> > > --Erika
> > >
> > > Sent via Deja.com http://www.deja.com/
> > > Before you buy.
> > >
> >
> > Sent via Deja.com http://www.deja.com/
> > Before you buy.
> >
> 
> Sent via Deja.com http://www.deja.com/
> Before you buy.

-- 
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com  or http://www.fpga-guru.com

Article: 27308
Subject: Re: COREGEN ROM in VHDL... How do I use it?
From: John Ayer <john.ayer@xilinx.com>
Date: Fri, 17 Nov 2000 09:46:48 -0800
Links: << >>  << T >>  << A >>
Hi Thereon,

There is a pretty good solution on this at:
http://support.xilinx.com/techdocs/9329.htm

So just a short overview the tags --synopsys translate_off and on are
there to tell Synopsys not synthesis anything between those tags.  The
reason for this is the code between those tags are only needed for
functional simulation and are read by simulators such as ModelSim.  The
example is shown with Synopsys, and if you are using Synplicity or
Exemplar you would need to use their equivalent of the
on/off tags.  Unless you are going to do functional simulation, you can
leave out what ever falls between the on/off tags.

The solution will explain where an how to use the configuration statements
in your design.  It has some example code included.

Hope this helps,
Regards,
John

Theron Hicks wrote:

> I have a ROM generated in coregen that I would like to place in my
> system.  How do I use the coregen template from the language tools?
> Several places in the instructions in the template are not especially
> clear.  For example what is the intent of the
> -- synopsys translate_off
> and
> -- synopsys translate_on
> comments in the template.
>
> Where exactly do I place the configuration snippet?
>
> -- synopsys translate_off
>
>  for all : rom256x8 use entity
> XilinxCoreLib.C_MEM_SP_BLOCK_V1_0(behavioral)
>   generic map(
>    c_has_en => 0,
>    c_rst_polarity => 1,
>    c_clk_polarity => 1,
>    c_width => 8,
>    c_has_do => 1,
>    c_has_di => 0,
>    c_en_polarity => 1,
>    c_has_we => 0,
>    c_has_rst => 0,
>    c_address_width => 8,
>    c_read_mif => 1,
>    c_depth => 256,
>    c_pipe_stages => 0,
>    c_mem_init_radix => 16,
>    c_default_data => "FF",
>    c_mem_init_file => "rom256x8.mif",
>    c_we_polarity => 1,
>    c_generate_mif => 0);
>  end for;
>
> -- synopsys translate_on
>
> What is the intent of these lines?
>
> --
> -- <Insert LIBRARY Declaration here>
> --
> -- configuration <cfg_my_design> of <my_design> is
> --     for <my_arch_name>
> --         <Insert CONFIGURATION Declaration here>
> --     end for;
> -- end <cfg_my_design>;
> --
> -- If this is not the top-level design then in the next level up, the
> following text
> -- should appear at the end of that file:
> --
> -- configuration <cfg> of <next_level> is
> --     for <arch_name>
> --           for all : <my_design> use configuration <cfg_my_design>;
> --           end for;
> --     end for;
> -- end <cfg>;
> --
> How do I fill in the various blanks?
>
> Does anyone have an example of code with a functioning coregen part in
> it?
>
> Thanks,
> Theron Hicks


Article: 27309
Subject: Re: VHDL & Spartan: How to power-up a Register to '1' ?
From: Ray Andraka <ray@andraka.com>
Date: Fri, 17 Nov 2000 17:53:00 GMT
Links: << >>  << T >>  << A >>
Here's the scoop guys:

YOu can instantiate the FD's in question and, assuming you are using VHDL, put a
user attribute on them to get the initial value:

attribute INIT:string;
attribute INIT of FD1:label is "S";

begin

FD1:FD port map(
...


If you would rather infer them, then you can put global resets in your design
(you'll probably need to put them on all registers) with the flip-flops in
question having a <='1' assignment in the global reset part of the if
construct.  Then connect the global resets either to an ROC component or to '0'
with a keep buffer on the global reset signal (I don't know the syntax for FPGA
express, in synplicity it is a syn_keep attribute):

signal global_reset;
attribute syn_keep:boolean;
attribute syn_keep of global_reset:signal is true;
begin
	global_reset<='0';

	process(clk,global_reset)
	begin
		if global_reset='1' then
			ff<='1';
		elsif clk'event and clk='1' then
			ff<=ff_d;
		end if;
	end process;

The syn_keep keeps the global reset signal around long enough to get into the
Xilinx tool so that the initial values don't disappear in the synthesizers
analysis.









"Mike H." wrote:
> 
> "Peter Lang" <Peter.Lang@rmvmachinevision.de> wrote in message
> news:8v0kfs$i4p$04$1@news.t-online.com...
> > Hi,
> > by default FGPA Express will init all Registers in my Spartan device to
> > zero.
> > How can I change this default?
> > When doing schematic entry this was easyly done by adding "INIT=S"
> > But how can I do this with VHDL?
> 
> I think you can do this by instantiating a "ROC" function
> (Reset On Configuration) and using the output to preset
> your registers.
> 
> Do a search for ROC in the Xilinx on-line documentation.
> 
> HTH
> 
> MH

-- 
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com  or http://www.fpga-guru.com

Article: 27310
Subject: Re: COREGEN ROM in VHDL... How do I use it?
From: Andy Peters <"apeters <"@> n o a o [.] e d u>
Date: Fri, 17 Nov 2000 10:59:14 -0700
Links: << >>  << T >>  << A >>
Theron Hicks wrote:
> 
> I have a ROM generated in coregen that I would like to place in my
> system.  How do I use the coregen template from the language tools?
> Several places in the instructions in the template are not especially
> clear.  For example what is the intent of the
> -- synopsys translate_off
> and
> -- synopsys translate_on
> comments in the template.

Those are pragmas that tell the synthesis tool to ignore code between
translate_off and translate_on.  In this case, they are used because
Synopsys does not understand configurations.  The synthesis tool just
creates a black box for the ROM that the P+R tools fill in.  However, to
simulate, something must be there.
 
> Where exactly do I place the configuration snippet?

At the end of the source file.
 
> -- synopsys translate_off
> 
>  for all : rom256x8 use entity
> XilinxCoreLib.C_MEM_SP_BLOCK_V1_0(behavioral)
>   generic map(
>    c_has_en => 0,
>    c_rst_polarity => 1,
>    c_clk_polarity => 1,
>    c_width => 8,
>    c_has_do => 1,
>    c_has_di => 0,
>    c_en_polarity => 1,
>    c_has_we => 0,
>    c_has_rst => 0,
>    c_address_width => 8,
>    c_read_mif => 1,
>    c_depth => 256,
>    c_pipe_stages => 0,
>    c_mem_init_radix => 16,
>    c_default_data => "FF",
>    c_mem_init_file => "rom256x8.mif",
>    c_we_polarity => 1,
>    c_generate_mif => 0);
>  end for;
> 
> -- synopsys translate_on
> 
> What is the intent of these lines?

The configuration indicates which entity/architecture pair are used "for
all" instantiations of the component rom256x8.  In this case, all
instantiations of rom256x8 pull a component called C_MEM_SP_BLOCK_V1_0
out of the XilinxCoreLib, and it uses the architecture called
behavioral.  In addition, generics are supplied.
 
> --
> -- <Insert LIBRARY Declaration here>
> --
> -- configuration <cfg_my_design> of <my_design> is
> --     for <my_arch_name>
> --         <Insert CONFIGURATION Declaration here>
> --     end for;
> -- end <cfg_my_design>;
> --
> -- If this is not the top-level design then in the next level up, the
> following text
> -- should appear at the end of that file:
> --
> -- configuration <cfg> of <next_level> is
> --     for <arch_name>
> --           for all : <my_design> use configuration <cfg_my_design>;
> --           end for;
> --     end for;
> -- end <cfg>;
> --
> How do I fill in the various blanks?
> Does anyone have an example of code with a functioning coregen part in
> it?

See example below!  Assume the code is in a source file called fifo.vhd.

library ieee;
use ieee.std_logic_1164.all;

entity fifo is
    port ( );
end entity fifo;

architecture fifo_arch of fifo is

    signal ....
    
    -- CORE dual-port RAM:
    component dpram16d16w is
	port ( ... );
    end component dpram16d16w;

begin

    u1 : dpram16d16w
	port map ( ... );

end architecture fifo_arch;

-- configuration only needed for simulation:
-- synopsys translate_off
library XilinxCoreLib;

configuration cfg_fifo of fifo is
    for fifo_arch
	for all : dpram16d16w use entity XilinxCoreLib.dpramVHT(behavioral)
	    generic map ( ... );
	end for; -- all
    end for; -- fifo arch
end configuration cfg_fifo;
-- synopsys translate_on

Now, assume the following is in the next-higher-level code.  This could
be your test bench for the fifo module, or it could be the next
hierarchy level of your chip design.  Call this file top_level.vhd.

library ieee;
use ieee.std_logic_1164.all;

entity top_level is
    port ( ... );
end entity top_level;

architecture top_level_arch is

    -- we want a fifo:
    component fifo is
	port ( ... );
    end component fifo;

begin

    u1 : fifo
	port map ( ... );

end architecture top_level_arch;

-- synopsys translate_off
configuration cfg_top_level of top_level is
    for top_level_arch
	for all : fifo
	    use configuration work.cfg_fifo;
	end for; -- all fifo
    end for; -- top-level-arch
end configuration cfg_top_level;
-- synopsys translate_on

The secret here is that you must write a configuration if a lower-level
component uses a configuration.

Yeah, wouldn't it be nice if Xilinx' documentation didn't suck so hard
here?  You should read the Ashenden book's section on configurations.

-- a
----------------------------
Andy Peters
Sr. Electrical Engineer
National Optical Astronomy Observatory
950 N Cherry Ave
Tucson, AZ 85719
apeters (at) n o a o [dot] e d u

"It is better to be silent and thought a fool, 
 than to send an e-mail to the entire company
 and remove all doubt."

Article: 27311
Subject: Re: Spartan 3.3V Driving 5v input tristate + pull up problem...
From: Andy Peters <"apeters <"@> n o a o [.] e d u>
Date: Fri, 17 Nov 2000 11:11:48 -0700
Links: << >>  << T >>  << A >>
Nial Stewart wrote:
> 
> The guy who did the board I'm currently working on had a
> 3.3V IO spartan 2 driving (or not)  the 5V CMOS inputs
> on an ADC.
> 
> I implemented the 'tri-state when driving high ie
> 
>     signal_out <= 'Z' when (signal_internal = '1') else signal_i;
> 
> with an external pull up' which allows the driven signals
> to reach 5V, but a couple of the lines are clocks and
> were taking 40nS to get from 1V -> 4V. I think this was
> causing problems with the DAC.

What value of pullup resistor are you using?  Smaller = faster!

One thing I don't understand: why are you using open-drain outputs to
drive a clock input?  Seems to me that you'd want to arrange your logic
such that one (and only one) driver clocks the ADC.
 
-- a
----------------------------
Andy Peters
Sr. Electrical Engineer
National Optical Astronomy Observatory
950 N Cherry Ave
Tucson, AZ 85719
apeters (at) n o a o [dot] e d u

"It is better to be silent and thought a fool, 
 than to send an e-mail to the entire company
 and remove all doubt."

Article: 27312
Subject: Re: VHDL & Spartan: How to power-up a Register to '1' ?
From: Andy Peters <"apeters <"@> n o a o [.] e d u>
Date: Fri, 17 Nov 2000 11:14:15 -0700
Links: << >>  << T >>  << A >>
Peter Lang wrote:
> 
> Hi,
> I think I must decribe my problem more precise:
> I only want that an CLB Register FF inits to one after the configuration of
> the FPGA is
> done. I dont want to use expilicit asynchron set lines to do this.

GSR does exactly that.  Write your code to set the flops upon assertion
of the async reset.  You can tie the async reset pin in the deasserted
state if you'll never use it.  GSR is asserted automatically at the end
of configuration and uses the same net as your reset pin.

-- a
----------------------------
Andy Peters
Sr. Electrical Engineer
National Optical Astronomy Observatory
950 N Cherry Ave
Tucson, AZ 85719
apeters (at) n o a o [dot] e d u

"It is better to be silent and thought a fool, 
 than to send an e-mail to the entire company
 and remove all doubt."

Article: 27313
Subject: Re: Microprocessor Verilog/VHDL Models
From: Andy Peters <"apeters <"@> n o a o [.] e d u>
Date: Fri, 17 Nov 2000 11:16:43 -0700
Links: << >>  << T >>  << A >>
Ulf Samuelsson wrote:
> 
> You might consider a simple instruction set simulator which
> connects to bus model written in PLI for verilog.
> It aint an exact model but might do.

I'm a VHDL bigot so it won't help! :)

-- a
----------------------------
Andy Peters
Sr. Electrical Engineer
National Optical Astronomy Observatory
950 N Cherry Ave
Tucson, AZ 85719
apeters (at) n o a o [dot] e d u

"It is better to be silent and thought a fool, 
 than to send an e-mail to the entire company
 and remove all doubt."

Article: 27314
Subject: Re: In the news
From: Ben Franchuk <bfranchuk@jetnet.ab.ca>
Date: Fri, 17 Nov 2000 18:33:32 +0000
Links: << >>  << T >>  << A >>
Philip Freidin wrote:
> 
> While I could make quite a few comments on this,
> I think I will just give you the link:
> 
>    http://www.xilinx.com/prs_rls/xilinxwin.htm
>

Shades of M$.

-- 
"We do not inherit our time on this planet from our parents...
 We borrow it from our children."
"Luna family of Octal Computers" http://www.jetnet.ab.ca/users/bfranchuk

Article: 27315
Subject: Re: reset pulse ?
From: erika_uk@my-deja.com
Date: Fri, 17 Nov 2000 18:41:52 GMT
Links: << >>  << T >>  << A >>
Hi,

Thanks ray for the reply
Now i am bit confused...so what is the need for the startup block which
has been recommended by xilinx to reset the design
( well at least for a non virtex type Fpga ).

regards

--Erika




In article <3A156E05.94B4D346@andraka.com>,
  Ray Andraka <ray@andraka.com> wrote:
> Erika,
>
> My newreader didn't get your original post.  The flip-flops are all
at the
> initial value at the end of reconfiguration (generally '0' unless
explicity set
> to '1' by an init="S", although the FDS, FDSE etc have that init='S'
already on
> them).  This is basically as if the global reset was applied even
though you
> don't have the start-up block in your design.  So in answer to your
question,
> yes the flip-flops do get set to a known state by configuration, and
no you
> don't need an explicit reset signal to do it.  Note that even though
this
> methodology works well and is one I subscribe to, it is likely to get
any ASCI
> designers reviewing your design to scream and jump up and down.
>
> erika_uk@my-deja.com wrote:
> >
> > ooh experts, any input here ?
> > ray,  where are you hidding !!!!???
> >
> > In article <8usdpl$qbl$1@nnrp1.deja.com>,
> >   erika_uk@my-deja.com wrote:
> > > I forget to add, is there any prefixed from where i can drive it ?
> > >
> > > In article <8usd7d$pqh$1@nnrp1.deja.com>,
> > >   erika_uk@my-deja.com wrote:
> > > > hey,
> > > >
> > > > just basic question. will the reset pulse be
> > generated "automatically"
> > > > after configuration? can i use this pulse to clear some counters
> > > > synchrnously. i don't want to infer the startup because of...
(the
> > > > famous story)
> > > >
> > > > thanks
> > > >
> > > > --Erika
> > > >
> > > > Sent via Deja.com http://www.deja.com/
> > > > Before you buy.
> > > >
> > >
> > > Sent via Deja.com http://www.deja.com/
> > > Before you buy.
> > >
> >
> > Sent via Deja.com http://www.deja.com/
> > Before you buy.
>
> --
> -Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930     Fax 401/884-7950
> email ray@andraka.com
> http://www.andraka.com  or http://www.fpga-guru.com
>


Sent via Deja.com http://www.deja.com/
Before you buy.

Article: 27316
Subject: Re: Schematics & VHDL
From: "John Janusson" <null@null.com>
Date: Fri, 17 Nov 2000 18:52:16 GMT
Links: << >>  << T >>  << A >>
Visual HDL includes libraries and symbols for gates, registers, muxes, etc.
that you can include in your block diagrams...  They are instances of some
pre-written hdl code provided by the tool vendor...  I think Renoir has done
something similar in recent releases...

Good Luck...
John

V Ram <ipickledthefigsmyself@mrbourns.com> wrote in message
news:8v13sj$e0n$1@news.utdallas.edu...
> Edwin Naroska <edwin@nospamthisaddress.either..de> wrote:
> > Hi,
>
> > You may take a look at part 3 section 5 of the VHDL FAQ
> > (http://www.vhdl.org/comp.lang.vhdl/). It lists some free
> > and commercial VHDL <-> Schematic/FSM Translators.
>
> Thanks Edwin but I meant a program that allows me to make
> "black-boxes" out of my VHDL and then use standard primatives like NAND2,
> OR2, etc and graphically hook it up. As the other posted said one could
> make these components in Renoir and then hook it up, but that defeats the
> purpose...
>
> Thanks.



Article: 27317
Subject: Re: Spartan 3.3V Driving 5v input tristate + pull up problem...
From: Peter Alfke <peter.alfke@xilinx.com>
Date: Fri, 17 Nov 2000 11:22:14 -0800
Links: << >>  << T >>  << A >>
I did not invent this "trick", but I was the first to publish it, so there is
a bit of parental pride here  :-)
Add routing or logic delay into the feedback, so that the output does not
"immediately" go 3-state when the level crosses the threshold. An extra ns or
two of staying active, pulling High, might help.

Peter Alfke
=======================
rickman wrote:

> Nial Stewart wrote:
> >
> > The guy who did the board I'm currently working on had a
> > 3.3V IO spartan 2 driving (or not)  the 5V CMOS inputs
> > on an ADC.
> >
> > I implemented the 'tri-state when driving high ie
> >
> >     signal_out <= 'Z' when (signal_internal = '1') else signal_i;
> >
> > with an external pull up' which allows the driven signals
> > to reach 5V, but a couple of the lines are clocks and
> > were taking 40nS to get from 1V -> 4V. I think this was
> > causing problems with the DAC.
>
> Can you explain the problems you saw in this mode? I am curious since
> the double clocking you saw when you had ringing is also a problem that
> could be caused by a slow edge. A slow edge has less dV/dt and can
> become non-monotonic from noise. This can cause double clocking when it
> is crossing the threshold of the input. If you don't see double clocking
> in this case, maybe there is a different way to fix your problem.
>
>
> > I then tried the 'drive it to 3.3V high level then
> > tristate' improvement ie
> >
> >  signal_out <= 'Z' when (signal_internal = '1' and signal_out = '1') else
> > signal_internal;
> >
> > This improved things a lot speedwise, but I started getting
> > a fair bit of ringing around 3.3 -> 4 V and the ADC input
> > started 'double clocking' on some of the edges (the traces
> > are fairly long).
> >
> > The Xilinx app note (Tech Topic VTT002 v1.0) says
> > "Ringing can be avoided by following proper board design
> > practices", but most termination techniques are concerned
> > with terminating a trace with it's characteristic
> > impedance, not having to simultaneously pull the signal
> > high as hard as possible to get a fast rising edge.
> >
> > I've experimented with various terminations, and with
> > varying the DRIVE attribute of the output to see if I
> > can cut down on the problem, withought much success.
> >
> > Has anone come across a similar problem and come up with a
> > satisfactory solution?
>
> I have not tried this trick, but is it possible that the ringing is
> actually causing an oscillation of the tristate driver? The equation
> lets the output drive until the input threshold is crossed. Then the
> driver is turned off. But if a small amount of ringing brings the output
> back low enough to trip the input threshold again, the output will drive
> hard again, causing more ringing.
>
> Is is possible to use the tristate control FF with the output signal
> driving the clock? Then once the clock turns the tristate off, it will
> stay off no matter what ringing happens. Of course this will stop the
> oscillation, but you still have the initial ring that may still cause
> problems on a clock line. But that truly is layout and edge rate
> related.
>
> --
>
> Rick "rickman" Collins
>
> rick.collins@XYarius.com
>
> Ignore the reply address. To email me use the above address with the XY
> removed.
>
> Arius - A Signal Processing Solutions Company
> Specializing in DSP and FPGA design
>
> Arius
> 4 King Ave
> Frederick, MD 21701-3110
> 301-682-7772 Voice
> 301-682-7666 FAX
>
> Internet URL http://www.arius.com


Article: 27318
Subject: Re: 5v parallel cable with 2.5/3.3v spartan II?
From: "Mark Harvey" <mark.harvey@iol.it>
Date: Fri, 17 Nov 2000 20:30:55 GMT
Links: << >>  << T >>  << A >>
I've used both the Xilinx & Insight download cables with the Insight SP2
demo board - everything works just fine.

Mark.


<cottons@concmp.com> wrote in message
news:m37l637tsk.fsf@bagua.concmp.com...
> I have a Xilinx Parallel Cable III, model DLC5, labeled as operating
> at 5v.  Does anyone know if this will work with a 2.5vccint/3.3vcco
> Spartan II board?  I'm using the Insight Electronics Spartan II board.
>
>         - Cotton



Article: 27319
Subject: Re: Schematics & VHDL
From: Greg Neff <gregneff@my-deja.com>
Date: Fri, 17 Nov 2000 21:06:08 GMT
Links: << >>  << T >>  << A >>
In article <8uuvue$8iq$1@news.utdallas.edu>,
  V Ram <ipickledthefigsmyeslf@mrbourns.com> wrote:
(snip)
Anyone
> use ViewDraw?

Yes, we use ViewDraw.  I have been told that you can mix VHDL and
schematics with ViewLogic, but I have never tried it.  You probably
need to generate an EDIF netlist out of the synthesis tool, and build a
schematic symbol wrapper for the netlist.

--
Greg Neff
VP Engineering
*Microsym* Computers Inc.
greg@guesswhichwordgoeshere.com


Sent via Deja.com http://www.deja.com/
Before you buy.

Article: 27320
Subject: Re: Can FPGA perform float point calculation?
From: gah@ugcs.caltech.edu (glen herrmannsfeldt)
Date: 17 Nov 2000 22:54:18 GMT
Links: << >>  << T >>  << A >>
Ray Andraka <ray@andraka.com> writes:

>My comment that it costs area is in comparison to fixed point.  The driver is
>mainly the denormalizing and normalizing barrel shifts needed for
>addition/subtraction.  Multiplication is not much more complex than a fixed
>point multiplier.  Fortunately, floating point is not really needed in most DSP
>applications, and where it is needed, you can usually get a way with block
>floating point or a partial floating point where the operation is done in fixed
>point with an exponent that is carried around the fixed point part and modified
>at the output by normalizing the fixed point result.

If you don't need so many bits for mantissa or exponent, it might not
be too bad.  Multiply is big in an FPGA, either fixed or floating.
Divide is even worse, fixed or floating.

If you did it base 16 (like IBM S/360 and S/370), it would take less
barrel shift logic.  

-- glen

Article: 27321
Subject: Re: Schematics & VHDL
From: Duane <junkmail@junkmail.com>
Date: Fri, 17 Nov 2000 15:02:00 -0800
Links: << >>  << T >>  << A >>
Greg Neff wrote:
> 
> In article <8uuvue$8iq$1@news.utdallas.edu>,
>   V Ram <ipickledthefigsmyeslf@mrbourns.com> wrote:
> (snip)
> Anyone
> > use ViewDraw?
> 
> Yes, we use ViewDraw.  I have been told that you can mix VHDL and
> schematics with ViewLogic, but I have never tried it.  You probably
> need to generate an EDIF netlist out of the synthesis tool, and build a
> schematic symbol wrapper for the netlist.

At least with Xilinx (where I frequently mix schematics -I like top
level schematics- and VHDL) the way I do it is to just create a black
box for the VHDL and stick it on my schematic. It gets put into the edif
(or xnf in my case) for the schematic as a black box. Then the edif (or
xnf) from the VHDL synthesis gets combined with the xnf from the
schematic by ngdbuild. I use a post processing tool to turn the
schematic into structural VHDL for simulation.

--
My real email is akamail.com@dclark (or something like that).

Article: 27322
Subject: Altera MAX+PlusII v.s. Xilinx Foundation
From: "Rex Fisher" <fisherr@ricks.edu>
Date: Fri, 17 Nov 2000 16:43:56 -0700
Links: << >>  << T >>  << A >>
I teach an introductory-level digital logic course at a junior college.  I
have been using PALs, such as the 16V8 to introduce students to programmable
logic.  The architecure is simple to understand and the CUPL programming
language is easy to learn.

I would like to expand this topic to include CPLDs and FPGAs.  I am not an
expert on these devices and must learn them for myself first.  Most of the
textbooks I have looked at use either the Altera or Xilinx software.  The
capabilities of the actual hardware I would use for the class is not as
important as the usability of the software, because the circuits would not
be very large or complicated.  Evaluation boards that can be used for lab
projects are available from both companies.  The main idea is to get some
exposure to the design tools and process.

Which software product do you experts think would be the easiest to learn
and use in an introductory digital circuits course?

Thanks!






Article: 27323
Subject: Re: Actel Compiler errors..... from Synplify?!
From: rk <stellare@nospamplease.erols.com>
Date: Fri, 17 Nov 2000 19:01:42 -0500
Links: << >>  << T >>  << A >>
James Buchanan wrote:
> 
> HI All,
>    Here's a seemingly easy problem that has me running for the hills!!!
> 
> Using Synplify to construct edif listings that are later pulled into
> Actel's designer. Problem seems to be that Synplify is using pre-define
> MACROS that construct an HCLK like architecture. Problem is that I am
> NOT using this HCLK architecture for the overall design. Thus, Synplify
> constructs an FPGA using macros that construct this HCLK stuff that I am
> NOT using. Granted, I am using the high performance IOCLKs, but NO WHERE
> do I use this HCLK. THE PIN IS EMPTY!!! THE VHDL DOES NOT CALL FOR
> THEM!!!
> 
>   HELP!!! HELP !!!!!
>      HELP!!!!!!
> 
> jhbuchanan@west.raytheon.com

Hi,

It sounds like you're using Act 3.  Are you synthesizing in chip mode or
module mode?  If you are using chip mode, it will generally insert,
automagically, one of the clock buffers such as HCLK to run signals to
your clock.  Normally, if you do not want it to insert I/O's or clock
buffers, you should not compile into the chip mode - now, annoyingly,
Synplicity will build for clock signals a network of buffers which,
depending on your clock architecture, may produce a poor circuit.  You
must work your way around this using a fan out attribute [granted, I'm
not running the latest, can't keep up with an update a day for each
tools - it's tough enough following the election, which changes at a
slower rate!

Generally, for most designs compiled at the chip level, putting the HCLK
in automagically is a good thing.  Not always, though, as for example it
won't be able to hook up to flip-flops constructed only out of C-Mods.

Not sure if this helps, please respond via e-mail or usenet with more
info.  Note I am a bit time constrained and don't follow the group as
closely as I used to.

Good luck,

rk

Article: 27324
Subject: Re: Spartan 3.3V Driving 5v input tristate + pull up problem...
From: Ray Andraka <ray@andraka.com>
Date: Sat, 18 Nov 2000 01:10:09 GMT
Links: << >>  << T >>  << A >>
I think he is using only one driver. His issue, if I'm reading this right is
that the ADC needs to see a level higher than the 3.3v output (I don't know what
ADC he's using), so he's using the FPGA output as an open drain to get the low
level and a pull-up for the high.

My first thought is to pick a different ADC.  There are several out there that
provide an option for 3.3v interface and 5v Analog.  If for some reason you are
stuck with that ADC, you might use a quickswitch as a level translator.  Those
things get you a nearly transparent translation...propagation delay is well
under a nanosecond.  I'm not sure Peter's suggestion of delaying the tristate
will help or not, as I am not sure what will happen if the active output is
externally pulled up to 5v.  I suspect it will continue on up close to 5v
without incident as long as the protection diodes are enabled.


Andy Peters wrote:
> 
> Nial Stewart wrote:
> >
> > The guy who did the board I'm currently working on had a
> > 3.3V IO spartan 2 driving (or not)  the 5V CMOS inputs
> > on an ADC.
> >
> > I implemented the 'tri-state when driving high ie
> >
> >     signal_out <= 'Z' when (signal_internal = '1') else signal_i;
> >
> > with an external pull up' which allows the driven signals
> > to reach 5V, but a couple of the lines are clocks and
> > were taking 40nS to get from 1V -> 4V. I think this was
> > causing problems with the DAC.
> 
> What value of pullup resistor are you using?  Smaller = faster!
> 
> One thing I don't understand: why are you using open-drain outputs to
> drive a clock input?  Seems to me that you'd want to arrange your logic
> such that one (and only one) driver clocks the ADC.
> 
> -- a
> ----------------------------
> Andy Peters
> Sr. Electrical Engineer
> National Optical Astronomy Observatory
> 950 N Cherry Ave
> Tucson, AZ 85719
> apeters (at) n o a o [dot] e d u
> 
> "It is better to be silent and thought a fool,
>  than to send an e-mail to the entire company
>  and remove all doubt."

-- 
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com  or http://www.fpga-guru.com



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