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Messages from 27825

Article: 27825
Subject: Cannot get chip's information from Synopsys
From: Marc Reinert <reinert@tu-harburg.de>
Date: Mon, 11 Dec 2000 11:34:32 +0100
Links: << >>  << T >>  << A >>
What's wrong when I get the following error message:

"Cannot get chip's information from Synopsys - Unknown error."

I  also get another window saying: "Synopsys internal error - abort at
1822"

I'm using Xilinx Foundation Express 3.1/3.2 (SP5) on a Win NT platform.
It works well with most of my VHDL-programs (even with the same chip,
XCV600E)

Regards

Marc

Article: 27826
Subject: ERROR: The net has more than one driver?
From: Tesisti DSPLab <tescom@diei.unipg.it>
Date: Mon, 11 Dec 2000 12:17:30 +0100
Links: << >>  << T >>  << A >>
Hallo,

we are implementing single-process applications
and we find the following error:

The net "clr" has more than one driver (FPGA-CHECK-5)

Xilinx Help has not this entry in its database: is that
possible?

The portion of the VHDL file that gives this problem follows:


...........

    component FFD_clr is
       port( D,CLK,clr : in std_logic;
                Q      : out std_logic);
    end component;

    signal d : std_logic_vector(0 to (M+1));

    signal clr : std_logic;

begin

    clr <='1';
    STR1 : for i in 0 to M generate
              node : FFD_clr port map (d(i),CLK,clr,d(i+1));
           end generate STR1;

.............



Please give us your opinions about this.

Thanks

Smilla.


Article: 27827
Subject: Re: Cannot get chip's information from Synopsys
From: Kent Orthner <korthner@hotmail.nospam.com>
Date: 11 Dec 2000 20:48:36 +0900
Links: << >>  << T >>  << A >>
Hi, Marc.  

I was getting the same error a little while ago.

I suggest that you open up Synopsys directly, and try 
synthesising from there.  Hopefully it will give you 
a bit more information, such as a failure code.

when I had the same problem it was because my 
component Instatiations looked like:

InstanceName: entity work.ComponentName
  port map (
    SignalName        => SignalName  );

instead of

InstanceName: ComponentName
  port map (
    SignalName        => SignalName  );

Once I deleted the "entity work.", there was no problem.

When the extra stuff was there, It still simulated 
beautifully.  The extra stuff (In my case) comes 
from Emcas VHDL mode when I use the "Paste as instance" 
command.

Hope this helps.

-Kent




Marc Reinert <reinert@tu-harburg.de> writes:

> What's wrong when I get the following error message:
> 
> "Cannot get chip's information from Synopsys - Unknown error."
> 
> I  also get another window saying: "Synopsys internal error - abort at
> 1822"
> 
> I'm using Xilinx Foundation Express 3.1/3.2 (SP5) on a Win NT platform.
> It works well with most of my VHDL-programs (even with the same chip,
> XCV600E)
> 
> Regards
> 
> Marc

Article: 27828
Subject: Re: fpga: 32 bit parity generation in 4 ns for virtexE
From: David Hawke <dhawke@xilinx.com>
Date: Mon, 11 Dec 2000 14:26:52 +0000
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.
--------------CC306B41476418BCCE7DA594
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Content-Transfer-Encoding: 7bit

You could also implement the function on the carry chain using the LUTs as a mask and then the XOR on the carry. The carry chain delay is 100ps per bit pair, and this is the fastest way to do it..However it does mean that you will have to instantiate everything, but it will give you the speed.

Dave

Nisreen Taiyeby wrote:

> I want to generate a 32 bit parity for which the delay is to be 4 ns maximum.I use Leonardo spectrum 2000.I do not insert pads since this is  a sub-module in my hierarchy.How do I acheive this in VirtexE architecture.Leonardo gives me 14 ns delay.After implementation in Xilinx I get 25% logic delay and
> 75 % routing delay which is 5 ns logic and 8 ns routing.I do manual placement in the floorplanner only to see Dr.watson error when I re-implement the design.Using Synplicity RLOC constraint Is a better option which gives me 4 ns logic delay while synthesis but the xilinx tool does away with the RLOC constraint and spreads the logic haphazardly once again.
>
> How can I acheive this 4ns delay through the parity logic with Leonardo-xilinx alliance combination.
> I have only eval license of synplicity.

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begin:vcard 
n:Hawke;David Hawke
tel;cell:(+44) 778 875 5002
tel;work:(+44) 870 7350 517
x-mozilla-html:TRUE
org:<br><img src="http://www.xilinx.com/images/smvirtex.gif" alt="Xilinx">
version:2.1
email;internet:dhawke@xilinx.com
title:XILINX   Field Applications Engineer
adr;quoted-printable:;;Xilinx Northern Europe=0D=0ABenchmark House;203 Brooklands road;Weybridge;;
x-mozilla-cpt:;2672
fn:David Hawke
end:vcard

--------------CC306B41476418BCCE7DA594--


Article: 27829
Subject: Fpga:How can I specify RLOC constraint in Leonardo
From: "Nisreen Taiyeby" <nisreen@bangalore.coreel.com>
Date: Mon, 11 Dec 2000 06:46:28 -0800
Links: << >>  << T >>  << A >>
Can someone tell me how to specify RLOC,U_SET and MAP constraint through Leonardo Spectrum.

Article: 27830
Subject: Re: jtag for fpga
From: Jamie Lokier <spamfilter.dec2000@tantalophile.demon.co.uk>
Date: 11 Dec 2000 16:37:43 +0100
Links: << >>  << T >>  << A >>
harveytwyman  writes:
> We use the Altera MaxPlus II Development Tool in my department.
> It has the JTAG facility for configuring individual devices or multiple
> devices in cascade. They can be different types of FPGA or even
> Configuration storage Devices like the EPC2.

It works pretty well.

But have you ever tried building a JTAG programming file for 32 devices
on a 35 device chain with Maxplus2?  On our Suns it took about 40
minutes to make the programming file.  The initial Place & Route step
took about 3 minutes.

-- Jamie

Article: 27831
Subject: Re: fpga: 32 bit parity generation in 4 ns for virtexE
From: Duane <junkmail@junkmail.com>
Date: Mon, 11 Dec 2000 08:19:53 -0800
Links: << >>  << T >>  << A >>
David Hawke wrote:
> 
> You could also implement the function on the carry chain using the LUTs as
> a mask and then the XOR on the carry. The carry chain delay is 100ps per
> bit pair, and this is the fastest way to do it..However it does mean that
> you will have to instantiate everything, but it will give you the speed.
> 
> Dave

Perhaps you could elaborate a bit on this. I have implemented other
logic by directly instantiating components of the Virtex carry chain,
but I do not see any way to do a parity chain. Assuming you are talking
about the XORCY, it looks to me like the output only goes to the output
of the slice. And I don't see any efficient way to inject the result of
it back into the carry chain, which would be needed to implement parity.
Maybe I am missing something here.

> 
> Nisreen Taiyeby wrote:
> 
> > I want to generate a 32 bit parity for which the delay is to be 4 ns
> > maximum.I use Leonardo spectrum 2000.I do not insert pads since this is
> >  a sub-module in my hierarchy.How do I acheive this in VirtexE
> > architecture.Leonardo gives me 14 ns delay.After implementation in
> > Xilinx I get 25% logic delay and
> > 75 % routing delay which is 5 ns logic and 8 ns routing.I do manual
> > placement in the floorplanner only to see Dr.watson error when I
> > re-implement the design.Using Synplicity RLOC constraint Is a better
> > option which gives me 4 ns logic delay while synthesis but the xilinx
> > tool does away with the RLOC constraint and spreads the logic haphazardly once again.
> >
> > How can I acheive this 4ns delay through the parity logic with
> > Leonardo-xilinx alliance combination.
> > I have only eval license of synplicity.

--
My real email is akamail.com@dclark (or something like that).

Article: 27832
Subject: VHDL Studio for Linux
From: "EuroEDA Information" <info@euro-eda.com>
Date: Mon, 11 Dec 2000 18:03:40 -0000
Links: << >>  << T >>  << A >>
VHDL Studio from Green Mountain Computing Systems is now available in Europe
exclusively from EuroEDA Limited. VHDL Studio is available for Win95/98/NT
and Linux.

Full details at http://www.euro-eda.com

--
EuroEDA Limited

Phone: +44 (0)1933 676373
Fax: +44 (0)1933 676372
Email: info@euro-eda.com
Web: http://www.euro-eda.com



Article: 27833
Subject: VHDL technique for synchronizer ?
From: Dave Nadler <drn@nadler.com>
Date: Mon, 11 Dec 2000 13:46:25 -0500
Links: << >>  << T >>  << A >>
This is a newbie question, but I'd appreciate help...

I have an FPGA attached to a uC bus. The uC bus is async w/respect
to the FPGA. The bus interface is "clocked" by the "WR" strobe
(Intel-style bus), so I latch the data for the FPGA based on the
WR transition (subject to CS etc), and also I set a latch that
indicates "data ready".

Now, I need the FPGA state machine to "notice" that there's data
sitting and waiting to be processed, in the latch, in a glitch-free
manner. I want to put a second latch triggered on the FPGA clock
after the "data has arrived" latch, to ensure I've got glitch-free
access to the incoming data. After I've processed the incoming
data, I need to clear the (sync and async) "data ready" latches.

Anybody got some hints, or better yet an example, of a good
way to handle this in VHDL, which is synthesizable without
"multiple-source" errors ?
Or, anybody got advice on what further textbooks I should
read ?

Thanks in advance for your help,
Best Regards, Dave



Article: 27834
Subject: Re: VHDL technique for synchronizer ?
From: Peter Alfke <peter.alfke@xilinx.com>
Date: Mon, 11 Dec 2000 11:22:47 -0800
Links: << >>  << T >>  << A >>

--------------DCDF4AC31C6671F3CB99C55B
Content-Type: text/plain; charset=us-ascii; x-mac-type="54455854"; x-mac-creator="4D4F5353"
Content-Transfer-Encoding: 7bit

Dave, you may want to look at an article I published in ISD magazine.
It's the top article under "Features":
"Moving data across asynchronous clock boundaries"
Click on:
http://www.isdmag.com/editorial/march00.html

Peter Alfke, Xilinx Applications
============================================
Dave Nadler wrote:

> This is a newbie question, but I'd appreciate help...
>
> I have an FPGA attached to a uC bus. The uC bus is async w/respect
> to the FPGA. The bus interface is "clocked" by the "WR" strobe
> (Intel-style bus), so I latch the data for the FPGA based on the
> WR transition (subject to CS etc), and also I set a latch that
> indicates "data ready".
>
> Now, I need the FPGA state machine to "notice" that there's data
> sitting and waiting to be processed, in the latch, in a glitch-free
> manner. I want to put a second latch triggered on the FPGA clock
> after the "data has arrived" latch, to ensure I've got glitch-free
> access to the incoming data. After I've processed the incoming
> data, I need to clear the (sync and async) "data ready" latches.
>
> Anybody got some hints, or better yet an example, of a good
> way to handle this in VHDL, which is synthesizable without
> "multiple-source" errors ?
> Or, anybody got advice on what further textbooks I should
> read ?
>
> Thanks in advance for your help,
> Best Regards, Dave

--------------DCDF4AC31C6671F3CB99C55B
Content-Type: text/html; charset=us-ascii
Content-Transfer-Encoding: 7bit

<!doctype html public "-//w3c//dtd html 4.0 transitional//en">
<html>
Dave, you may want to look at an article I published in ISD magazine.
<br>It's the top article under "Features":
<br>"Moving data across asynchronous clock boundaries"
<br>Click on:
<br><u><A HREF="http://www.isdmag.com/editorial/march00.html">http://www.isdmag.com/editorial/march00.html</A></u>
<p>Peter Alfke, Xilinx Applications
<br>============================================
<br>Dave Nadler wrote:
<blockquote TYPE=CITE>This is a newbie question, but I'd appreciate help...
<p>I have an FPGA attached to a uC bus. The uC bus is async w/respect
<br>to the FPGA. The bus interface is "clocked" by the "WR" strobe
<br>(Intel-style bus), so I latch the data for the FPGA based on the
<br>WR transition (subject to CS etc), and also I set a latch that
<br>indicates "data ready".
<p>Now, I need the FPGA state machine to "notice" that there's data
<br>sitting and waiting to be processed, in the latch, in a glitch-free
<br>manner. I want to put a second latch triggered on the FPGA clock
<br>after the "data has arrived" latch, to ensure I've got glitch-free
<br>access to the incoming data. After I've processed the incoming
<br>data, I need to clear the (sync and async) "data ready" latches.
<p>Anybody got some hints, or better yet an example, of a good
<br>way to handle this in VHDL, which is synthesizable without
<br>"multiple-source" errors ?
<br>Or, anybody got advice on what further textbooks I should
<br>read ?
<p>Thanks in advance for your help,
<br>Best Regards, Dave</blockquote>
</html>

--------------DCDF4AC31C6671F3CB99C55B--


Article: 27835
Subject: Re: Linear Regulator troubles
From: murray@pa.dec.com (Hal Murray)
Date: 11 Dec 2000 21:16:38 GMT
Links: << >>  << T >>  << A >>

In article <3A32EA0F.AB3B1A17@xilinx.com>,
 Peter Alfke <peter.alfke@xilinx.com> writes:
> I would use the second LP3965 to make 1.8 from 5 V. That avoids
> cascading two "amplifiers", which is always a tricky proposition.
> You lose nothing by running the two linear regulators in parallel, but
> you gain stability and peace of mind.

We tried that this morning.  Works.
  (even with a 1.5 inch inductor over to the 5 V supply.)
But I don't have many miles on it yet.

Thanks for the suggestion.

Note that (I think) this is a false shutdown problem, not an
instability.  I've got a clean triangle on the 1.8 supply
and the slope on the ramp matches the load current and filter
caps.
-- 
These are my opinions, not necessarily my employers.  I hate spam.

Article: 27836
Subject: ActelDeskTop Macro fanout problem
From: "Nick" <virg.in@virgin.net>
Date: Tue, 12 Dec 2000 01:09:46 -0000
Links: << >>  << T >>  << A >>
Hi,

I recently created a 16 bit wide counter using the ActGen macro tool in
ActelDesktop.
Everything was fine up until the point where I compiled the design using
Actel Designer. The compilations only error is that the clock fanout inside
the macro is 32, which exceeds the error limit of 24.
I then 'hacked' the macros VHDL  to incorporate a buffer every 4 FF's in the
counter chain. This made no difference to the compiler , still getting
exactly the same error.

Due to time restraints I have had to redesign the counter using two 8-bit
counter macros cascaded (this gives a 2 fanout warnings of 16 - below the
error limit but above recommended limit ).

If anyone can shed any light on this problem I would be very grateful

Cheers

Nick





Article: 27837
Subject: Re: Altera free development tools
From: bob_42690@my-deja.com
Date: Tue, 12 Dec 2000 02:25:26 GMT
Links: << >>  << T >>  << A >>


http://www.xilinx.com/xlnx/xil_prodcat_product.jsp?
iLanguageID=1&iCountryID=1&ioid=-8883&isiod=-8883&ipoid=24380#XES

The above link?? states that the XE Starter is appropriate for designs
of less than 500 lines of HDL code, and the Modelsim XE evaluation
version has a 30 day limit.


> Note
> that Modelsim XE starter is also free from Xilinx Website.
> It is not a size design limited tool. However, it is slower
> than the Modelsim XE which is not slower than the Altera
> Modelsim. There is also no time limitation, means that tools
> will work even after 1 year use.
> >
> <end orig>
> My license file for Modelsim XE starter has a 30day limit.
> If you are sure this is not time limited then please advise
> & I'll chase a correction.
>
> Anyone else?
>
> Dave
>
>


Sent via Deja.com http://www.deja.com/
Before you buy.

Article: 27838
Subject: Verilog and VHDL people wanted!!
From: "Barry Schneider" <barry61s@optonline.com>
Date: Tue, 12 Dec 2000 04:35:05 GMT
Links: << >>  << T >>  << A >>
I am presently working at a ASIC consulting company and we have a huge
backlog of work.  We need help and will pay well.  We have a great office
and have very flexible hours.   We are looking for Verilog and/or VHDL
experience.
Synthesis and/or Mixed Signal a plus. If you are interested in a Good Job
e-mail me at barry61s@optonline.com
  Hope to hear from you.

                        Sincerely,
                                        Barry


PS: We have needs in:       Commack, Long Island New York,
                                         Hazlet, New Jersey
                                         Bethlehem, Pennsylvania.
                                         Cherry Hill, New Jersey









Article: 27839
Subject: Re: dual port ram for altera
From: alexkarpel@my-deja.com
Date: Tue, 12 Dec 2000 08:03:38 GMT
Links: << >>  << T >>  << A >>
I used lpm_ram_dp to implement histogram function. At the same clock
you canread and write to the memory. My board is not yet ready, but I
checked thisfunction by simulation in MAX II 10KE family and compiled
this function forAPEX20KE. It seems that this function is working good.
In my designs I usedfifo's with different read and write clocks for
10KE and 20KE.
Ray Andraka wrote that RAM in Altera is not true dual port ram, but it
was for the 10K family, and in the 10KE and 20K, 20KE as I understand
it is real dual port memory.

 Alex




In article <3A32A6E7.2DAC2045@andraka.com>,
  Ray Andraka <ray@andraka.com> wrote:
> The ESB RAM in the Altera 20K is not a true dual port RAM.  It has a
read port
> and a write port.  In order to make it look like a dual port RAM, you
need to
> clock it at 2x your data clock to do 2 accesses per clock.  Depending
on your
> system clock, you may not be able to do that with one ESB.  You can
also double
> the number of ESBs so that you read or write two words for one
virtual port on
> even clocks and 2 words for the other virtual port on odd clocks.
>
> Xilinx Virtex's block RAM is a true dual port RAM, so you have
independent
> read/write access to both ports, even if the clocks are different.
>
> Jerry Pongstaporn wrote:
> >
> > has anyone tried to implement a true dual port ram in an altera 20k
> > device.  by true dual port, i mean you can write and read both
ports.
> > the only lpm they offer is lpm_ram_dp.  but that only allows you to
> > write one port and read the other.  i also tried the csdpram
function
> > they offer, but i cannot get that to work.  that is a cycle-shared
dual
> > port ram.  xilinx has a true dual port in their libraries, but i
would
> > rather not switch from altera at this point.  has anyone else run
into
> > this before?  btw, i am synthesizing vhdl with synplicity, and using
> > quartus for place and route.
>
> --
> -Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930     Fax 401/884-7950
> email ray@andraka.com
> http://www.andraka.com  or http://www.fpga-guru.com
>


Sent via Deja.com http://www.deja.com/
Before you buy.

Article: 27840
Subject: Re: Linear Regulator troubles
From: murray@pa.dec.com (Hal Murray)
Date: 12 Dec 2000 08:19:44 GMT
Links: << >>  << T >>  << A >>

[Context is my struggle with linear regulators and Peter's
suggestion to put them in parallel rather than series.]

> We tried that this morning.  Works.
>   (even with a 1.5 inch inductor over to the 5 V supply.)
> But I don't have many miles on it yet.

I should have started a raffle or something.

The old setup failed at 40 MHz.  This one fails around 60.

I think I'll go beat my head against a different wall for a while.

-- 
These are my opinions, not necessarily my employers.  I hate spam.

Article: 27841
Subject: Xilinx CPLD capable of driving LEDs
From: "Damir Danijel Zagar" <damir.zagar@tipro.hr>
Date: Tue, 12 Dec 2000 10:26:06 +0100
Links: << >>  << T >>  << A >>
Which Xilinx CPLD is capable of driving multiple LEDS or segment displays
(>50).

Is XC9500XL family good for this application, or should I look into FPGA
families
(i.e. Spartan II).

Thanks,

Damir




Article: 27842
Subject: Re: dual port ram for altera
From: Magnus Homann <d0asta@mis.dtek.chalmers.se>
Date: 12 Dec 2000 11:34:28 +0100
Links: << >>  << T >>  << A >>
alexkarpel@my-deja.com writes:

> I used lpm_ram_dp to implement histogram function. At the same clock
> you canread and write to the memory. My board is not yet ready, but I
> checked thisfunction by simulation in MAX II 10KE family and compiled
> this function forAPEX20KE. It seems that this function is working good.
> In my designs I usedfifo's with different read and write clocks for
> 10KE and 20KE.
> Ray Andraka wrote that RAM in Altera is not true dual port ram, but it
> was for the 10K family, and in the 10KE and 20K, 20KE as I understand
> it is real dual port memory.

Depends on what you mean by dual port. In Altera you can't read and
write from the same side. For a FIFO, that's often good enough, but
it is not the same as a normal dual port memory (as seen in discrete
DP-RAM).

Homann
--
Magnus Homann, M.Sc. CS & E
d0asta@dtek.chalmers.se

Article: 27843
Subject: Re: ActelDeskTop Macro fanout problem
From: rk <stellare@nospamplease.erols.com>
Date: Tue, 12 Dec 2000 06:01:40 -0500
Links: << >>  << T >>  << A >>
Nick wrote:

> I recently created a 16 bit wide counter using the ActGen macro tool in
> ActelDesktop.
> Everything was fine up until the point where I compiled the design using
> Actel Designer. The compilations only error is that the clock fanout inside
> the macro is 32, which exceeds the error limit of 24.
> I then 'hacked' the macros VHDL  to incorporate a buffer every 4 FF's in the
> counter chain. This made no difference to the compiler , still getting
> exactly the same error.
>
> If anyone can shed any light on this problem I would be very grateful

OK, not much info here - don't know what family/die you are targetting,
exact type of counter w/ options, or what version of Actgen/Designer. 
But let's go with what we got.

-- Semi-random educated guess mode on

1. Clock fanout compilation error - 32, with a limit of
   24 for a 16-bit wide counter.  Hmm ... factor of tw.

2. That is correct.  Large fanouts on a regular net are not
   allowed.

3. There are no limits on the fanout of the global clock.

4. You are using a parallel clock structure.  If you chose
   a ripple clock, then there would be not be a fan out problem.

5. You have committed a crime against humanity - using a local
   clock for parallel counter.  This structure often has hold
   time problems because of the high-skew nature of local
   signals.

6. You should be thankful for the error.

7. Remember, the counter is a *soft* macro, it is not a TTL
   component with a buffered clock input.

8. Easy solution: hook up the clock to one of the global clock
   buffers (all families) or one of the low-skew quadrant
   clocks (some families, some parts).

9. Other solutions using high-skew clocks quite doable and
   reliable.

10. Er, send info if this isn't your problem and/or doesn't help.

Good luck!


----------------------------------------------------------------------
rk                               How the hell do I know? I'm just a
stellar engineering, ltd.        common, ordinary, simple savior of
stellare@erols.com.NOSPAM        America's destiny.
Hi-Rel Digital Systems Design    -- Pat Paulsen

Article: 27844
Subject: Re: Linear Regulator troubles
From: Nial Stewart <nials@sqf.hp.com>
Date: Tue, 12 Dec 2000 11:25:53 +0000
Links: << >>  << T >>  << A >>
Hal Murray wrote:
> 
> [Context is my struggle with linear regulators and Peter's
> suggestion to put them in parallel rather than series.]
> 
> > We tried that this morning.  Works.
> >   (even with a 1.5 inch inductor over to the 5 V supply.)
> > But I don't have many miles on it yet.
> 
> I should have started a raffle or something.
> 
> The old setup failed at 40 MHz.  This one fails around 60.


Hal,

When you say it fails around 60MHz do you mean when you 
increase the clock the logic's running off to 60MHz?

If so it sounds like your new configuration is making
things a _bit_ better, but when you increase the clock
speed/current load it's going unstable again.

You intuitively might expect the regulator to have 
more overhead/be more stable when runing off the 5V as 
opposed to the 3.3V supply, so this seems logical.

Looks like you haven't got to the bottom of your problem
yet, keep denting that wall with your head.

Nial.

Article: 27845
Subject: Synplify PRO 6.1 + Foundation 3.1i
From: Michael Boehnel <boehnel@iti.tu-graz.ac.at>
Date: Tue, 12 Dec 2000 13:15:43 +0100
Links: << >>  << T >>  << A >>
I use Synplify PRO 6.1 in conjunction with Foundation 3.1i. When I
synthesize Synplicity's VHDL Tutorial on the Virtex50 with the described
timing constraints I get the expected maximum frequency of 85MHz. When I
place and route the design with Xilinx design manager I only get
68.2MHz. Where comes this difference from? Are the estimations of
Synplify that bad? I can't believe it.

Regards,

Michael

PS. The .ncf-File is in the same directory as the .edf-File.



Article: 27846
Subject: Re: Synplify PRO 6.1 + Foundation 3.1i
From: Magnus Homann <d0asta@mis.dtek.chalmers.se>
Date: 12 Dec 2000 13:46:49 +0100
Links: << >>  << T >>  << A >>
Michael Boehnel <boehnel@iti.tu-graz.ac.at> writes:

> I use Synplify PRO 6.1 in conjunction with Foundation 3.1i. When I
> synthesize Synplicity's VHDL Tutorial on the Virtex50 with the described
> timing constraints I get the expected maximum frequency of 85MHz. When I
> place and route the design with Xilinx design manager I only get
> 68.2MHz. Where comes this difference from? Are the estimations of
> Synplify that bad? I can't believe it.

20% off isn't too bad, in my experience. At least for a first try.

Homann
-- 
Magnus Homann, M.Sc. CS & E
d0asta@dtek.chalmers.se

Article: 27847
Subject: Re: Synplify PRO 6.1 + Foundation 3.1i
From: Nial Stewart <nials@sqf.hp.com>
Date: Tue, 12 Dec 2000 14:37:30 +0000
Links: << >>  << T >>  << A >>
Michael Boehnel wrote:
> 
> I use Synplify PRO 6.1 in conjunction with Foundation 3.1i. When I
> synthesize Synplicity's VHDL Tutorial on the Virtex50 with the described
> timing constraints I get the expected maximum frequency of 85MHz. When I
> place and route the design with Xilinx design manager I only get
> 68.2MHz. Where comes this difference from? Are the estimations of
> Synplify that bad? I can't believe it.
                     ^^^^^^^^^^^^^^^^^^

Why not? In the latest big FPGAs the delays are dominated by
routing delays, not logic delays, so the synthesis tool
has no direct information about the biggest factor affecting
the speed of a design.

The synthesis tools have to work with rules of thumb that have
been empirically derived, so 20% out isn't too bad.

Nial.

Article: 27848
Subject: Re: dual port ram for altera
From: Ray Andraka <ray@andraka.com>
Date: Tue, 12 Dec 2000 16:07:12 GMT
Links: << >>  << T >>  << A >>
Altera RAMs are NOT true dual port, in that you can't do both a read and a write
from one port.  Here's a quick summary:

Altera 10K.  Not dual port at all.  Address is shared for read and write, but
data is separated.  This is a single port memory with separated data I/O

Altera 10KE, 20K, and 20KE.  The memory has separate read and write addresses. 
This allows unidirectional dual port operation similar to the dual port mode of
the CLB RAM in Xilinx devices.  In this case, the memory can be read from and
written to at different addresses in the same clock cycle, but the write port is
a write-only port and the read port is read-only.  Both sides of the memory
share the same organization (ie 1Kx2, 256x8 etc).

Virtex block RAM:  These memories are true dual port.  Both ports may be
independently read or written to.  The organization at each port can also be set
independently.

For many applications, the unidirectional dual port is sufficient.  Other
applications work better when there is full access through both ports.



alexkarpel@my-deja.com wrote:
> 
> I used lpm_ram_dp to implement histogram function. At the same clock
> you canread and write to the memory. My board is not yet ready, but I
> checked thisfunction by simulation in MAX II 10KE family and compiled
> this function forAPEX20KE. It seems that this function is working good.
> In my designs I usedfifo's with different read and write clocks for
> 10KE and 20KE.
> Ray Andraka wrote that RAM in Altera is not true dual port ram, but it
> was for the 10K family, and in the 10KE and 20K, 20KE as I understand
> it is real dual port memory.
> 
>  Alex
> 
> In article <3A32A6E7.2DAC2045@andraka.com>,
>   Ray Andraka <ray@andraka.com> wrote:
> > The ESB RAM in the Altera 20K is not a true dual port RAM.  It has a
> read port
> > and a write port.  In order to make it look like a dual port RAM, you
> need to
> > clock it at 2x your data clock to do 2 accesses per clock.  Depending
> on your
> > system clock, you may not be able to do that with one ESB.  You can
> also double
> > the number of ESBs so that you read or write two words for one
> virtual port on
> > even clocks and 2 words for the other virtual port on odd clocks.
> >
> > Xilinx Virtex's block RAM is a true dual port RAM, so you have
> independent
> > read/write access to both ports, even if the clocks are different.
> >
> > Jerry Pongstaporn wrote:
> > >
> > > has anyone tried to implement a true dual port ram in an altera 20k
> > > device.  by true dual port, i mean you can write and read both
> ports.
> > > the only lpm they offer is lpm_ram_dp.  but that only allows you to
> > > write one port and read the other.  i also tried the csdpram
> function
> > > they offer, but i cannot get that to work.  that is a cycle-shared
> dual
> > > port ram.  xilinx has a true dual port in their libraries, but i
> would
> > > rather not switch from altera at this point.  has anyone else run
> into
> > > this before?  btw, i am synthesizing vhdl with synplicity, and using
> > > quartus for place and route.
> >
> > --
> > -Ray Andraka, P.E.
> > President, the Andraka Consulting Group, Inc.
> > 401/884-7930     Fax 401/884-7950
> > email ray@andraka.com
> > http://www.andraka.com  or http://www.fpga-guru.com
> >
> 
> Sent via Deja.com http://www.deja.com/
> Before you buy.

-- 
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com  or http://www.fpga-guru.com

Article: 27849
Subject: Re: Synplify PRO 6.1 + Foundation 3.1i
From: Michael Boehnel <boehnel@iti.tu-graz.ac.at>
Date: Tue, 12 Dec 2000 18:10:16 +0100
Links: << >>  << T >>  << A >>
Hi, Magnus and Neal!

Thanks for your hints. First I thought I've forgotten to take over constraints
to P&R. But as you explained the result seems reasonable now.
I will take the estimated frequencies with caution.

Michael

But why do real things always become worse than estimated? ;-)





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