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Messages from 27850

Article: 27850
Subject: Re: Synplify PRO 6.1 + Foundation 3.1i
From: "Joel Kolstad" <JoelKolstad@Earthlink.Net>
Date: Tue, 12 Dec 2000 17:39:00 GMT
Links: << >>  << T >>  << A >>
"Michael Boehnel" <boehnel@iti.tu-graz.ac.at> wrote in message
news:3A365BF8.DC3B8F2@iti.tu-graz.ac.at...
> But why do real things always become worse than estimated? ;-)

They don't.  In particular, if you've gone off and floorplanned parts of
your design, Synplify may very well come back with a much more pessimistic
clock rating that what you'll actually get our of PAR.

---Joel Kolstad




Article: 27851
Subject: Re: Synplify PRO 6.1 + Foundation 3.1i
From: Nial Stewart <nials@sqf.hp.com>
Date: Tue, 12 Dec 2000 17:49:30 +0000
Links: << >>  << T >>  << A >>
Michael Boehnel wrote:
> 
> Hi, Magnus and Neal!
> 
> Thanks for your hints. First I thought I've forgotten to take over constraints
> to P&R. But as you explained the result seems reasonable now.
> I will take the estimated frequencies with caution.
> 
> Michael
> 
> But why do real things always become worse than estimated? ;-)

Not always!

You'll find that if your place and route tools give timing
errors a design may well work (as long as you're not too
far out), or you will be able to clock it faster than
the tools report.

The timing figures used here are for absolute worst case,
highest temperatures and lowest voltages so that if the 
design 'passes' it will work under all rated conditions.

Of course it's not good practice to consider a design
'finished' until it's giving no timing errors, even if
it appears to work on the bench.

Nial.

Article: 27852
Subject: Re: Xilinx CPLD capable of driving LEDs
From: PeteD <pdowell@mil-x-dig.com>
Date: Tue, 12 Dec 2000 17:54:52 GMT
Links: << >>  << T >>  << A >>
The XC9500 series (5 volt parts) outputs can sink 24 mA. Just watch the total
power disipation.

Article: 27853
Subject: Re: Synplify PRO 6.1 + Foundation 3.1i
From: Michael Boehnel <boehnel@iti.tu-graz.ac.at>
Date: Tue, 12 Dec 2000 18:58:18 +0100
Links: << >>  << T >>  << A >>
Joel Kolstad wrote:

> "Michael Boehnel" <boehnel@iti.tu-graz.ac.at> wrote in message
> news:3A365BF8.DC3B8F2@iti.tu-graz.ac.at...
> > But why do real things always become worse than estimated? ;-)
>
> They don't.  In particular, if you've gone off and floorplanned parts of
> your design, Synplify may very well come back with a much more pessimistic
> clock rating that what you'll actually get our of PAR.
>
> ---Joel Kolstad

Joel,

you're right. I already have a design where I get the following results:

Synplicity estimated: 164MHz
P&R (after Synplicity Synthesis): 215MHz
P&R (after FPGA Express Synthesis): 126MHz

Same #CLBs used for both synthesis tools.

Michael



Article: 27854
Subject: Re: Xilinx CPLD capable of driving LEDs
From: Peter Alfke <peter.alfke@xilinx.com>
Date: Tue, 12 Dec 2000 10:39:34 -0800
Links: << >>  << T >>  << A >>
The CPLD and FPGA outputs have an I/V characteristic (IBIS model), a max dc
current ( metal migration), and a limited power dissipation.
They "know" nothing about LEDs.
So you have to specify and evaluate this in terms of current, voltage, and
power.
That's why it is impossible to answer your question.

Peter Alfke
=======================================
Damir Danijel Zagar wrote:

> Which Xilinx CPLD is capable of driving multiple LEDS or segment displays
> (>50).
>
> Is XC9500XL family good for this application, or should I look into FPGA
> families
> (i.e. Spartan II).
>
> Thanks,
>
> Damir


Article: 27855
Subject: Fpga Newbie
From: Joel Smith <joels@mobyfoo.NOSPAMorg>
Date: Tue, 12 Dec 2000 20:21:22 +0000
Links: << >>  << T >>  << A >>
Hi,

I have just recently come across fpga's and decided that I might have a
play with them. The prototyping kit I thought I might buy is the
BED-SPARTAN2+ from http://www.BurchED.com.au/. It seems quite good
value, even with the extra plug-on modules! What do people think about
this kit?

Also do the development boards come with the fpga soldered to the board
or is it detachable? If you are building a device round the fpga does
the board have to become part of the device or can you simply unplug the
fpga and use it on its own? I realize that you would have to use a
eeprom chip to hold the fpga design. It just seems sort of nasty that if
you are making a number of devices that you would have to include a new
prototyping board with each device.

Thanks in advance,

Joel.

Article: 27856
Subject: Re: Synplify PRO 6.1 + Foundation 3.1i
From: Ray Andraka <ray@andraka.com>
Date: Tue, 12 Dec 2000 20:42:25 GMT
Links: << >>  << T >>  << A >>
For floorplanned designs, I find the synplicity numbers are consistently
pessimistic.

Michael Boehnel wrote:
> 
> Hi, Magnus and Neal!
> 
> Thanks for your hints. First I thought I've forgotten to take over constraints
> to P&R. But as you explained the result seems reasonable now.
> I will take the estimated frequencies with caution.
> 
> Michael
> 
> But why do real things always become worse than estimated? ;-)

-- 
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com  or http://www.fpga-guru.com

Article: 27857
Subject: Re: Fpga Newbie
From: Terry Hicks <hicksthe@egr.msu.edu>
Date: Tue, 12 Dec 2000 15:54:39 -0500
Links: << >>  << T >>  << A >>
Joel,
    You definately do NOT need a new board for each system.  You obviously
need to include the FPGA and EEPROM in the new design.  This is fairly well
documented in the various notes, etc. from XILINX.  It is not especially
difficult to do.  I am not familiar with the board you mentioned.  (My first
design went straight to FPGA and EEPROM from simulation/verification.)  I
had a few problems finding out all the tricks but it appears that the new
notes for the Virtex chip do a better job of tying it all together.  If you
have a problem when you get to that point send me e-mail and I will give you
what I found worked with the SPARTANXL series parts.  They all seem to have
similar configuration requirements.
Theron Hicks

Joel Smith wrote:

> Hi,
>
> I have just recently come across fpga's and decided that I might have a
> play with them. The prototyping kit I thought I might buy is the
> BED-SPARTAN2+ from http://www.BurchED.com.au/. It seems quite good
> value, even with the extra plug-on modules! What do people think about
> this kit?
>
> Also do the development boards come with the fpga soldered to the board
> or is it detachable? If you are building a device round the fpga does
> the board have to become part of the device or can you simply unplug the
> fpga and use it on its own? I realize that you would have to use a
> eeprom chip to hold the fpga design. It just seems sort of nasty that if
> you are making a number of devices that you would have to include a new
> prototyping board with each device.
>
> Thanks in advance,
>
> Joel.


Article: 27858
Subject: Re: ActelDeskTop Macro fanout problem
From: johne@vcd.hp.com (John Eaton)
Date: 12 Dec 2000 22:39:01 GMT
Links: << >>  << T >>  << A >>
Nick (virg.in@virgin.net) wrote:
: Hi,

: I recently created a 16 bit wide counter using the ActGen macro tool in
: ActelDesktop.
: Everything was fine up until the point where I compiled the design using
: Actel Designer. The compilations only error is that the clock fanout inside
: the macro is 32, which exceeds the error limit of 24.
: I then 'hacked' the macros VHDL  to incorporate a buffer every 4 FF's in the
: counter chain. This made no difference to the compiler , still getting
: exactly the same error.

: Due to time restraints I have had to redesign the counter using two 8-bit
: counter macros cascaded (this gives a 2 fanout warnings of 16 - below the
: error limit but above recommended limit ).

: If anyone can shed any light on this problem I would be very grateful

: Cheers

: Nick


Actel parts have global clock nets that have no problem with fanouts. 



John Eaton

 


Article: 27859
Subject: TWo CLOKS in VHDL synthesis
From: "Qian Zhang" <qianz@cae.wisc.edu>
Date: Tue, 12 Dec 2000 18:41:16 -0600
Links: << >>  << T >>  << A >>


I have once read one book on VHDL
it says that in the design no two clock permitted
which means
I could not use
rising_edge(STRB)
rising_edge(CLK)
at the same time.
But I did not remember that correctly?
Anyone have idea?
Thanks a lot!




Article: 27860
Subject: Re: Synplify PRO 6.1 + Foundation 3.1i
From: Kent Orthner <korthner@hotmail.nospam.com>
Date: 13 Dec 2000 10:20:13 +0900
Links: << >>  << T >>  << A >>
Michael Boehnel <boehnel@iti.tu-graz.ac.at> writes:
> you're right. I already have a design where I get the following results:
> 
> Synplicity estimated: 164MHz
> P&R (after Synplicity Synthesis): 215MHz
> P&R (after FPGA Express Synthesis): 126MHz
> 
> Same #CLBs used for both synthesis tools.
> 
> Michael

Ack!

I've heard people say over and over that Synplicity is far and away 
better than FPGA Express, but 215MHz vs. 126MHz for the same design?

This is the same input files and the same PnR software, right?

Does anyone else have comparison numbers?

Thanks!

-Kent

Article: 27861
Subject: Re: TWo CLOKS in VHDL synthesis
From: Kent Orthner <korthner@hotmail.nospam.com>
Date: 13 Dec 2000 10:25:37 +0900
Links: << >>  << T >>  << A >>
Hi!

It's perfectly acceptable to use more than 
one clock in a given design.

However, if your design is going to be synthesized and 
then implemented, then you can not use two clocks in 
the same process.  That would be telling the synthesis 
tools to use a flip-flop with two clock inputs (Which 
I have yet to see).

If you do use two clocks in your design, then you have 
to watch out for any place that your data crosses clock 
boundaries, guard against metastable events, and so on.

If it's only for simulation, then there is no problem 
using two clocks inside a process.

Hope this helps,
-Kent

"Qian Zhang" <qianz@cae.wisc.edu> writes:
> I have once read one book on VHDL
> it says that in the design no two clock permitted
> which means
> I could not use
> rising_edge(STRB)
> rising_edge(CLK)
> at the same time.
> But I did not remember that correctly?
> Anyone have idea?
> Thanks a lot!

Article: 27862
Subject: Re: TWo CLOKS in VHDL synthesis
From: "Qian Zhang" <qianz@cae.wisc.edu>
Date: Tue, 12 Dec 2000 20:37:29 -0600
Links: << >>  << T >>  << A >>
Kent

Thank you very much!
Here I have problem in implementing my VHDL design
since for some registers I used STRB as clock to control its writing,
for some other registers I used CLK as clock
I don't know whether it is the key which hooked me from implementing it


Kent Orthner <korthner@hotmail.nospam.com> wrote in message
news:wklmtlw1ri.fsf@hotmail.nospam.com...
> Hi!
>
> It's perfectly acceptable to use more than
> one clock in a given design.
>
> However, if your design is going to be synthesized and
> then implemented, then you can not use two clocks in
> the same process.  That would be telling the synthesis
> tools to use a flip-flop with two clock inputs (Which
> I have yet to see).
>
> If you do use two clocks in your design, then you have
> to watch out for any place that your data crosses clock
> boundaries, guard against metastable events, and so on.
>
> If it's only for simulation, then there is no problem
> using two clocks inside a process.
>
> Hope this helps,
> -Kent
>
> "Qian Zhang" <qianz@cae.wisc.edu> writes:
> > I have once read one book on VHDL
> > it says that in the design no two clock permitted
> > which means
> > I could not use
> > rising_edge(STRB)
> > rising_edge(CLK)
> > at the same time.
> > But I did not remember that correctly?
> > Anyone have idea?
> > Thanks a lot!



Article: 27863
Subject: Re: TWo CLOKS in VHDL synthesis
From: Kent Orthner <korthner@hotmail.nospam.com>
Date: 13 Dec 2000 12:50:07 +0900
Links: << >>  << T >>  << A >>
"Qian Zhang" <qianz@cae.wisc.edu> writes:

> Kent
> 
> Thank you very much!
> Here I have problem in implementing my VHDL design
> since for some registers I used STRB as clock to control its writing,
> for some other registers I used CLK as clock
> I don't know whether it is the key which hooked me from implementing it

There should be no problem using STRB as a clock for some 
registers, and using CLK as a clock for other registers.

Just make sure you don't have them in the same process.

HTH,  Kent.


Article: 27864
Subject: Synthesis Tools
From: "Kirk A Daley" <kdaley@ccf.nrl.navy.mil>
Date: Wed, 13 Dec 2000 01:23:19 -0500
Links: << >>  << T >>  << A >>
I was using Orcad Express for my FPGA designs because I really liked the
idea
of schematic entry rather than HDL.   Oracd have discontinued their (in
house )
Synthesis tool I am now in search of  a suitable workaround.   How does  the
following
tools compare to each other by performance, price, and ease of use.   Could
anyone
explain why the various licensing options for these tools so expensive?

1.   Simplicity - Simplify, Simplify Pro
2.    Exemplar  - Leonardo Spectrum
3.    Accolade  - Metamor

Thanks
Kirk



Article: 27865
Subject: fpga :CLB locking prevents flops to be in IOB's
From: "Nisreen Taiyeby" <nisreen@bangalore.coreel.com>
Date: Tue, 12 Dec 2000 23:14:57 -0800
Links: << >>  << T >>  << A >>
When I use the LOC constraint on a sub-module (to lock it in a particular region of the FPGA) I see that the -pr b (lock input/output flops in IOB) to be overridden.
This results in poor pad to setup and setup to pad timings.

Using the IOB=True on the identified flops in the design and Then identifying the remaining portion of the design for CLB locking is one way out but very timeconsuming and tedious.

Does anyone know a better way out.

Article: 27866
Subject: Re: Synplify PRO 6.1 + Foundation 3.1i
From: Michael Boehnel <boehnel@iti.tu-graz.ac.at>
Date: Wed, 13 Dec 2000 09:48:44 +0100
Links: << >>  << T >>  << A >>
> I've heard people say over and over that Synplicity is far and away
> better than FPGA Express, but 215MHz vs. 126MHz for the same design?
>
> This is the same input files and the same PnR software, right?
>
> Does anyone else have comparison numbers?
>
> Thanks!
>
> -Kent

Same inputs files (incl. .UCF) and same PnR.

But I think it isn't serious to take this single result to compare the two
synthesis tools. Additionally the design was very simple. I just wanted to
show an example for the big range of resulting frequency ranges.

Michael




Article: 27867
Subject: Re: fpga :CLB locking prevents flops to be in IOB's
From: Andreas Doering <doering@iti.mu-luebeck.de>
Date: Wed, 13 Dec 2000 09:58:22 +0100
Links: << >>  << T >>  << A >>
Nisreen Taiyeby wrote:
> 
> When I use the LOC constraint on a sub-module (to lock it in a particular region of
> the FPGA) I see that the -pr b (lock input/output flops in IOB) to be overridden.
> This results in poor pad to setup and setup to pad timings.
I had the same problem, but it is consequent: 
if you put a 
INST mymodule LOC=CLB_RxCy:... ;
whatever constraint, putting FFs from that design into IOB obviously 
hurts the constraint. 
Therefore I used to add an extra level of hierarchy and putting the 
FFs in the outer level. 
I use a Synopsys-VHDL design flow and it is therefore hard 
to assign attributes to FFs infered by the synthesizer. 

> Does anyone know a better way out.
What do you think, is this better?
Andreas

- -  
---------------------------------------------------------------
                        Andreas C. Doering
                        Medizinische Universitaet zu Luebeck
                        Institut fuer Technische Informatik
		        Tel.: +49 451 500-3741, Fax: -3687
		        Email: doering@iti.mu-luebeck.de
                        Home: http://www.iti.mu-luebeck.de/~doering 
"The fear of the LORD is the beginning of ... science" (Proverbs 1.7)
----------------------------------------------------------------

Article: 27868
Subject: Re: dual port ram for altera
From: "Karpel Alex" <alex@cmt.co.il>
Date: Wed, 13 Dec 2000 09:31:24 -0000
Links: << >>  << T >>  << A >>
I used lpm_ram_dp to implement histogram function. At the same clock you can
read and write to the memory. My board is not yet ready, but I checked this
function by simulation in MAX II 10KE family and compiled  this function for
APEX20KE. It seems that this function is working good. In my designs I used
fifo's with different read and write clocks for 10KE and 20KE.
Ray Andraka wrote that RAM in Altera is not true dual port ram, but it was
for the 10K family, and in the 10KE and 20K, 20KE as I understand it is real
dual port memory.

 Alex


Ray Andraka <ray@andraka.com> wrote in message
news:3A32A6E7.2DAC2045@andraka.com...
> The ESB RAM in the Altera 20K is not a true dual port RAM.  It has a read
port
> and a write port.  In order to make it look like a dual port RAM, you need
to
> clock it at 2x your data clock to do 2 accesses per clock.  Depending on
your
> system clock, you may not be able to do that with one ESB.  You can also
double
> the number of ESBs so that you read or write two words for one virtual
port on
> even clocks and 2 words for the other virtual port on odd clocks.
>
> Xilinx Virtex's block RAM is a true dual port RAM, so you have independent
> read/write access to both ports, even if the clocks are different.
>
> Jerry Pongstaporn wrote:
> >
> > has anyone tried to implement a true dual port ram in an altera 20k
> > device.  by true dual port, i mean you can write and read both ports.
> > the only lpm they offer is lpm_ram_dp.  but that only allows you to
> > write one port and read the other.  i also tried the csdpram function
> > they offer, but i cannot get that to work.  that is a cycle-shared dual
> > port ram.  xilinx has a true dual port in their libraries, but i would
> > rather not switch from altera at this point.  has anyone else run into
> > this before?  btw, i am synthesizing vhdl with synplicity, and using
> > quartus for place and route.
>
> --
> -Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930     Fax 401/884-7950
> email ray@andraka.com
> http://www.andraka.com  or http://www.fpga-guru.com





Article: 27869
Subject: Hold time constraint in Xilinx?
From: mark4415@my-deja.com
Date: Wed, 13 Dec 2000 10:41:41 GMT
Links: << >>  << T >>  << A >>
How do I set a hold time constraint in xilinx?

I have a design with many input busses each with their own clock (too many to
use DLL/dedicated clock routing resources). Currently some inputs have
excesive hold times. How can I specify a hold time requirement for each the
input buses in the .ucf file? (Set up is no problem with the OFFSET IN
BEFORE)

Mark.


Sent via Deja.com
http://www.deja.com/

Article: 27870
Subject: Hold time constraints in virtex?
From: Mark Russell <mark4415@my-deja.com>
Date: Wed, 13 Dec 2000 10:52:17 GMT
Links: << >>  << T >>  << A >>
How do I set a hold time constraint in virtex?

I have a design where there are many input busses each with their own
clock(too many to use dedicated clock resources).

I can set up a setup constraint using OFFSET IN BEFORE, but how do I set
a hold time requirement?


Sent via Deja.com
http://www.deja.com/

Article: 27871
Subject: Configuration : XC4000
From: "Ralph Friedrich" <Ralph.Friedrich@erlf.siemens.de>
Date: Wed, 13 Dec 2000 03:51:06 -0800
Links: << >>  << T >>  << A >>
How are the 4 CRC bits in XC4000 configuration bitstream build?

The procedure for the readback bitstream is descriped in databook.

Is it the same LFSR generator?
Which bits are used for CRC generation?
Which bits of the CRC are placed in the 4 bit positions?

Anyone have idea?
Thanks a lot!

Article: 27872
Subject: Re: Synplify PRO 6.1 + Foundation 3.1i
From: eml@riverside-machines.com.NOSPAM
Date: Wed, 13 Dec 2000 12:14:37 GMT
Links: << >>  << T >>  << A >>
On Tue, 12 Dec 2000 14:37:30 +0000, Nial Stewart <nials@sqf.hp.com>
wrote:

>Michael Boehnel wrote:
>> 
>> I use Synplify PRO 6.1 in conjunction with Foundation 3.1i. When I
>> synthesize Synplicity's VHDL Tutorial on the Virtex50 with the described
>> timing constraints I get the expected maximum frequency of 85MHz. When I
>> place and route the design with Xilinx design manager I only get
>> 68.2MHz. Where comes this difference from? Are the estimations of
>> Synplify that bad? I can't believe it.
>                     ^^^^^^^^^^^^^^^^^^
>
>Why not? In the latest big FPGAs the delays are dominated by
>routing delays, not logic delays, so the synthesis tool
>has no direct information about the biggest factor affecting
>the speed of a design.
>
>The synthesis tools have to work with rules of thumb that have
>been empirically derived, so 20% out isn't too bad.
>
>Nial.

I had this argument with a Sprectrum rep last year. I asked why the
timing estimates could be up to 50% out, and he got annoyed. He
started on about how clever their statistical load models were, and
said the results were 'accurate'. I couldn't be bothered to provide
any test cases to demonstrate the obvious, and that was the end of the
conversation. It occurred to me afterwards that you could believe that
the timing estimates were accurate, if the synth was pessimistic, and
PAR stopped running as soon as it reached target. In fact, it could be
100% accurate.

This probably means that the current generation of FPGA physical
synthesis tools are worthless. The good news is that Virtex-II routing
should be much more predictable, so the situation should get better.

Evan

Article: 27873
Subject: Dual-ported RAM instantiation in Virtex-E ?
From: Marcel Melters <marcel.melters@philips.com>
Date: Wed, 13 Dec 2000 13:14:43 +0100
Links: << >>  << T >>  << A >>
Hi,
I'm currently working on a VHDL design running in a Virtex-50E chip.
I need a Dual-ported RAM in this design, but I'm having trouble
instantiating a Block-RAM for this.
I'm using Exemplar Leonardo. I am aware that there is an application
note explaining how to instantiate a SINGLE-port RAM as Block-RAM,
but when I try and modify this to a dual-port setup, the synthesizer
simply
refuses to use the block-ram.
I guess I'm missing something here, but can anyone shed some light on
this ?
Any help is much appreciated.

===============================================================
Ing. Marcel Melters                     Philips Medical Systems
Hardware engineer                       Veenpluis 6
MR-backend  room QR-2352             5684 PC  Best
mailto: marcel.melters@philips.com      P.O. box 10000
phone +31 40 27 63266                   5680 DA  Best
fax   +31 40 27 63771                   The Netherlands
===============================================================
... deadlines? I like deadlines ...
    I like the "whoosh" sound they make when they rush past ...
   Douglas Adams, author of T.H.H.G.T.T.G.



Article: 27874
Subject: Re: Hold time constraints in virtex?
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Wed, 13 Dec 2000 13:36:40 +0000
Links: << >>  << T >>  << A >>


Mark Russell wrote:

> How do I set a hold time constraint in virtex?
>
> I have a design where there are many input busses each with their own
> clock(too many to use dedicated clock resources).
>
> I can set up a setup constraint using OFFSET IN BEFORE, but how do I set
> a hold time requirement?
>
> Sent via Deja.com
> http://www.deja.com/

Basically you can't. Hold time is supposed to be taken care of, if a global
clock is used, by the design guarantees:

(1) The global pin-pin su/hld characteristics of the IOB FFs. 1.5/-0.4 if
the DLL
is used and 2.1/0 if no DLL & input delay is set.

(2) For any pair of FFs Tco(min) + routing(min) > Tgclkskew.

Unfortunately this leaves open the case where you have an input from a pin
feeding an internal (not IOB) FF. Assuming 0 hold time at the pin, you need
to know whether the

(3) No DLL: routing delay of the input is always > global clock routing, or

(4) DLL: the routing delay > DLL jitter + phase delay.

It would seem that (1), (2), (4) cover it *But* in the case of PCI the clock
frequency is allowed to vary or even stop so you can't use a DLL in systems
where this may happen. The Xilinx tools don't give a lot of help in
analysing case (3) esp. since the min delays for device families don't
usually get published for up to a year after device introduction - if ever.





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