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Messages from 28000

Article: 28000
Subject: how to bind xilinx lib to activeHDL?
From: xiaoqiang@my-deja.com
Date: Tue, 19 Dec 2000 10:09:11 GMT
Links: << >>  << T >>  << A >>
I download the activeHDL 4.1 and xilinx verilog library,and install it
successfully.  But it seems the xilinx lib don't bind the activeHDL.
When i configure the device in flow setting, the console display
warning message: Library VIRTEX required for the selected device has
not been installed. (I can see the xilinx lib in "Verilog Library" tab
in "Design setting" menu).

Further,when I run timing simulation,the console display:
ELBREAD: Warning: No design unit found (library simprim_edif ,name
x_or2).
ELBREAD:Warning: Component .UUT.count_reg_1_GSR_OR :x_or2 not bound.
etc.

Is the situation lib problem?
So what's the step to bind the lib to design?

Regards
Frank


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Article: 28001
Subject: Re: 3V -> 5V clock signal level conversion
From: Tomppa <apsku@my-deja.com>
Date: Tue, 19 Dec 2000 11:02:02 GMT
Links: << >>  << T >>  << A >>
Hi,

You could use HCT- logic since it's inputs high-state
is about 2.4V. I read this at some manufactures datasheets
so that should be ok. At least Philips (and maybe others)
have single logic ports in one tiny package (picogate).

If your clock inputs are allready TTL- compatible,
there's no problem to drive those signals directly.

I have used this method in my mp3 player (still proto)
where the decoder works with 3.3V and the dac (CS4334)
needs 5V supply. According to dac's datasheets it's
inputs are TTL-compatible. Works fine!

Hope this helps.


Tommi


In article <3A3F3339.AC12CB9E@sqf.hp.com>,
  nials@sqf.hp.com wrote:
> I'm looking at a problem where we need to drive a
> couple of 5V CMOS clock inputs from a SpartanII
> 3v output.
>
> There are data lines being driven from the 3V output,
> we can get away with the 'tristate and pull high
> for logic high' trick, but I don't want to do this with
> the clock signals. The active (rising) edges are
> _very_ slow and the risk of double clocking etc
> would be too high.
>
> Space is fairly tight so my immediate thought was
> to use an 8 pin soic dual comparator with the -ve
> input tied to 1.8V (power plane).
>
> My only concern with this is that I think I read a
> while ago that comparators shouldn't be used for this
> sort of application, I can't remember where I read this
> so I can't check if I'm right. It might have been
> because of the lask of hysteresis on the input,
> but if the -ve input is set to a 'clean' part
> of the waveform I don't think we should see
> any problems.
>
> Can anyone think of any drawbacks of using a fast
> comparator for this conversion?
>
> Nial.
>


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Article: 28002
Subject: Re: JTAG protocol
From: sulimma@my-deja.com
Date: Tue, 19 Dec 2000 11:55:37 GMT
Links: << >>  << T >>  << A >>
In article <3A3DD507.F7214EBF@wp.pl>,
  Daniel =?iso-8859-1?Q?Ha=F1czewski?= <danhan@wp.pl> wrote:
> Dear all,
I allways wondered, whether it would be possible to configure an FPGA
PCI interface using PCIs JTAG pins. This would allow you to get rid of
the expensive configuration ROM.

However, the JTAG pins are optional for the PCI standard and such a
device would only work in mainboards that support jtag.

Also, I do not think that there is a common way to access the jtag
functions of a mainboard. So you probably would need to obtain
seperate drivers for each mainboard.

Also, as you only configure your board after your operation system
has been booted, you can not use much of the plug and play
functionality. (No big deal :-)

Kolja
> I'm developing a PCI card with Xilinx's XC9572 on board and I have a
> problem. I would like to use PCI bus to program XC9572 via JTAG
> interface. This solution would allow me to program the card without
> opening computer case and in the future remotely with a use of a
modem.
>


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Article: 28003
Subject: Re: FPGA and Board for Microprocessor Design?
From: Dave Vanden Bout <devb@xess.com>
Date: Tue, 19 Dec 2000 06:55:50 -0500
Links: << >>  << T >>  << A >>
hoyte@ucsu.colorado.edu wrote:

> I recently worked on a senior project where we designed a 16-bit RISC
> microprocessor, and implemented the design in an FPGA. I'd like to be
> able to do something similar on my own, and I'm trying to find a good
> FPGA/board combination that is (relatively) affordable, and compatible
> with the Xilinx student edition software. If anyone has any suggestions,
> they would be greatly appreciated.
>

I'll propose using an XS40 Board.  You can see more about those by checking
the links at http://www.xess.com/ho04000.html.  You can find information
about Jan Gray's XSOC CPU and associated C compiler that work with the
XS40-005XL Board at http://www.fpgacpu.org.

You can also look at the list of FPGA boards at http://www.optimagic.com.
The list summarizes various features and prices so you can make a quick
determination of suitable manufacturers.


--
|| Dr. Dave Van den Bout   XESS Corp.               (919) 387-0076 ||
|| devb@xess.com           2608 Sweetgum Dr.        (800) 549-9377 ||
|| http://www.xess.com     Apex, NC 27502 USA   FAX:(919) 387-1302 ||



Article: 28004
Subject: Methodology
From: bfredc@my-deja.com
Date: Tue, 19 Dec 2000 12:02:06 GMT
Links: << >>  << T >>  << A >>
Hi all,

I'm starting a new design using VIRTEX XCV600. I want to know if the
methodology is the same than with a device like XCV 50 ?

BFC


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Article: 28005
Subject: Re: Hold time constraints in virtex?
From: Mark Russell <mark4415@my-deja.com>
Date: Tue, 19 Dec 2000 13:07:49 GMT
Links: << >>  << T >>  << A >>
In article <3A377B68.26B507F1@algor.co.uk>,
  Rick Filipkiewicz <rick@algor.co.uk> wrote:
>
>
> Mark Russell wrote:
>
> > How do I set a hold time constraint in virtex?
> >
> > I have a design where there are many input busses each with their
own
> > clock(too many to use dedicated clock resources).
> >
> > I can set up a setup constraint using OFFSET IN BEFORE, but how do I
set
> > a hold time requirement?
> >
> > Sent via Deja.com
> > http://www.deja.com/
>
> Basically you can't. Hold time is supposed to be taken care of, if a
global
> clock is used, by the design guarantees:
>
> (1) The global pin-pin su/hld characteristics of the IOB FFs. 1.5/-0.4
if
> the DLL
> is used and 2.1/0 if no DLL & input delay is set.
>
> (2) For any pair of FFs Tco(min) + routing(min) > Tgclkskew.
>
> Unfortunately this leaves open the case where you have an input from a
pin
> feeding an internal (not IOB) FF. Assuming 0 hold time at the pin, you
need
> to know whether the
>
> (3) No DLL: routing delay of the input is always > global clock
routing, or
>
> (4) DLL: the routing delay > DLL jitter + phase delay.
>
> It would seem that (1), (2), (4) cover it *But* in the case of PCI the
clock
> frequency is allowed to vary or even stop so you can't use a DLL in
systems
> where this may happen. The Xilinx tools don't give a lot of help in
> analysing case (3) esp. since the min delays for device families don't
> usually get published for up to a year after device introduction - if
ever.
>
The best I have been able to do is set an impossible MAXDELAY for the
clock net. This obviously fails but gives a short clock track which
helps the hold time.

To improve the hold time further I would like to turn on the IOB delay.
How do you turn it ON?
My understanding is it defaults to on for registered inputs and may be
turned off using NODELAY.
What about non-registered inputs where the default seems to be off?


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Article: 28006
Subject: Re: Setup violation
From: Søren A.Møller <samtronic@my-deja.com>
Date: Tue, 19 Dec 2000 14:09:38 +0100
Links: << >>  << T >>  << A >>
In article <3A3EBCB4.93ADDE5B@xilinx.com>, peter.alfke@xilinx.com says...
<SNIP> 
> As I said, the gain of the slave latch makes that (almost) impossible.
> But I also question the importance of the question.
> For data, it is irrelevant whether it oscillates or not.

Not if the signal has different delays to the following FF's (assuming 
synchronous design) and therefore is interpreted as '0' at some FF's and 
'1' at others.

> And anybody using a metastable-prone signal as a clock should have his/her
> head examined.

Agreed.

Søren A.Møller

PS. I recommend 'The Commandments of Digital Design':

               The Commandments of Digital Design.
               ===================================

I)   Thou shalt have only one Master clock and thou shalt not
     build false idolatorous clocks from astables.

II)  Thou shalt not gate the clock, for that causeth false clock
     edges and skews.

III) Thou shalt make all circuits synchronous unless thou canst
     convince he who pays thy salary, or assigns thy marks, that
     for reasons such as speed, pulse capture, or paper publishing,
     synchronous circuits cannot serve thy purpose.

IV)  Thou shalt not associate with undesirables such as ripple counters
     and one shots, but cultivate friendships with Johnson counters and
     enabled flip-flops. 

V)   Thou shalt have a master reset for all filp-flops sp that the test
     engineer will love you, and you simulations will not remain           
     undefined for time eternal.

VI)  Thou shalt not let analog ground mix with digital ground, for                
     nothing but grief will come of such union.

VII) He shall not be held blameless, who leavith CMOS inputs open.

VIII) Asynchronous reset was not conceived for tasks such as returning a
      count to zero. Verily I say thee, that six circuitscreated after
      that manner will clear properly and bring honour to thy name, but
      the seventh shall fail and carry thee down in shame and disgrace. 

IX)  Raw asynchronous inputs are unclean, and must be cleansed by passing
     through a single D flip-flop before they are allowed access to thy
     pure and chaste variables.

X)   Ye who completely understand the reasons for the commandments, then
     ye also know what liberties can be taken with them. Ye who would            
     break them in ignorance, beware.

                                                   ----- Dr. John Knight

or http://www.cmc.ca/Design_Flows/commandments_digdesign.pdf
It seems that the 10th commandment is missing.

Article: 28007
Subject: Re: 3V -> 5V clock signal level conversion
From: Nial Stewart <nials@sqf.hp.com>
Date: Tue, 19 Dec 2000 13:24:58 +0000
Links: << >>  << T >>  << A >>
Tomppa wrote:

> You could use HCT- logic since it's inputs high-state
> is about 2.4V. I read this at some manufactures datasheets
> so that should be ok. At least Philips (and maybe others)
> have single logic ports in one tiny package (picogate).

Vinhigh for these two signals is 3.5V, and we're getting
a 'glitch' at ~2.4V that would cause double clocking if that
was the threshold.

I also don't think you can get any 74XX series devices in an
8 pin package.

Nial.

Article: 28008
Subject: New 200K gate, low cost FPGA proto kit
From: "Tony Burch" <tony@BurchED.com.au>
Date: Wed, 20 Dec 2000 00:35:07 +1100
Links: << >>  << T >>  << A >>
Announcing the new
BED-SPARTAN2+ FPGA Prototyping Kit

***Hot***
- 200,000 gates!!!  (Xilinx Spartan II device)
- free Xilinx Webpack software CD included
- introductory price US$120!!!

Great for some serious prototyping, or
for education.

See http://www.burched.com.au/bedspartan2.html
for full specs and secure online shop.

Low cost plug-on modules also available - great
companion modules for the BED-SPARTAN2+ kit:
- BED-SRAM (2 MBit)
- BED-FPGA-CPU-IO (for computer architecture experimenters)
- BED-7SEG-DISPLAYS
- BED-DIP-SWITCH
See http://www.burched.com.au/products.html

We currently have stock of all kits, but
stocks are decreasing rapidly (even before this
announcement).  Reserve your kit for the new year
by placing your order now!

Our secure online shop is open 365 days of the year,
and is accepting orders.  Please note, however, that
Burch Electronic Designs is closed until 2nd January 2001 -
we will start processing orders again on that day, in the
order that they were received over the break.

International orders are very welcome.

Best regards, and seasons greetings,

Tony Burch
www.BurchED.com.au




Article: 28009
Subject: Re: FPGA and Board for Microprocessor Design?
From: "Tony Burch" <tony@BurchED.com.au>
Date: Wed, 20 Dec 2000 00:51:31 +1100
Links: << >>  << T >>  << A >>
Hi Eric,
You may wish to consider the new, low cost
BED-SPARTAN2+ FPGA Protoyping Kit from
Burch Electronic Designs http://www.burched.com.au
(Also see announcement posted on this group
"New 200K gate, low cost FPGA proto kit")

There are also some very neat Plug-On Modules that
may be appropriate for you project:
- BED-SRAM (2 MBit)
- BED-FPGA-CPU-IO (for computer architecture experimenters)
- BED-7SEG-DISPLAYS
- BED-DIP-SWITCH
See http://www.burched.com.au/products.html

The Xilinx Webpack software CD comes in the box with
the kit.  Great free software, no license required!  Supports
Spartan II.  You can also download this software for free
from the Xilinx website.

200K gates is alot of gates :) Quite suitable for some
serious computer architecture investigation, and for
implementing your own RISC CPUs.  As an aside, here's
a link with some great work from the highly esteemed
Jan Gray: http://www.fpgacpu.org
Well worth a visit to this site.

Good luck with your project!

Best regards
Tony Burch
www.BurchED.com.au

<hoyte@ucsu.colorado.edu> wrote in message
news:91mdlq$pi6$1@nnrp1.deja.com...
> I recently worked on a senior project where we designed a 16-bit RISC
> microprocessor, and implemented the design in an FPGA. I'd like to be
> able to do something similar on my own, and I'm trying to find a good
> FPGA/board combination that is (relatively) affordable, and compatible
> with the Xilinx student edition software. If anyone has any suggestions,
> they would be greatly appreciated.
>
> Thanks,
> Eric Hoyt
>
>
> Sent via Deja.com
> http://www.deja.com/



Article: 28010
Subject: Question about Xilinx pins at high-frequency
From: "Pascal C." <>
Date: Tue, 19 Dec 2000 06:03:44 -0800
Links: << >>  << T >>  << A >>
I have 2 questions about Xilinx pins used in high-frequency designs.<br>
<br>
First:<br>
There are DFFs on the OE in VirtexE IOBs.  These, however, are not used by the PAR, even if they are needed.  When my colleague called Xilinx support, they said the only way was to use them was to use FPGA Editor and place them manually.  On a 32-bit bus, however, this is hardly practical (esp. since you have to do it on each implementation).<br>
<br>
Second:<br>
In another high-frequency design, I found it was necessary to put a FAST 12 mA DRIVE on an output pin.  However, in the lab, I saw it created a 1V overshoot on the LVTTL pin, which would damage external components.  I would like to reduce the drive, but PAR does not allow me to go below 12 mA: when I do attempt it, it tells me it cannot respect constraints.  However, it says this assuming a 35 pF load, when in fact I a have a much lighter 5 pF load.  Considering this load, I know I can go well below 12 mA, however PAR stops and refuses to go on despite violations.  Is there any work-around?

Article: 28011
Subject: Re: 3V -> 5V clock signal level conversion
From: Søren A.Møller <samtronic@my-deja.com>
Date: Tue, 19 Dec 2000 15:22:31 +0100
Links: << >>  << T >>  << A >>
In article <3A3F61AA.13A69394@sqf.hp.com>, nials@sqf.hp.com says...
> Tomppa wrote:
> 
> > You could use HCT- logic since it's inputs high-state
> > is about 2.4V. I read this at some manufactures datasheets
> > so that should be ok. At least Philips (and maybe others)
> > have single logic ports in one tiny package (picogate).
> 
> Vinhigh for these two signals is 3.5V, and we're getting
> a 'glitch' at ~2.4V that would cause double clocking if that
> was the threshold.
> 
> I also don't think you can get any 74XX series devices in an
> 8 pin package.

No, but you can get them in SOT23-5 and SC70-5 from e.g. TI:
http://www-s.ti.com/cgi-bin/sc/family3.cgi?family=SINGLE-GATES
or Fairchild (they have some in US-8):
http://www.fairchildsemi.com/products/logic/tinylogic/
or Philips:
http://www.philipslogic.com/products/picogate/
http://www.philipslogic.com/products/picogate/overview/
or Toshiba or On-semi and probably others.

Søren A.Møller

Article: 28012
Subject: Re: jtag for fpga
From: "Steven Zedeck" <saz@sonusnet.com>
Date: Tue, 19 Dec 2000 06:23:10 -0800
Links: << >>  << T >>  << A >>
Hi:
Assuming you always plan to program
the FPGAs via an on-board microprocessor (such as a PowerPC),
and you have many FPGAs (all different Xilinx) devices, why would you want to use a JTAG chain ?

Wouldn't it make sense to use serial
parallel mode and create seperate image files so that you can download any FPGA image you want at any time ? It also allows you to upgrade (in the field) any image without having to program/update them all. Comments ?

Also, has anyone done any analysis of the image sizes and time to program a JTAG chain with many FPGAs or to not use JTAG at all and
to program each image individually, one at a time ?
Thanks,
Steve

Article: 28013
Subject: Re: jtag for fpga
From: "Steven Zedeck" <saz@sonusnet.com>
Date: Tue, 19 Dec 2000 06:25:17 -0800
Links: << >>  << T >>  << A >>
Hi: Assuming you always plan to program the FPGAs via an on-board microprocessor (such as a PowerPC), and you have many FPGAs (all different Xilinx) devices, why would you want to use a JTAG chain ? 

Wouldn't it make sense to use serial parallel mode and create seperate image files so that you can download any FPGA image you want at any time ? It also allows you to upgrade (in the field) any image without having to program/update them all. Comments ? 

Also, has anyone done any analysis of the image sizes and time to program a JTAG chain with many FPGAs or to not use JTAG at all and to program each image individually, one at a time ? Thanks, Steve 
email: saz@sonusnet.com
Article: 28014
Subject: Re: jtag for fpga
From: "Steven Zedeck" <saz@sonusnet.com>
Date: Tue, 19 Dec 2000 06:48:59 -0800
Links: << >>  << T >>  << A >>
Hi: Assuming you always plan to program the FPGAs via an on-board microprocessor (such as a PowerPC), and you have many FPGAs (all different Xilinx) devices, why would you want to use a JTAG chain ? 

Wouldn't it make sense to use serial parallel mode and create seperate image files so that you can download any FPGA image you want at any time ? It also allows you to upgrade (in the field) any image without having to program/update them all. Comments ? 

Also, has anyone done any analysis of the image sizes and time to program a JTAG chain with many FPGAs or to not use JTAG at all and to program each image individually, one at a time ? Thanks, Steve 
email: saz@sonusnet.com
Article: 28015
Subject: Re: dual port ram for altera
From: bobdittmar@my-deja.com
Date: Tue, 19 Dec 2000 14:57:22 GMT
Links: << >>  << T >>  << A >>
Perhaps I was to abit to strong in my last reply but:

> Well, how far can we drive the definition of "true dual port RAM".
> Bob Dittmar thinks it should include an arbiter that resolves the
> case when both ports access the same location "kind of
> simultaneously".

I never indicated that I thought it should include an arbitor.

> Virtex BlockRAM has two totally independent ports accessing a common
> storage array.
> Both might access the same location.
> If one writes and the other one reads, it depends on the relative
> clock timing whether the reader gets the old or the new data. Note
> that read is a synchronous, clocked operation. Each port has its own
> clock.

I indicated that I thought the above statement didnot reflect what is
published. What is published is that the read port is invalid - not the
new or the previous data value is what is read.

> If both ports write, the one with the later clock wins. Definitely no
> damage.
> This operation is clear and unambiguous. Solving the contention in
> dedicated hardware would not be in the user's best interest.
>
I agreee completely.


I only posted response to original post because I am doing design with
common clock where 1 side constantly reads only and the other side
constantly writes.
I had several designeers tell me that the Xilinx DPRAM could handle this
without arbitration. I decided to verify it myself and found that not to
be true (or so I believe) so I added arbitartion. Yet my initial arch
did not have it. I would of found the problem in the lab at the
expense of other developers time.

So I was passing this along

Regards,
Bob Dittmar


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Article: 28016
Subject: Re: 3V -> 5V clock signal level conversion
From: Robert <romapa@earthlink.net>
Date: Tue, 19 Dec 2000 15:11:34 GMT
Links: << >>  << T >>  << A >>


Nial Stewart wrote:

> I'm looking at a problem where we need to drive a
> couple of 5V CMOS clock inputs from a SpartanII
> 3v output.
>
> There are data lines being driven from the 3V output,
> we can get away with the 'tristate and pull high
> for logic high' trick, but I don't want to do this with
> the clock signals. The active (rising) edges are
> _very_ slow and the risk of double clocking etc
> would be too high.
>
> Space is fairly tight so my immediate thought was
> to use an 8 pin soic dual comparator with the -ve
> input tied to 1.8V (power plane).
>
> My only concern with this is that I think I read a
> while ago that comparators shouldn't be used for this
> sort of application, I can't remember where I read this
> so I can't check if I'm right. It might have been
> because of the lask of hysteresis on the input,
> but if the -ve input is set to a 'clean' part
> of the waveform I don't think we should see
> any problems.
>
> Can anyone think of any drawbacks of using a fast
> comparator for this conversion?

Yes- the comparator has an even greater chance of producing double
clocking when driven directly off the line because of  an abrupt input
impedance change on switchover which interacts with the line impedance.
The time-tested technique for clean clock reception is the Schmitt
trigger with RC low pass filter at the input. Make the RC time constant
be something on the order of, or a bit longer than, the Tpd for the
Schmitt trigger. Usually a 100 ohm- 100pF will do just fine. This will
be suitable for an actual CW clock as well as an asynchronous clock used
to latch parallel data off a line which I take to be the application
here.

>
>
> Nial.


Article: 28017
Subject: Spartan2 and industrial temperatures
From: "Karl Olsen" <karl@micro-technic.com>
Date: Tue, 19 Dec 2000 16:14:42 +0100
Links: << >>  << T >>  << A >>
Hi,

According to ds001_1.pdf, some Spartan2 -5 speed grades are available in the
industrial temperature range -- this should mean that the worst-case timings
are guaranteed at die temperatures -40 to 100°C instead of 0 to 85°C.  What
does the "Temperature Prorating" then mean in the WebPack Timing Analyzer?

The Timing Analyzer allows Temperature Prorating down to -40°C.  Can
commercial grade parts safely be used down at these temperatures, and can I
expect other effects than faster timings and larger power-up currents?

Thanks a lot,
Karl Olsen



Article: 28018
Subject: Re: Setup violation
From: Greg Neff <gregneff@my-deja.com>
Date: Tue, 19 Dec 2000 15:28:43 GMT
Links: << >>  << T >>  << A >>
In article <3A3EBCB4.93ADDE5B@xilinx.com>,
  peter.alfke@xilinx.com wrote:
>
>
> Greg Neff wrote:
>
(snip)
>
> > IOW, they are both functioning as high gain inverting
> > amplifiers, with VOUT=VIN.  In this case, I would not be surprised
to
> > see some brief oscillation before the inverter pair snaps back to
> > stable digital operating area states.
>
> No, I don't see how such a primitive structure can sustain an
oscillation.
> Once it leaves its metastable balanced state, there is no way to
return
> back to or through it. ( As is possible in multi-stage structures
popular
> with TTL technology)
>

I'm thinking that the phase delay of noise amplified through the
inverters may permit a very brief low amplitude oscillation around Vth
before the latch stabilizes.  Depending on the structure of the flip-
flop, this oscillation could be amplified by the next stage.  This is
hypothetically speaking of course, I'm not saying that Xilinx FPGAs do
this.

(snip)
> But I also question the importance of the question.

Maybe not important from a practical perspective, but interesting none
the less.  I just wanted a little clarification on your statement in
your reply to the OP.

> For data, it is irrelevant whether it oscillates or not.

Irrelevant only if the data has one destination, hence the need for two-
stage synchronizers.

> And anybody using a metastable-prone signal as a clock should have
his/her
> head examined.

Absolutely right!  I was not, in any way shape or form, implying that
this should be done.

--
Greg Neff
VP Engineering
*Microsym* Computers Inc.
greg@guesswhichwordgoeshere.com


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Article: 28019
Subject: Re: Question about Xilinx pins at high-frequency
From: Greg Neff <gregneff@my-deja.com>
Date: Tue, 19 Dec 2000 15:43:06 GMT
Links: << >>  << T >>  << A >>
In article <ee6f135.-1@WebX.sUN8CHnE>,
  "Pascal C." <> wrote:
(snip)
> Second:<br>
> In another high-frequency design, I found it was necessary to put a
FAST 12 mA DRIVE on an output pin.  However, in the lab, I saw it
created a 1V overshoot on the LVTTL pin, which would damage external
components.  I would like to reduce the drive, but PAR does not allow
me to go below 12 mA: when I do attempt it, it tells me it cannot
respect constraints.  However, it says this assuming a 35 pF load, when
in fact I a have a much lighter 5 pF load.  Considering this load, I
know I can go well below 12 mA, however PAR stops and refuses to go on
despite violations.  Is there any work-around?
>

First of all, make sure that all FAST outputs are properly terminated.
With your 5pf load you should expect rise and fall times in the order
of 0.2ns, so proper termination is *required*.

Second, how did you measure the overshoot?  If you are using a typical
scope probe with a 4" ground lead then you are not seeing the real
signal.  You need a low capacitance active probe, with a very short
(<1/2") ground lead.  Also, with 0.2ns edge rates, you need a scope
with at least 5GHz bandwidth to make reasonable measurements.

--
Greg Neff
VP Engineering
*Microsym* Computers Inc.
greg@guesswhichwordgoeshere.com


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Article: 28020
Subject: Re: 3V -> 5V clock signal level conversion
From: "Jason Daughenbaugh" <jad_NOSPAM@aedinc.net>
Date: Tue, 19 Dec 2000 07:51:09 -0800
Links: << >>  << T >>  << A >>
"There are data lines being driven from the 3V output,
we can get away with the 'tristate and pull high
for logic high' trick, but I don't want to do this with
the clock signals. The active (rising) edges are 
_very_ slow and the risk of double clocking etc
would be too high."

Something worth considering would be a modified version of this method.  I have had great success driving a clock line by configuring the logic so that it drives the output pad high until it is a high level and then tristate and let the pullup work the rest.  This allows the output to be driven all of the way up to 3V, creating some much faster slew rates.  

Xilinx clains that this can decrease the rise time from 0.4 to 3.0V from 20ns to 3ns.  I have seen this to be true on a spartan-2.

See:
http://www.xilinx.com/products/virtex/techtopic/5volt.htm
http://www.xilinx.com/products/virtex/techtopic/vtt002.pdf

Jason Daughenbaugh
http://www.aedinc.net

Article: 28021
Subject: Re: 3V -> 5V clock signal level conversion
From: Greg Neff <gregneff@my-deja.com>
Date: Tue, 19 Dec 2000 16:15:55 GMT
Links: << >>  << T >>  << A >>
In article <3A3F3339.AC12CB9E@sqf.hp.com>,
  nials@sqf.hp.com wrote:
> I'm looking at a problem where we need to drive a
> couple of 5V CMOS clock inputs from a SpartanII
> 3v output.
>
(snip)

I like to have a reel of these on hand:

http://www.fairchildsemi.com/pf/NC/NC7ST86.html

They can be used as inverters or buffers, depending on how you strap
the other input.

Other manufacturers (such as Toshiba) make similar parts.


--
Greg Neff
VP Engineering
*Microsym* Computers Inc.
greg@guesswhichwordgoeshere.com


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Article: 28022
Subject: Re: Question about Xilinx pins at high-frequency
From: "Pascal C." <>
Date: Tue, 19 Dec 2000 08:25:35 -0800
Links: << >>  << T >>  << A >>
I don't think any terminations were put on those pins.

The measure was taken with an active probe, at 5 GS/s sampling.

Article: 28023
Subject: Re: Setup violation
From: Peter Alfke <peter.alfke@xilinx.com>
Date: Tue, 19 Dec 2000 09:03:47 -0800
Links: << >>  << T >>  << A >>


"Søren A.Møller" wrote:
, peter.alfke@xilinx.com says...

> <SNIP>
> > As I said, the gain of the slave latch makes that (almost) impossible.
> > But I also question the importance of the question.
> > For data, it is irrelevant whether it oscillates or not.
>
> Not if the signal has different delays to the following FF's (assuming
> synchronous design) and therefore is interpreted as '0' at some FF's and
> '1' at others.
>

I should have said:
Oscillation or unknown delay can lead to exactly the same bad result.
So, oscillation is no worse than an unpredictably long delay.

I think we agree.
Nice list of commandments.
Especially #10!

Peter Alfke


Article: 28024
Subject: Re: 3V -> 5V clock signal level conversion
From: Peter Alfke <peter.alfke@xilinx.com>
Date: Tue, 19 Dec 2000 09:07:42 -0800
Links: << >>  << T >>  << A >>
I am sure that the reborn Fairchild ( I am an old Fairchilder of 30
years ago!) has circuits with an input threshold of 2.4 V and
available in really tiny packages.

Peter Alfke

Nial Stewart wrote:

> Tomppa wrote:
>
> > You could use HCT- logic since it's inputs high-state
> > is about 2.4V. I read this at some manufactures datasheets
> > so that should be ok. At least Philips (and maybe others)
> > have single logic ports in one tiny package (picogate).
>
> Vinhigh for these two signals is 3.5V, and we're getting
> a 'glitch' at ~2.4V that would cause double clocking if that
> was the threshold.
>
> I also don't think you can get any 74XX series devices in an
> 8 pin package.
>
> Nial.




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