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Messages from 28250

Article: 28250
Subject: NIOS Processor soft core
From: eriks@avidyne.com
Date: Wed, 03 Jan 2001 21:56:54 GMT
Links: << >>  << T >>  << A >>
I'm thinking about using the NIOS processor from Altera in a new design
and I am curious if anyone has had any good or bad experiences with it?


Sent via Deja.com
http://www.deja.com/

Article: 28251
Subject: Re: Boston/Senior Software engineer FPGA/ Well Funded Start up/100k+++/Hot Data Storage Market
From: msimon@xta.com (M. Simon)
Date: Wed, 03 Jan 2001 21:59:17 GMT
Links: << >>  << T >>  << A >>
On 03 Jan 2001 16:17:19 +0000, Jon Schneider
<jms@geriatrix.circlesquared.cXoXm> wrote:

>OSFT Inc. <info@osft.com> wrote:
>> Skematic Capture
>
>I did my first (1.2u) ASIC years ago with schematic capture when that
>was the way to do it. Is this similar ?
>
>> Birth Trouble shooting
>
>Now I _know_ I'm completely out of touch with semiconductor technology.
>
>        Jon

I believe the current (or former) term is HW/SW integration.



M. Simon  Space-Time Productions http://www.spacetimepro.com
              Free CNC Machine Control Software
              Free Source Code
              Control the World From a Parallel Port

Article: 28252
Subject: Re: Fixing pins on Spartan II
From: Ray Andraka <ray@andraka.com>
Date: Wed, 03 Jan 2001 22:55:03 GMT
Links: << >>  << T >>  << A >>
You can assign your pins before the design is done, but you should apply at
least a little thought to make success more likely.  Some points to ponder: 

Try to register all the I/O in the design at the IOB.  That isolates the
internal timing from the external timing, and makes it more likely to get a
design to work.

The routing in the the Spartan II is more plentiful than the older 4K/spartan
family, so a poor pin placement is not nearly as likely to give you a no-route
than it had been previously.  

Some simple things can reduce the routing congestion greatly and accelerate the
place and route times.  FIrst, if it is a data flow design that will be using
the carry chains, run your data across the chip (as viewed in the floorplanner)
with the LSBs at the bottom to line up with the carry chain direction.  If you
have signals that go in and then back out iwth no or only one registers, then
those should be placed nearby to keep the routing delays minimum.

Mikhail Matusov wrote:
> 
> Hi all,
> 
> Egg-chicken kind of problem. I have to give my board design out to a layout
> person but I haven't yet had chance to start my FPGA work. Usually I do some
> draft FPGA design and run tools at least once to fix the pins before giving
> it out to do a layout but this time the schedule is really tight and if I go
> this route it will be too late. This is not a very demanding design neither
> in terms of complexity nor in terms of speed and I am using Spartan II
> family device. Scary part is that the pins utilization is almost 100%.
> 
> Nonetheless, do you guys think that I can get away with pins fixed
> beforehand without too much thought (I put my clocks on global clock lines)?
> 
> Thanks in advance,
> 
> --
> ============================
> Mikhail Matusov
> Hardware Design Engineer
> Square Peg Communications
> Tel.: 1 (613) 271-0044 ext.231
> Fax: 1 (613) 271-3007
> http://www.squarepeg.ca

-- 
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com  or http://www.fpga-guru.com

Article: 28253
Subject: Serial interface (urgent)
From: "yaohan" <yaohan@tm.net.my>
Date: Thu, 4 Jan 2001 08:46:04 +0800
Links: << >>  << T >>  << A >>
Hi,
I need to send and receive my data through serial interface for my FPGA
project.


I plan to use a NS16450 (UART) to do so. However I am not sure how to
control
and utilize it. Any reference / example / or suggestion?

regards,
chew



Article: 28254
Subject: Re: Fixing pins on Spartan II
From: John Larkin <jjlarkin@highlandSNIPTHIStechnology.com>
Date: Wed, 03 Jan 2001 17:47:58 -0800
Links: << >>  << T >>  << A >>
On Wed, 03 Jan 2001 20:17:53 GMT, "Mikhail Matusov"
<matusov@ANNTIsquarepegSPPAMM.ca> wrote:

>Hi all,
>
>Egg-chicken kind of problem. I have to give my board design out to a layout
>person but I haven't yet had chance to start my FPGA work. Usually I do some
>draft FPGA design and run tools at least once to fix the pins before giving
>it out to do a layout but this time the schedule is really tight and if I go
>this route it will be too late. This is not a very demanding design neither
>in terms of complexity nor in terms of speed and I am using Spartan II
>family device. Scary part is that the pins utilization is almost 100%.
>
>Nonetheless, do you guys think that I can get away with pins fixed
>beforehand without too much thought (I put my clocks on global clock lines)?
>
>
>Thanks in advance,

Mikhail,

we always preassign pins so that we can do the PCB layout and the FPGA
design concurrently. We try to pick a signal flow pattern that makes
the PCB layout easy and seems to make FPGA routing happy, or at least
make a rough guess at it. Seems to work.

John





Article: 28255
Subject: FPGA starter kit recommendations
From: "valeri" <vassenov@dsl.ca>
Date: Thu, 04 Jan 2001 06:55:39 GMT
Links: << >>  << T >>  << A >>
Hi,
I want to start with FPGA design.
I will appreciate any suggestions for good starter kit.

Val




Article: 28256
Subject: Re: FPGA starter kit recommendations
From: "Wolfgang Loewer" <wolfgang.loewer@elca.de>
Date: Thu, 4 Jan 2001 10:17:06 +0100
Links: << >>  << T >>  << A >>
Val,

check out the DIGILAB picoMAX, 10K10 and 1Kx208 from El Camino
(http://www.elca.de/prode.html ). All you need, to get started with one of
these kits, is a PC. The included tools support Altera Hardware Description
Language (AHDL) synthesis, schematic design entry, full featured timing
analysis and simulation, floorplanning and more. You can also download free
LeonardoSpectrum and Synopsys FPGA Express versions from the Altera web
(http://www.altera.com/html/tools/download_2.html), that can be used
together with these kits for VHDL and Verilog synthesis.

Regards
Wolfgang

valeri <vassenov@dsl.ca> wrote in message
news:978591339.623677@sai.velocet.net...
> Hi,
> I want to start with FPGA design.
> I will appreciate any suggestions for good starter kit.
>
> Val
>
>
>



Article: 28257
Subject: Re: NIOS Processor soft core
From: "Wolfgang Loewer" <wolfgang.loewer@elca.de>
Date: Thu, 4 Jan 2001 11:21:07 +0100
Links: << >>  << T >>  << A >>
We've implemented NIOS on three of our prototyping platforms with a fourth
to come and had only good experiences so far. For some of these systems we
use NIOS with software to do board tests and for others its used for on-chip
test pattern generation and checking when doing ASIC prototyping. It worked
very well with APEX 20K/Quartus and we just had a little hassle using
MAX+plus II for FLEX 10KE and ACEX 1K which are not officially supported
yet. The problem with MAX+plus II is that it doesn't support node names
longer than 32 characters. With Synopsys DC you can automatically limit the
length of node names in the EDIF netlist passed to MAX+plus II. For other
synthesis tools we've written a little utility that shortens the names in an
EDIF netlist. The problem will go away, once ACEX 1K and FLEX 10KE are
supported in Quartus II.
We're supporting a customer here in Germany that decided to completely
switch to NIOS for future designs and they use a lot embedded processors.
The best thing about NIOS is that once you generate a system, including a
core and it's peripherals you get VHDL or Verilog source code. You can
easily re-target this code. Never again you'll have to worry about
discontinued processors or peripherals and the associated hassle with last
time buys, major re-designs or re-writing software.

Regards
Wolfgang

El Camino
http://www.elca.de


<eriks@avidyne.com> wrote in message news:930771$rds$1@nnrp1.deja.com...
> I'm thinking about using the NIOS processor from Altera in a new design
> and I am curious if anyone has had any good or bad experiences with it?
>
>
> Sent via Deja.com
> http://www.deja.com/



Article: 28258
Subject: Re: Serial interface (urgent)
From: "Jaan Sirp" <jaan.sirp@mail.ee>
Date: Thu, 4 Jan 2001 02:28:25 -0800
Links: << >>  << T >>  << A >>
NS16450 - a big archaic chip without fifo and without input/output drivers. A UART inside FPGA (or CPLD) plus MAX232 derivate could be better variant.

Article: 28259
Subject: XILINX SRL16E - FIFO
From: hirsch_yoav@hotmail.com
Date: Thu, 04 Jan 2001 12:12:38 GMT
Links: << >>  << T >>  << A >>
I'm using the example listed at XILINX web site for implementing XILINX
SRL16E as  a FIFO. But in order to use the SRL 16E as a FIFO, I've added
Write_Enable and ADDRESS_rd signals.

The problem that I'm having is that once the signal addr_rd is added to the
design, the LEONARDO EXEMPLAR (Version: v20001b.106) does not "recognize"
that I'm referring to SRL16E.

Please look at the VHD file listed below, and you can notice at the end of
the architecture that I have 2 line codes for the DOUT signal where one line
is remarked If I switch between those 2 line codes, everything is OK, but
It's not what I want to do.

In other words:
If I use the line: dout <= zigmond(cycle-1);
LEONARDO recognises SEL16E

But if I use: dout <= zigmond(conv_integer(addr_rd));
LEONARDO makes it all using FLIP-FLOPS, which I do not want.

Can you assist?


----------------------------------------------------
----------------------------------------------------
--
--  Library Name :  srl_fifo
--  Unit    Name :  srl16e
--  Unit    Type :  Text Unit
--
------------------------------------------------------
------------------------------------------
------------------------------------------
-- Date        : Wed Jan 03 17:34:14 2001
--
-- Author      : Yoav Hirsch
--
-- Company     : ECI - ACCESS SOLUTIONS - ASIC group
--
-- Description : XILINX SRL 16E basic element for FIFO
--               Synthisizable by Exemplar
------------------------------------------
------------------------------------------
Library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity  srl16e  is
Generic (cycle : integer := 16;
		width : integer := 16);
port (
		din		: IN std_logic_vector(width-1 downto 0);
		addr_rd	: IN std_logic_vector(3 downto 0);
		clk_w	: IN std_logic;
		we		: IN std_logic;
		dout		: OUT std_logic_vector(width-1 downto 0)
	);
attribute	clock_node	: boolean;
attribute	clock_node of clk_w	: signal is TRUE;
end;
------------------------------------------
------------------------------------------
architecture  srl16e_arch  of  srl16e  is
type freud is array(0 to cycle -1) of
	std_logic_vector(width-1 downto 0);
signal zigmond	: freud;
begin
   process(clk_w)
	begin
		IF clk_w'event AND clk_w = '1' THEN
			if we = '1' THEN
				zigmond <= din & zigmond(0 to cycle - 2);
			END IF;
		END IF;
	end process;
-- dout <= zigmond(cycle-1);
dout <= zigmond(conv_integer(addr_rd));
end;





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Article: 28260
Subject: Re: Jedec to tms/tdi wiggles
From: "Leopold Faschalek" <fale@skidata.com>
Date: Thu, 4 Jan 2001 13:13:19 +0100
Links: << >>  << T >>  << A >>
>Neil Glenn Jacobson <neil.jacobson@xilinx.com> schrieb in im Newsbeitrag:
3A539955.58A802CE@xilinx.com...
>Please check this app. note for a Xilinx-supplied solution:
> Xilinx XAPP Note Summaries
>The accompanying software is available from here:
>  eisp_pc.zip

I tried the software from the eisp_pc.zip (xapp058) and my system crashes
after/while the ISPEN command.
Has anybody succesfully used this software for ISP purposes ?

I found that the xsvf-download software (from the micro.c file) always goes
to the
Run-Test/Idle State after a XSIR command.

But the EZTAG programmer does not go to the Run-Test/Idle state but
continues with
the Select-DR-Scan state to shift in the 6bit value 0x0f before it goes to
Reset_test/Idle
state.

Maybe someone has a modified/corrected micro.c sourcecode ?

TIA

Leopold Faschalek
SkiData AG
http://www.skidata.com
mailto:fale@skidata.com





Article: 28261
Subject: Re: Question about Xilinx pins at high-frequency
From: hirsch_yoav@hotmail.com
Date: Thu, 04 Jan 2001 12:55:46 GMT
Links: << >>  << T >>  << A >>
Hi Pascal,
See whether the following article of XILINX would be of any help to you:
http://www.xilinx.com/support/techxclusives/signals-techX5.htm

Yoav Hirsch.


Sent via Deja.com
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Article: 28262
Subject: Re: FPGA starter kit recommendations
From: Dave Vanden Bout <devb@xess.com>
Date: Thu, 04 Jan 2001 08:08:09 -0500
Links: << >>  << T >>  << A >>
> Hi,
> I want to start with FPGA design.
> I will appreciate any suggestions for good starter kit.
>
> Val

I would suggest you go to http://www.deja.com and do a search for the
term "FPGA starter kit" within the comp.arch.fpga news archive.  I got
40 hits on this subject within the past year.  You should be able to
find references to all the popular introductory kits in this way.

--
|| Dr. Dave Van den Bout   XESS Corp.               (919) 387-0076 ||
|| devb@xess.com           2608 Sweetgum Dr.        (800) 549-9377 ||
|| http://www.xess.com     Apex, NC 27502 USA   FAX:(919) 387-1302 ||



Article: 28263
Subject: Spartan-II DLL Usage
From: felix_bertram@my-deja.com
Date: Thu, 04 Jan 2001 15:44:30 GMT
Links: << >>  << T >>  << A >>
Hello everybody,

I am working on an FPGA with the surrounded hardware being given, so
that I have to find a solution, even if it is not optimal.

I want to quadruple a clock of 24MHz, so that I finally have a clock
with 96MHz frequency. I used two DLLs to do so and- it seems to work
fine. However, the datasheet gives 25MHz as the lowest DLL input
frequency, so that I am definitly out of spec.

There seem to be two solutions:
1) There is some safety margin, so that I can feed 24MHz into the DLL.
As the DLL's resolution is limited to 60ps I assume that it is built
from 60ps-delay items- which will have some temperature or voltage
dependency. Is there some detailed information on the behavior of the
DLLs???

2) I first double the clock by using combinational logic, basically a
small delay followed by an XOR. This results in a 48MHz clock with a
very small duty cycle which is fed into a single DLL. This DLL will
correct my duty cycle to 50% and at the same time doubles my clock to
96MHz. If this works, has anybody done so? I am working with VHDL, how
do I prevent the tools from "optimizing" my combinational path?

Any comments very much appreciated,
best regards

Felix Bertram


Sent via Deja.com
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Article: 28264
Subject: FPGA Compiler2 question
From: Lee Weston <lee.weston@philips.com>
Date: Thu, 04 Jan 2001 16:07:41 +0000
Links: << >>  << T >>  << A >>
Hello,

I'm trying to generate a FPGA compiler2 script. What I want to do is
create user defined VHDL libraries. From the help menu the command to do
this is:

create_library -name my_library

This gives the following error:

Error: extra positional option 'my_library' (CMD-012)

Does anyone know what I'm doing wrong?


Lee
-- 
Lee Weston, Philips Semiconductors, CS-DM Southampton, SO15 0DJ, UK
mailto:lee.weston@philips.com                  seri:weston@ukpsshp1
phone: +44 (0) 23 80316471                  fax +44 (0) 23 80316303

Article: 28265
Subject: Re: XILINX SRL16E - FIFO
From: Ray Andraka <ray@andraka.com>
Date: Thu, 04 Jan 2001 16:41:10 GMT
Links: << >>  << T >>  << A >>
In the one that works, the delay tap is constant, while in the second it is
dynamic.  The synthesizers until very recently won't infer an SRL16 with a
dynamically changed delay.  I think the latest release of Synplicity is supposed
to infer the dynamic SRL16, although I have not tried it.  For this case,
instantiate yoru SRL16's and it should work for you.

hirsch_yoav@hotmail.com wrote:
> 
> I'm using the example listed at XILINX web site for implementing XILINX
> SRL16E as  a FIFO. But in order to use the SRL 16E as a FIFO, I've added
> Write_Enable and ADDRESS_rd signals.
> 
> The problem that I'm having is that once the signal addr_rd is added to the
> design, the LEONARDO EXEMPLAR (Version: v20001b.106) does not "recognize"
> that I'm referring to SRL16E.
> 
> Please look at the VHD file listed below, and you can notice at the end of
> the architecture that I have 2 line codes for the DOUT signal where one line
> is remarked If I switch between those 2 line codes, everything is OK, but
> It's not what I want to do.
> 
> In other words:
> If I use the line: dout <= zigmond(cycle-1);
> LEONARDO recognises SEL16E
> 
> But if I use: dout <= zigmond(conv_integer(addr_rd));
> LEONARDO makes it all using FLIP-FLOPS, which I do not want.
> 
> Can you assist?
> 
> ----------------------------------------------------
> ----------------------------------------------------
> --
> --  Library Name :  srl_fifo
> --  Unit    Name :  srl16e
> --  Unit    Type :  Text Unit
> --
> ------------------------------------------------------
> ------------------------------------------
> ------------------------------------------
> -- Date        : Wed Jan 03 17:34:14 2001
> --
> -- Author      : Yoav Hirsch
> --
> -- Company     : ECI - ACCESS SOLUTIONS - ASIC group
> --
> -- Description : XILINX SRL 16E basic element for FIFO
> --               Synthisizable by Exemplar
> ------------------------------------------
> ------------------------------------------
> Library IEEE;
> use ieee.std_logic_1164.all;
> use ieee.std_logic_arith.all;
> use ieee.std_logic_unsigned.all;
> 
> entity  srl16e  is
> Generic (cycle : integer := 16;
>                 width : integer := 16);
> port (
>                 din             : IN std_logic_vector(width-1 downto 0);
>                 addr_rd : IN std_logic_vector(3 downto 0);
>                 clk_w   : IN std_logic;
>                 we              : IN std_logic;
>                 dout            : OUT std_logic_vector(width-1 downto 0)
>         );
> attribute       clock_node      : boolean;
> attribute       clock_node of clk_w     : signal is TRUE;
> end;
> ------------------------------------------
> ------------------------------------------
> architecture  srl16e_arch  of  srl16e  is
> type freud is array(0 to cycle -1) of
>         std_logic_vector(width-1 downto 0);
> signal zigmond  : freud;
> begin
>    process(clk_w)
>         begin
>                 IF clk_w'event AND clk_w = '1' THEN
>                         if we = '1' THEN
>                                 zigmond <= din & zigmond(0 to cycle - 2);
>                         END IF;
>                 END IF;
>         end process;
> -- dout <= zigmond(cycle-1);
> dout <= zigmond(conv_integer(addr_rd));
> end;
> 
> Sent via Deja.com
> http://www.deja.com/

-- 
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com  or http://www.fpga-guru.com

Article: 28266
Subject: Re: Spartan-II DLL Usage
From: Austin Lesea <austin.lesea@xilinx.com>
Date: Thu, 04 Jan 2001 08:43:56 -0800
Links: << >>  << T >>  << A >>
Felix,

The low frequency limit of the DLL is process, voltage and temperature
dependent (as you might guess!).

The delay lines run off their own regulated supply, so the voltage
variations are extremely small (don't worry about them).

The temperature variation is important, because if it locks at hot, and
then it gets cold, it could run out of taps at a low frequency (line not
long enough as it gets faster as it got colder).

There is definitely a safety margin, and it is at least 10%.  But we may
choose to ship product that is much much faster (everyone loves faster),
and reduce this margin in the future.

Now,  I am assuming you are not going below 0C, so there will be some
margin there.  But if not, then definitely don't do it.

In process, the delay lines use techniques to make them less sensitive to
transistor speed, but a fast lot will still have slightly faster delay
lines, which will not work reliably at lower frequencies.

All of that said, I would not recommend its use out of specification.  You
would probably get away with it until that one lot came along that was
just a little too fast when your board got just a little too
cold.....(been there, done that:  not good for your career!).

Doubling with a delay and an XOR is a common technique, and if you can
take the delay element and place it off chip, you will not have to worry
about it getting too fast due to the process/voltage/temperature
variations in the FPGA.  I used to use a small RC off chip that added to
the delay and made this reliable (used in 100K+ units of a fiber optic
transmission system).  I lived through three process changes of Xilinx
fpga's with this method, even though it is an asynchronous "no-no".

The DLL only cares about the rising edge of the input, and is incredibly
tolerant to input jitter, so it can easily use the XOR doubled input
signal.

The resulting 4X output,  however achieved, will have more jitter.  I
would expect less than 200ps peak to peak period jitter, worst case, when
everything is up and running (all ff's clocking, IOB's toggling, etc).  A
single DLL (not doubling) in the same scenario would have less than 100
ps.  Jitter is not strictly additive, and the DLL does no filtering of any
input jitter.

Austin

felix_bertram@my-deja.com wrote:

> Hello everybody,
>
> I am working on an FPGA with the surrounded hardware being given, so
> that I have to find a solution, even if it is not optimal.
>
> I want to quadruple a clock of 24MHz, so that I finally have a clock
> with 96MHz frequency. I used two DLLs to do so and- it seems to work
> fine. However, the datasheet gives 25MHz as the lowest DLL input
> frequency, so that I am definitly out of spec.
>
> There seem to be two solutions:
> 1) There is some safety margin, so that I can feed 24MHz into the DLL.
> As the DLL's resolution is limited to 60ps I assume that it is built
> from 60ps-delay items- which will have some temperature or voltage
> dependency. Is there some detailed information on the behavior of the
> DLLs???
>
> 2) I first double the clock by using combinational logic, basically a
> small delay followed by an XOR. This results in a 48MHz clock with a
> very small duty cycle which is fed into a single DLL. This DLL will
> correct my duty cycle to 50% and at the same time doubles my clock to
> 96MHz. If this works, has anybody done so? I am working with VHDL, how
> do I prevent the tools from "optimizing" my combinational path?
>
> Any comments very much appreciated,
> best regards
>
> Felix Bertram
>
> Sent via Deja.com
> http://www.deja.com/


Article: 28267
Subject: CFP: DATE2001 University Booth
From: DATE 2001 University Booth <DATE2001@informatik.uni-tuebingen.de>
Date: 04 Jan 2001 18:22:43 +0100
Links: << >>  << T >>  << A >>
**************************************************************************
DATE'2001    DATE'2001    DATE'2001    DATE'2001    DATE'2001    DATE'2001
**************************************************************************


     ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
     +                                                                +
     +          CALL FOR DEMOS AT THE UNIVERSITY BOOTH                +
     +          --------------------------------------                +
     +                                                                +
     +           DESIGN AUTOMATION AND TEST IN EUROPE                 +
     +                         DATE 2001                              +
     +                                                                +
     +                     Munich,  Germany                           +
     +                     13-16 March 2001                           +
     +                                                                +
     + http://www.date-conference.com/conference/university-booth.htm +
     +                                                                +
     ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++


Sponsored by the European Design and Automation Association, 
the EDA Consortium, the IEEE Computer Society - TTTC, ECSI and RAS. 
In cooperation with ACM SIGDA.

A university booth will be organized for CAD software and hardware
demonstrations during DATE'2001 in Munich, Germany. The conference
and the exhibition including the university booth will be held in the 
superb new facilities of the International Congress Center (ICM), 
(Info: http://www.icm-muenchen.de)

All demonstrations will take place on Tuesday 13th until Friday 16th 
March 2001. The demonstrations have to be accompanied by a one-page 
abstract which will be published and distributed to all conference 
participants.

--------------------------------------------------------------------------

CAD Software Demonstrations: 

Several machines (SPARC Ultra running Solaris 7) will be provided.
The demonstration software has to be installed on the SPARC Ultra  
machines BEFORE the exhibition itself takes place:
  Demonstrators will be given a machine name and an user-id 
  valid from February 19th, 2001, to March 2nd, 2001, 
  for an installation via Internet. 

Each CAD demonstration should be supported by a poster (not larger
than 0.9m width by 1.4m height).

CAD demonstrations on other computer architectures are possible on the 
condition that demonstrators provide their own equipment and set up the 
demonstration well before the assigned presentation time slot. 

--------------------------------------------------------------------------

Working Silicon Hardware Demonstrations:

All circuits must be demonstrated within a working environment. Stand
alone circuits will not be exhibited. Each exhibitor is responsible
for bringing and installing the hardware and software resources necessary 
for showing the entire functionality of the circuit.

Each hardware demonstration should be supported by a poster (not
larger than 0.9m width by 1.4m height). Each poster should contain
a plot of the circuit, complemented by any information on the
functionality of the circuit, test results and working environment.

--------------------------------------------------------------------------

Deadline and addresses:

The deadline for submission of a CAD software or a working silicon
demonstration is January 31st, 2001.

The appropriate application form (CAD software or working silicon)
should be sent together with a one page description (in PostScript or
PDF) via email to

            DATE2001@informatik.uni-tuebingen.de

For any further information or requests feel free to contact 

Juergen Ruf or Carsten Schulz-Key

            DATE2001@informatik.uni-tuebingen.de

**************************************************************************
DATE'2001    DATE'2001    DATE'2001    DATE'2001    DATE'2001    DATE'2001
**************************************************************************



--------------------------------------------------------------------------
REGISTRATION FORM FOR CAD SOFTWARE DEMOS AT THE UNIVERSITY BOOTH
--------------------------------------------------------------------------

1/ University or Institution:

2/ Contact person    Name:

                     Address:

                     Phone:

                     Fax:

                     E-mail:

3/ Software demonstrated (name):

4/ Abstract of the functionality of the software (please attach a one
   page description as a separate PostScript or PDF file)

5/ Machine specifications:

SPARC:                                            [ ] Yes      [ ] No

other computer  (hardware and operating system requirements): 


In this case, can you bring your own machine?     [ ] Yes      [ ] No

6/ Configuration requirements: 

Hard Disk:.......  Internal Memory:........   Swap Space:........... 

7/ Number of one hour slots wanted for demonstrations: 




--------------------------------------------------------------------------
   REGISTRATION FORM FOR WORKING SILICON DEMOS AT THE UNIVERSITY BOOTH
--------------------------------------------------------------------------

1/ University or Institution:

2/ Contact Person    Name: 

                     Address: 

                     Phone: 

                     Fax: 

                     E-mail: 

3/ Circuit demonstrated (Name): 

4/ Abstract of the functionality of the circuit, test results, working
   environment (please attach a one page description as a separate
   PostScript or PDF file)

5/ Necessary hardware and software resources (provided by the demonstrator):





 
6/ Number of one hour slots wanted for demos: 


**************************************************************************
DATE'2001    DATE'2001    DATE'2001    DATE'2001    DATE'2001    DATE'2001
**************************************************************************

Article: 28268
Subject: how do you design with + compile separate entity +architecture files
From: "jon" <jon@frg.freeserve.com>
Date: Thu, 4 Jan 2001 18:26:06 -0000
Links: << >>  << T >>  << A >>
Hi,

I  have a hierarchical design, with the entities stored in individual files
and all the architectures stored in 1 file, some of the archs use synopsys
Design Ware components, in the past I have always designed with the entity
and architecture for each module the same file, is there any advantage in
doing it this way?
Where do I put the the Library and Use statements for the libraries, in the
entity, architecture or somewhere else? and how do I go about compiling
these files in Synopsys DC and ModelSim?

Thanks jon



Article: 28269
Subject: Re: how do you design with + compile separate entity +architecture files
From: Brian Philofsky <brian.philofsky@xilinx.com>
Date: Thu, 04 Jan 2001 12:09:08 -0700
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.
--------------E70F5D543D1AEA87E45EC4CD
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit


Hey jon,

jon wrote:

> Hi,
>
> I  have a hierarchical design, with the entities stored in individual files
> and all the architectures stored in 1 file, some of the archs use synopsys
> Design Ware components, in the past I have always designed with the entity
> and architecture for each module the same file, is there any advantage in
> doing it this way?

The main advantage I see for this methodlogy is the fact you can have multiple
architectures (if you desire) for each entity.
A side advantage, if you are targeting Xilinx, could be that you would be able
to specify generics (for bus widths for instance) within the entity, then
generate an architecture only structural netlist from the place and route
tools.  You can then re-use the RTL entity with the structural architecture and
most likely not have to do any modification to your testbench for back-end
simulation.  You can still do this with both in the same file but this is a bit
cleaner this way.

The disadvantage is now you have more files to deal with and an associated
compilation order to deal with.


> Where do I put the the Library and Use statements for the libraries, in the
> entity, architecture or somewhere else?

Both.  You need library statements in the entity to specify port typing (i.e.
std_logic requires the ieee libraries).  You need libraries specifications in
the architecture file as well for signal typing as well as any other simulation
libraries such as in your case, the DW simulation library models.  I usually
just mimic the library and use specification for both files for clarity.


> and how do I go about compiling
> these files in Synopsys DC and ModelSim?

There will be an associated compilation order now.  You need to compile the
entity before the architecture for both DC and ModelSim.  If you are to use
multiple architectures, it is generally a good idea to write a configuration
(possibly in yet another seperate file) to at minimum bind the right
architecture to the right entity.  This way you know what you get when you
simulate or synthesize.  Otherwise, the general rule is the last architecture
that was compiled is the one that is bound.


--  Brian



>
>
> Thanks jon

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begin:vcard 
n:Philofsky;Brian
tel;work:1-800-255-7778
x-mozilla-html:TRUE
url:http://www.xilinx.com
org:Xilinx, Inc.;Software Marketing
adr:;;2300 55th Street;Boulder;CO;80301;USA
version:2.1
email;internet:brianp@xilinx.com
title:Sr. Technical Marketing Engineer
fn:Brian Philofsky
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--------------E70F5D543D1AEA87E45EC4CD--


Article: 28270
Subject: Nondeterministic FSMs in hardware?
From: sidhu@halcyon.usc.edu (Reetinder P. S. Sidhu)
Date: 4 Jan 2001 13:59:30 -0800
Links: << >>  << T >>  << A >>

Hi all

I'm a PhD student whose current research focuses on nondeterministic
FSMs. It seems to me that there are interesting ways of implementing
them efficiently in hardware. I was wondering if nondeterministic FSMs
have previously been implemented in VLSI/programmable logic and if so,
for what applications.

I would be grateful for any info/pointers regarding above. Thanks in
advance.

						     Regards

Article: 28271
Subject: Re: Nondeterministic FSMs in hardware?
From: Peter Alfke <peter.alfke@xilinx.com>
Date: Thu, 04 Jan 2001 14:21:31 -0800
Links: << >>  << T >>  << A >>
Hi,
tell us more about non-deterministic finite state machines.
What makes them non-deterministic?
Do they roll dice? ;-)
What's good about them?

Peter Alfke, Xilinx
==============================
"Reetinder P. S. Sidhu" wrote:

> Hi all
>
> I'm a PhD student whose current research focuses on nondeterministic
> FSMs. It seems to me that there are interesting ways of implementing
> them efficiently in hardware. I was wondering if nondeterministic FSMs
> have previously been implemented in VLSI/programmable logic and if so,
> for what applications.
>
> I would be grateful for any info/pointers regarding above. Thanks in
> advance.
>
>                                                      Regards


Article: 28272
Subject: Re: Nondeterministic FSMs in hardware?
From: "Eric C. Fromm" <efromm@sgi.com>
Date: Thu, 04 Jan 2001 16:38:11 -0600
Links: << >>  << T >>  << A >>
"Reetinder P. S. Sidhu" wrote:
> 
> Hi all
> 
> I'm a PhD student whose current research focuses on nondeterministic
> FSMs. It seems to me that there are interesting ways of implementing
> them efficiently in hardware. I was wondering if nondeterministic FSMs
> have previously been implemented in VLSI/programmable logic and if so,
> for what applications.
> 
> I would be grateful for any info/pointers regarding above. Thanks in
> advance.
> 
>                                                      Regards

and I would be grateful if someone would simply explain what these things
are...

i.e., in what sense deterministic?

thanks,

-eric

-- 
Eric C. Fromm                           efromm@sgi.com
Principal Engineer                      Scalable Systems Division
SGI - Silicon Graphics, Inc.            Chippewa Falls, Wi.

Article: 28273
Subject: Re: Nondeterministic FSMs in hardware?
From: george@snork.capybara.org (George Coulouris)
Date: 4 Jan 2001 23:47:10 GMT
Links: << >>  << T >>  << A >>
In article <3A54FB53.832ACB93@sgi.com>, Eric C. Fromm wrote:
>"Reetinder P. S. Sidhu" wrote:
>> 
>> Hi all
>> 
>> I'm a PhD student whose current research focuses on nondeterministic
>> FSMs. It seems to me that there are interesting ways of implementing
>> them efficiently in hardware. I was wondering if nondeterministic FSMs
>> have previously been implemented in VLSI/programmable logic and if so,
>> for what applications.
>> 
>> I would be grateful for any info/pointers regarding above. Thanks in
>> advance.
>> 
>>                                                      Regards
>
>and I would be grateful if someone would simply explain what these things
>are...
>
>i.e., in what sense deterministic?
>
>thanks,
>
>-eric
>
>-- 
>Eric C. Fromm                           efromm@sgi.com
>Principal Engineer                      Scalable Systems Division
>SGI - Silicon Graphics, Inc.            Chippewa Falls, Wi.

Given a state and an input symbol, a deterministic finite automaton (DFA)
can "go to" only one next state. A nondeterministic finite state automaton
(NFA), however, may have multiple candidates for the next state.

DFAs and NFAs have equivalent expressive power, namely, that of the regular
expressions.

-- 
George Coulouris - http://www.tc.cornell.edu/~glc5/

Article: 28274
Subject: Re: Nondeterministic FSMs in hardware?
From: "Eric C. Fromm" <efromm@sgi.com>
Date: Thu, 04 Jan 2001 17:59:43 -0600
Links: << >>  << T >>  << A >>
George Coulouris wrote:

> 
> Given a state and an input symbol, a deterministic finite automaton (DFA)
> can "go to" only one next state. A nondeterministic finite state automaton
> (NFA), however, may have multiple candidates for the next state.
> 
> DFAs and NFAs have equivalent expressive power, namely, that of the regular
> expressions.
> 
> --
> George Coulouris - http://www.tc.cornell.edu/~glc5/

OK, I get the 'multiple candidates for next state' bit. You lost me with
the 'expressive power' assertion though. What is this characteristic and
how do DFAs and NFAs compare to other constructs (and what are those
constructs)?

thanks,

-eric

-- 
Eric C. Fromm                           efromm@sgi.com
Principal Engineer                      Scalable Systems Division
SGI - Silicon Graphics, Inc.            Chippewa Falls, Wi.



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