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Messages from 28525

Article: 28525
Subject: Re: Xilinx UCF/ngdbuild problem
From: Nicolas Matringe <nicolas.matringe@IPricot.com>
Date: Tue, 16 Jan 2001 16:02:47 +0100
Links: << >>  << T >>  << A >>
Utku Ozcan wrote:

> Are the lines separated by newline characters? Maybe
> Ngdbuild UCF parser might not handle newline characters.
> Can it be the case?

There is only one line with all the FFs names. I even tried to replace
the separating spaces with dots
(FFS(copier_cout(41):copier_cout(42):...) but it gave the same error.

I'm puzzled that a Xilinx tool generates things that are not recognized
by other Xilinx tools...

-- 
Nicolas MATRINGE           IPricot European Headquarters
Conception electronique    10-12 Avenue de Verdun
Tel +33 1 46 52 53 11      F-92250 LA GARENNE-COLOMBES - FRANCE
Fax +33 1 46 52 53 01      http://www.IPricot.com/

Article: 28526
Subject: How to implement a 5-variable function in a CLB?
From: "Kwong Chan" <kwong_chan@hongkong.com>
Date: Tue, 16 Jan 2001 23:54:29 +0800
Links: << >>  << T >>  << A >>
Hi all,

The Xilinx documentation says that a CLB
can implement any 5-variable function. However, this is not
the case when I compile the design implementing a 5-variable
function. Usually two or more CLBs are required.

Please help how to fix this problem.



Kwong,



Article: 28527
Subject: Re: Xilinx UCF/ngdbuild problem
From: Utku Ozcan <ozcan@netas.com.tr>
Date: Tue, 16 Jan 2001 17:56:12 +0200
Links: << >>  << T >>  << A >>
Nicolas Matringe wrote:

> Utku Ozcan wrote:
>
> > Are the lines separated by newline characters? Maybe
> > Ngdbuild UCF parser might not handle newline characters.
> > Can it be the case?
>
> There is only one line with all the FFs names. I even tried to replace
> the separating spaces with dots
> (FFS(copier_cout(41):copier_cout(42):...) but it gave the same error.
>
> I'm puzzled that a Xilinx tool generates things that are not recognized
> by other Xilinx tools...

Have you tried:

TIMEGRP "your_group"= FFS (net1) FFS (net2) FFS (net3) ... ;

neti, i=1,2,.. might include wildcharts.

That's what I have used to group 30 nets, and I didn't give any error.
Tool was M1.5 with latest patch.

Utku



Article: 28528
Subject: Synplicity newsgroup?
From: Utku Ozcan <ozcan@netas.com.tr>
Date: Tue, 16 Jan 2001 18:02:53 +0200
Links: << >>  << T >>  << A >>

What happened to Synplicity's newsgroup?
The newsgroup browser tells that the server is down...

Utku


Article: 28529
Subject: Re: How to implement a 5-variable function in a CLB?
From: Utku Ozcan <ozcan@netas.com.tr>
Date: Tue, 16 Jan 2001 18:42:13 +0200
Links: << >>  << T >>  << A >>
Kwong Chan wrote:

> Hi all,
>
> The Xilinx documentation says that a CLB
> can implement any 5-variable function. However, this is not
> the case when I compile the design implementing a 5-variable
> function. Usually two or more CLBs are required.
>
> Please help how to fix this problem.
>
> Kwong,

In the worst case, have you not used map with -k option?

Utku


Article: 28530
Subject: Re: Xilinx UCF/ngdbuild problem
From: Nicolas Matringe <nicolas.matringe@IPricot.com>
Date: Tue, 16 Jan 2001 18:18:41 +0100
Links: << >>  << T >>  << A >>
Utku Ozcan wrote:

> Have you tried:
> 
> TIMEGRP "your_group"= FFS (net1) FFS (net2) FFS (net3) ... ;
>
> That's what I have used to group 30 nets, and I didn't give any
> error. Tool was M1.5 with latest patch.

I haven't tried to separate each FF. I made 4 groups but each one gave
an error. I'll try it.

-- 
Nicolas MATRINGE           IPricot European Headquarters
Conception electronique    10-12 Avenue de Verdun
Tel +33 1 46 52 53 11      F-92250 LA GARENNE-COLOMBES - FRANCE
Fax +33 1 46 52 53 01      http://www.IPricot.com/

Article: 28531
Subject: testss
From: "Sven Fleck" <fleck@informatik.uni-tuebingen.de>
Date: Tue, 16 Jan 2001 18:46:26 +0100
Links: << >>  << T >>  << A >>




Article: 28532
Subject: Re: Stereo vision on Virtex
From: "Sven Fleck" <fleck@informatik.uni-tuebingen.de>
Date: Tue, 16 Jan 2001 19:16:49 +0100
Links: << >>  << T >>  << A >>
> The thing is that there would be no reason (except power consumption) to
> implement correlation based approach in an FGPA since you can already
> get real-time in sowtware with recent CPUs or DSPs...
This sounds not possible in my eyes for large resolutions and
complete-image-disparities with more sophisticated filters, as in
http://www.ai.sri.com/~konolige/papers/svm.pdf only relatively small images
have been taken (320x240, 32 disparities). I believe that this problem maps
far better to an FPGA design than to a DSP.




Article: 28533
Subject: Re: Looking for prototyping board
From: "Sven Fleck" <fleck@informatik.uni-tuebingen.de>
Date: Tue, 16 Jan 2001 19:38:04 +0100
Links: << >>  << T >>  << A >>
Hi Juan,

on http://www.x2e.de/ you'll find a wide range of so-called "Spyder-Virtex"
PCI based FPGA boards (including the XCV2000E;-), especially designed for
prototyping.
Just send me an email, if you are interested in further details!

--Sven Fleck
University of Tuebingen
Germany

"Juan Antonio Gómez Pulido" <jangomez@unex.es> wrote in message
news:3A62C11A.57D215C8@unex.es...
> Hi!
>
> I am looking for a prototyping board with a great Virtex FPGA. This
> board should have PCI communication, RAM modules and interfacing
> software.
>
> Thanks a lot,
>
> -- Juan
> University of Extremadura. Spain
>
>



Article: 28534
Subject: Re: revision control tools ??
From: "Berni Joss" <berni_13@yahoo.com>
Date: Tue, 16 Jan 2001 21:33:57 +0100
Links: << >>  << T >>  << A >>
> I have a newbie question to ask you.  What kind of Revision control
> tools do you use when you are working on a design?  Any recommendation
> as to which is better?

I use QVCS from http://www.qumasoft.com/ .
It's almost free at $25. Small, easy to install & use.
Runs under windoze ... you can't always choose.

Berni.




Article: 28535
Subject: Re: Fixing pins on Spartan II
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Tue, 16 Jan 2001 21:19:03 +0000
Links: << >>  << T >>  << A >>


Ray Andraka wrote:

> NO!
>
> There are a few things the automatic placement is exceptionally poor at, with
> pin placement leading the list, followed by tbuf placement, and data-path
> placement.  You should always specify the pin placement rather than letting the
> tools do it.  Even a bad guess is likely to be better than the random placement
> generated by the tools, especially if you start itrating a design.  See earlier
> posts in this thread for some guidelines on assigning pins.
>
> As for number of pins used, 100% is not a problem...most of the designs I touch
> have 100% of the pins defined.  The only time 100% pin utilization becomes a
> problem is when you let the tools do the assigning!
>
> Jakab Tanko wrote:
> >
> > NO, pins are better left to be picked by the place&route tool.
> > At minimum I think you should put together a dummy design,
> > if you don't have time for a detailed one, do a quick place and route
> > and go with that. As for the pins 100% is 20% to many used pins, I
> > would select a larger device or different package to get more I/O pins.
> > This is of course just my opinion and I could be wrong,
> >
> > jakab
> >

Another consideration is that leaving the pin assignment to the P&R tools can lead
to a pinout that makes the PCB autorouter give up & die. Esp the case with the full
square FG devices e.g. FG676.


Article: 28536
Subject: Re: Foundation P&R + location constraint
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Tue, 16 Jan 2001 21:49:17 +0000
Links: << >>  << T >>  << A >>


Michael Boehnel wrote:

> Hi!
>
> When I start a new design with partially coded (not yet fully
> implemented) black boxes and location constraints for a fixed pin
> assignment I often have the problem that the unused pins are optimized
> away by the synthesis tool. This results in an error of the place&root
> tools since the location constraint can't be met.
>
> Is it really necessary that the P&R tool results in an error if a pin in
> the constraint file isn't existent? I think a warning would be enough so
> that I don't have to set extra attributes in the VHDL/Verilog code!?
>
> Whats' the easiest way to prevent that (yet) unused pins are optimized
> away?
>
> Thanks,
>
> Michael

The easiest way is to temporarily change all the pins to outputs & drive
them either to 0 or - better - to the value of one of the already defined
inputs.


Article: 28537
Subject: Oscillator for FPGA - low cost
From: "Mladen Veselic" <veselic@eunet.yu>
Date: Tue, 16 Jan 2001 23:06:30 +0100
Links: << >>  << T >>  << A >>
Hello,

I know this is a little off topic ...

FPGA that I'm using have CMOS threshold on CLK input. Vtrh=3.1v and
Vtrl=1,3v ( 5V supply ).
Standard Quartz oscillator build with TTL gates inside can reach these
thresholds on lower frequencies <10MHz. On higher frequencies amplitude
drops and threshold are not reached or, in some cases, FPGA is randomly
triggered. Also CLK input have very low impendance.
I have build my own quartz oscillator with BF246 transistor but it requires
30V to archive 3Vpp output when  loaded with FPGA.
Can anybody give me an advice how to implement crystal oscillator with:
- output amplitude >2.5 v
- work with crystals from 1MHz  to  ~50 MHz ( fundamental frequency )
- high fanout
- without expensive special components.

Thankful for any design experience.

--
Veselic Mladen
Sigma Laboratorija
ECO Inzenjering



Article: 28538
Subject: Re: Virtex-II officially launched
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Tue, 16 Jan 2001 22:24:47 +0000
Links: << >>  << T >>  << A >>


Peter Alfke wrote:Sorry for the blatant propaganda. Got carried away by
my enthusiasm.

>
> I had been impatiently waiting for the Ides of January, for a long
> time !
>
> Peter Alfke, Xilinx Applications
> =====================================

Peter,

Sorry to sound a dampening note here among all the enthusiasm but a real
world question occurs:

Are Xilinx going to avoid the SpartanII mistake of letting a few major
customers soak up all the Virtex-II production leaving those of us
reliant on the disti's completely out of luck ? [lead time > 20 weeks =>
no design in]

[Anybody remember Ray's joke about the SpartanII T-shirt ?]





Article: 28539
Subject: Re: Xilinx UCF/ngdbuild problem
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Tue, 16 Jan 2001 22:30:44 +0000
Links: << >>  << T >>  << A >>


Nicolas Matringe wrote:

> Utku Ozcan wrote:
>
> > Have you tried:
> >
> > TIMEGRP "your_group"= FFS (net1) FFS (net2) FFS (net3) ... ;
> >
> > That's what I have used to group 30 nets, and I didn't give any
> > error. Tool was M1.5 with latest patch.
>
> I haven't tried to separate each FF. I made 4 groups but each one gave
> an error. I'll try it.
>
> --
> Nicolas MATRINGE           IPricot European Headquarters
> Conception electronique    10-12 Avenue de Verdun
> Tel +33 1 46 52 53 11      F-92250 LA GARENNE-COLOMBES - FRANCE
> Fax +33 1 46 52 53 01      http://www.IPricot.com/

Hi There Nicholas,

One possibility that has happened to me before is that the real error is
in the line *before* the one that NGDBUILD complains about.




Article: 28540
Subject: Re: Spartan programming error
From: Leon Heller <leon_heller@hotmail.com>
Date: Tue, 16 Jan 2001 22:32:37 GMT
Links: << >>  << T >>  << A >>
In article <93v2rr$f97$1@nnrp1.deja.com>,
  bjorn_lindegren@my-deja.com wrote:
> Hi
>
> I use a Spartan device, and some thing is wrong when programming it.
>
> I know that I can check on an out pin for a check sum.
> This check sum tells me when the fpga is right programed.
>
> But whitch pin do I have to check on?

I use an LED on the DONE pin.

Leon
--
Leon Heller, G1HSM
Tel: (Mobile) 079 9098 1221 (Work) +44 1327 357824
Email: leon_heller@hotmail.com
Web: http://www.geocities.com/SiliconValley/Code/1835


Sent via Deja.com
http://www.deja.com/

Article: 28541
Subject: Re: Synplicity newsgroup?
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Tue, 16 Jan 2001 22:33:52 +0000
Links: << >>  << T >>  << A >>


Utku Ozcan wrote:

> What happened to Synplicity's newsgroup?
> The newsgroup browser tells that the server is down...
>
> Utku

I've never been able to get to it either - I contacted Synplicity about
this a long time ago but never got any result.



Article: 28542
Subject: Re: Oscillator for FPGA - low cost
From: Peter Alfke <peter.alfke@xilinx.com>
Date: Tue, 16 Jan 2001 15:53:12 -0800
Links: << >>  << T >>  << A >>
Mladen
If you lived in the US, the answer would be very simple:
Go to the nearest parts distributor and buy a canned crystal oscillator for
about $1 to $2 in small quantity. ( It runs on 3.3 or 5 V and drives your FPGA
easily)
The FPGA input has a 10 pF max impedance, and no dc current !
There are also a number of oscillator manufacturers in Europe ( I remember
some Swiss manufacturers from the recent Electronica fair).
Building your own with a transistor, and ending up with an unacceptable supply
voltage is not the right solution.

Regards,

Peter Alfke
==========================
Mladen Veselic wrote:

> Hello,
>
> I know this is a little off topic ...
>
> FPGA that I'm using have CMOS threshold on CLK input. Vtrh=3.1v and
> Vtrl=1,3v ( 5V supply ).
> Standard Quartz oscillator build with TTL gates inside can reach these
> thresholds on lower frequencies <10MHz. On higher frequencies amplitude
> drops and threshold are not reached or, in some cases, FPGA is randomly
> triggered. Also CLK input have very low impendance.
> I have build my own quartz oscillator with BF246 transistor but it requires
> 30V to archive 3Vpp output when  loaded with FPGA.
> Can anybody give me an advice how to implement crystal oscillator with:
> - output amplitude >2.5 v
> - work with crystals from 1MHz  to  ~50 MHz ( fundamental frequency )
> - high fanout
> - without expensive special components.
>
> Thankful for any design experience.
>
> --
> Veselic Mladen
> Sigma Laboratorija
> ECO Inzenjering


Article: 28543
Subject: FPGA driving clock line
From: Dean Armstrong <daa1@cs.waikato.ac.nz>
Date: Wed, 17 Jan 2001 12:55:10 +1300
Links: << >>  << T >>  << A >>
Hi All,

Is it possible to drive a clock line for a Spartan II device and three
Xilinx XC9500XL CPLD devices from a user IO pin on another Spartan II.
The application is one where I want logic within the main Spartan to
select between two different input clocks. To be used for itself and the
other devices.

Thanks
Dean Armstrong


Article: 28544
Subject: Re: FPGA driving clock line
From: Dean Armstrong <daa1@cs.waikato.ac.nz>
Date: Wed, 17 Jan 2001 12:56:44 +1300
Links: << >>  << T >>  << A >>
Sorry,  I also forgot to mention that this will only be operating at low
frequencies (~2MHz).

Dean Armstrong wrote:

> Hi All,
>
> Is it possible to drive a clock line for a Spartan II device and three
> Xilinx XC9500XL CPLD devices from a user IO pin on another Spartan II.
> The application is one where I want logic within the main Spartan to
> select between two different input clocks. To be used for itself and the
> other devices.
>
> Thanks
> Dean Armstrong


Article: 28545
Subject: Re: FPGA driving clock line
From: "S. Ramirez" <sramirez@deletethis.cfl.rr.com>
Date: Wed, 17 Jan 2001 00:14:17 GMT
Links: << >>  << T >>  << A >>

"Dean Armstrong" <daa1@cs.waikato.ac.nz> wrote in message
news:3A64DFBC.A895C809@cs.waikato.ac.nz...
> Sorry,  I also forgot to mention that this will only be operating at low
> frequencies (~2MHz).
>
> Dean Armstrong wrote:
>
> > Hi All,
> >
> > Is it possible to drive a clock line for a Spartan II device and three
> > Xilinx XC9500XL CPLD devices from a user IO pin on another Spartan II.
> > The application is one where I want logic within the main Spartan to
> > select between two different input clocks. To be used for itself and the
> > other devices.
> >
> > Thanks
> > Dean Armstrong


Dean,
It' hard to determine exactly what you are talking about.  Let me see if I
have this right.  You have two Spartan II devices and three CPLDs.  You call
one Spartan II device the "main" device, and you want logic on this device
to select from two different input clocks for itself as well as the other
Spartan II device and three CPLDs.

This means that the main Spartan II will have two or more input clocks, and
it is going to select the clock and drive itself as well as the other
Spartan II and the three CPLDs.  I thnk that the following are applicable:
   1.  You won't have a clock out of main Spartain II
         until after configuration.  It could glitch, too.
         Can you handle this?
   2.  The logic selecting the clock is totally combinatorial
        and not dependent on any of the clocks.
  3.  You drive the selected clock to a IO pad and distribute
        the clock to both Spartan IIs and CPLDs.
  4.  The IO pad will be tristated and weakly pulled high.
       You might want to pull it high with an external pull up
        resistor.
  5.  The clock network will probably have no termination
       or a mild termination (pullup resistor?) due to the
       Spartan II 24ma limit.  The clock may be 2 MHz, max,
       but you still have to contend with those edges.
  6.  You're not too worried about duty cycle.  At 2 MHz,
        I think this would be true.

Without having more information to work with, this is what I came up with.
It would be nice to know how you are originally generating the clock, as the
clock selection can be made there, too.

With what you have, though, I would be tempted to select the clocks in the
CPLDs, though, because they come right up after power on.
Simon Ramirez, Consultant
Synchronous Design, Inc.
Oviedo, FL  USA




Article: 28546
Subject: Re: FPGA driving clock line
From: Dean Armstrong <daa1@cs.waikato.ac.nz>
Date: Wed, 17 Jan 2001 13:25:13 +1300
Links: << >>  << T >>  << A >>
Hi Simon,

Thanks for your reply.

You understood me correctly.

The intention is that one clock source be a crystal oscillator at about 2MHz,
the other will be a push button (which will be debounced in programmable logic
somewhere). A third input (an on/off switch) will select between the two. This
will allow the devices to run on the clock or be switched into a single-step
mode.

Basically, what I am designing is a computer system that can free-run, or be
switched into a mode where the CPU and bus operations are single stepping. Some
of these devices (eg UART, programmable timer) will still need the high speed
clock to perform their operations correctly, but all bus transactions with them
will be single stepped.

Thanks,
Dean

"S. Ramirez" wrote:

> "Dean Armstrong" <daa1@cs.waikato.ac.nz> wrote in message
> news:3A64DFBC.A895C809@cs.waikato.ac.nz...
> > Sorry,  I also forgot to mention that this will only be operating at low
> > frequencies (~2MHz).
> >
> > Dean Armstrong wrote:
> >
> > > Hi All,
> > >
> > > Is it possible to drive a clock line for a Spartan II device and three
> > > Xilinx XC9500XL CPLD devices from a user IO pin on another Spartan II.
> > > The application is one where I want logic within the main Spartan to
> > > select between two different input clocks. To be used for itself and the
> > > other devices.
> > >
> > > Thanks
> > > Dean Armstrong
>
> Dean,
> It' hard to determine exactly what you are talking about.  Let me see if I
> have this right.  You have two Spartan II devices and three CPLDs.  You call
> one Spartan II device the "main" device, and you want logic on this device
> to select from two different input clocks for itself as well as the other
> Spartan II device and three CPLDs.
>
> This means that the main Spartan II will have two or more input clocks, and
> it is going to select the clock and drive itself as well as the other
> Spartan II and the three CPLDs.  I thnk that the following are applicable:
>    1.  You won't have a clock out of main Spartain II
>          until after configuration.  It could glitch, too.
>          Can you handle this?
>    2.  The logic selecting the clock is totally combinatorial
>         and not dependent on any of the clocks.
>   3.  You drive the selected clock to a IO pad and distribute
>         the clock to both Spartan IIs and CPLDs.
>   4.  The IO pad will be tristated and weakly pulled high.
>        You might want to pull it high with an external pull up
>         resistor.
>   5.  The clock network will probably have no termination
>        or a mild termination (pullup resistor?) due to the
>        Spartan II 24ma limit.  The clock may be 2 MHz, max,
>        but you still have to contend with those edges.
>   6.  You're not too worried about duty cycle.  At 2 MHz,
>         I think this would be true.
>
> Without having more information to work with, this is what I came up with.
> It would be nice to know how you are originally generating the clock, as the
> clock selection can be made there, too.
>
> With what you have, though, I would be tempted to select the clocks in the
> CPLDs, though, because they come right up after power on.
> Simon Ramirez, Consultant
> Synchronous Design, Inc.
> Oviedo, FL  USA


Article: 28547
Subject: Re: Looking for prototyping board
From: "S. Ramirez" <sramirez@deletethis.cfl.rr.com>
Date: Wed, 17 Jan 2001 00:27:04 GMT
Links: << >>  << T >>  << A >>

"Juan Antonio Gómez Pulido" <jangomez@unex.es> wrote in message
news:3A62C11A.57D215C8@unex.es...
> Hi!
>
> I am looking for a prototyping board with a great Virtex FPGA. This
> board should have PCI communication, RAM modules and interfacing
> software.
>
> Thanks a lot,
>
> -- Juan
> University of Extremadura. Spain


Juan,
   Have you looked at PLX's prototyping board?  Check out:
                  http://www.plxtech.com/tools/rdk/9054rdk-lite.htm

This kit is a PCI prototype adaptor board with a PLX PCI9054 32-bit/33MHz
PCI interface chip.  It also has surface mount footprints on the board that
support industry standard packages.  It comes with a CD-ROM which includes
complete hardware design info and software tools, inclduing a reference
manual, OrCAD schematics, Gerber files, BOM, software tools, etc.
     In short, this kit has everything you need to put some devices on the
board, wire it together to the PCI chip, plug it into a PCI slot and start
working on the software.  This kit is great if you have to do a one of a
kind product.  The PCI interface chip is an industry standard, too.
Simon Ramirez, Consultant
Synchronous Design, Inc.
Oviedo, FL  USA



Article: 28548
Subject: Re: revision control tools ??
From: Eric Smith <eric-no-spam-for-me@brouhaha.com>
Date: 16 Jan 2001 16:32:24 -0800
Links: << >>  << T >>  << A >>
hamish@cloud.net.au (Hamish Moffatt VK3SB) writes:
> Sure, but ClearCase is much better. For one thing, because it
> has a custom virtual file system on the client (MVFS -- multi version
> file system) it can do a lot of things which CVS can't do.

On the other hand, depending on a special file system is also a
disadvantage.  It's not portable, and it prevents you from using
some tools that are available for normal file systems.

> It's integrated quite well into NT, as well as Unix.

Too well, some of us claim.

CVS has some deficiencies, but for most projects it works
quite well.

Article: 28549
Subject: Re: Oscillator for FPGA - low cost
From: Eric Smith <eric-no-spam-for-me@brouhaha.com>
Date: 16 Jan 2001 16:33:55 -0800
Links: << >>  << T >>  << A >>
"Mladen Veselic" <veselic@eunet.yu> writes:
> FPGA that I'm using have CMOS threshold on CLK input. Vtrh=3.1v and
> Vtrl=1,3v ( 5V supply ).
> Standard Quartz oscillator build with TTL gates inside can reach these
> thresholds on lower frequencies <10MHz. On higher frequencies amplitude
> drops and threshold are not reached or, in some cases, FPGA is randomly
> triggered.

Why not buy CMOS-output oscillators?  I've had no trouble with them.



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