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Messages from 28600

Article: 28600
Subject: Re: CMOS or TTL
From: Ray Andraka <ray@andraka.com>
Date: Thu, 18 Jan 2001 02:10:09 GMT
Links: << >>  << T >>  << A >>
I started out in the mid 70's with TTL I was buying from junk resellers like
Poly-Paks.  Back then CMOS was new, and at the time it was very slow compared to
TTL, plus it died if there was a static discharge anywhere in the same room if
it was out of it's foil wrapper it came in.  Back then, we used CMOS when power
was a consideration (or when you didn't want to mess with regulated power
supplies).  So what is slow?  TTL gates delays were measured in tens of
nanoseconds (a 7474 D flip-flop had a clock to out of 40 ns).  CMOS gates
delays, in some cases were specified in microseconds.

CMOS has since come a long way, and TTL has more or less gone the way of the
dinosaur (what is sold as TTL now is generally CMOS with TTL level outputs).  

The good thing those days was the Joe Hobbyist could walk into Radio Shack and
pick up quite a variety of TTL parts (you'd pay through the nose at Radio Shack,
but you didn't have to wait a week for it to come from a mail order place). 
What a great way to learn about logic, as well as learning how to troubleshoot a
real design (those designs in Radio Electronics never worked as advertised). 
Fast forward to now, and the hobbyist's best hope is an FPGA board, which he
isn't going to throw together with $10-15 of surplus parts.  

Thanks for the Nostalgic trip!  (No, I wouldn't want to go back)

Peter Alfke wrote:
> 
> This discussion looks like a time warp.
> TTL was created in the 'sixties and, through Low-power Schottky variations,
> served us into the 'eighties. But that's almost 20 years in the past...
> All modern development is, and has been, in CMOS, with some GaAs and
> belated ECL thrown in for extra high speed.
> I spent the first half of my professional life designing with TTL, but that
> is now just a faint memory...
> 
> Peter Alfke
> 
> plogic1@my-deja.com wrote:
> 
> > Its all depend on what you are trying to do.Industry prefers CMOS
> > due to its size of the devices and the relative low power. But on the
> > other hand the devices may be a bit expensive.
> >
> > Reg
> >
> > plogic1
> >
> > In article <9443qv$njm$1@nnrp1.deja.com>,
> >   erika_uk@my-deja.com wrote:
> > > hello,
> > >
> > > which provides better performance CMOS or TTL based devices?
> > > I believe that CMOS gives better performance, and it's the CMOS based
> > > devices which are more expensive...but my friend told me the inverse ?
> > >
> > > but what let the better to be better ?
> > > are all fpga based CMOS devise ?
> > >
> > > any input  ?
> > >
> > > --Erika
> > >
> > > Sent via Deja.com
> > > http://www.deja.com/
> > >
> >
> > Sent via Deja.com
> > http://www.deja.com/

-- 
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com  or http://www.fpga-guru.com

Article: 28601
Subject: Re: FSM encoding
From: Ray Andraka <ray@andraka.com>
Date: Thu, 18 Jan 2001 02:27:46 GMT
Links: << >>  << T >>  << A >>


elmoties@hotmail.com wrote:
> 
> Hi,
> 
> I'm designing an arithmetic accelerator for the Xilinx Virtex 50K.
> 
> I'm having trouble synthsizing a design that I thought would fit with no
> problems.  Xilinx's ISE 3.1i reports only using about 10500 gates but it
> requires 99% of the slices on the FPGA.
> 
> The design is a large FSM that has about 30 states.  There is four
> registers (idealing I want to have > 128 bit) that have operations
> performed between them (xor, shifting with feedback) in several of the
> states.  Most of the other states just before trivial signaling for
> memory loading.
> 
> Several of the states have case statements contained with-in them to
> determine when to peform specific operations.
> 
> My questions: (I'm more than willing to post more information if
> somebody wants it)
> 
> Do FPGA's have an inherently hard time laying out large FSM's?
> Is there a particular FSM encoding that is better than others for space
> considerations?

THere are two things that need to be considered.  First is the logic
implementation,
which for a FSM means reducing the equations to logic.  This is a function of
your 
coding style as well as of the synthesis and mapper algorithms.  If you have
nested ifs
in your code, those will often generate many levels of logic, often shared.
Signals that 
have more than one destination are harder to layout.  I don't know that any one
encoding
is going to work out better space wise without knowing how many ins and outs to
each state.
The second is the placement.  I am still not very impressed with the abilities
of the 
automatic placer.  Unfortunately, a synthesized FSM is very difficult to place
by hand, and
because it usually has several levels of combinatorial logic is subject to
instance name changes
when the design is iterated.



> Is having nested states (via cases statements inside a state) a bad
> thing for compact sythesizing?

can be.
> Is having nonstandard signal sizes that are quite large ( greater than
> 128 bit) really difficult to place and route on an FPGA
> 
No,not usually.  The current FPGA placement tools do not seem to have much
awareness of 
whether a signal is part of a bus or not.

a few suggestions:

1) You might use the block rams in the XCV50 for the FSM, it will provide a
faster machine, and 
alot less sensitivity to changes in the state machine definition.  I think there
may be a
xilinx app-note on it.  The BRAM is used as a ROM that outputs the next state,
plus any decoded outputs
as a function of the current (encoded) state and some inputs.  If there are many
inputs, they can usually
be selected by a mux using the current state to reduce the number of address
pins needed for the memory.

2) Break the state machine into several smaller linked state machines.  It makes
it easier for the synthesis and placement,
and also has the advantage of usually making it easier for you to follow when
you come back to it 6 months from 
now.  It will most likely also reduce the number of inputs to at least some of
the states.  It sounds like you might have
some data path mixed in with your state machine.  That's the first place I'd
look for subdividing.



> Thanks,
> 
> Jeff Elmot
> 
> Sent via Deja.com
> http://www.deja.com/

-- 
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com  or http://www.fpga-guru.com

Article: 28602
Subject: Re: revision control tools ??
From: Eric Smith <eric-no-spam-for-me@brouhaha.com>
Date: 17 Jan 2001 18:37:14 -0800
Links: << >>  << T >>  << A >>
eml@riverside-machines.com.NOSPAM writes:
> I don't think anyone's mentioned [...] Microsoft's Sourcesafe.

There are very good reasons for nobody having mentioned the S-word.
I used that at a former job, and although version 5 doesn't corrupt
its repository as often as earlier versions, it still has lots of
major problems.

It has a concept they call "branching", which has absolutely no
connection to the way "real" source control systems do branching.

The thing is a joke.  Several MS employees have told me that almost
noone inside MS uses it.

They actually used to *brag* on their web site about how it came with
a tool for fixing corrupted repositories.  Hmmm, neither RCS nor CVS
came with one of those.  I guess SS is better.  :-)

If you read the fine print of the information on that tool, though,
they mentioned that if a repository was very corrupt, you might have
to run the tool multiple times.  What, they can't even figure out
when they're done?

Article: 28603
Subject: FAQ for this news group? (or What is an FPGA?)
From: Terry Hicks <hicksthe@egr.msu.edu>
Date: Wed, 17 Jan 2001 22:10:34 -0500
Links: << >>  << T >>  << A >>
Today a fellow student (Masters level EE) asked me "What is an FPGA?"
Of course I know what an FPGA is but I didn't have the time to deal with
the question at the time.  (Late for another appointment...)  He also
wanted to know if there was a book dealing with the question.  So I
thought I would ask the newsgroup if anyone was aware of a FAQ on the
subject.  Also maybe you can recommend a web site he could peruse.
Perhaps a good book on the subject?

Thanks for your help,
Theron Hicks


Article: 28604
Subject: Re: FAQ for this news group? (or What is an FPGA?)
From: Ray Andraka <ray@andraka.com>
Date: Thu, 18 Jan 2001 04:51:59 GMT
Links: << >>  << T >>  << A >>
Skahill's VHDL for Programmable logic has a passable description of what an FPGA
is in it.

Terry Hicks wrote:
> 
> Today a fellow student (Masters level EE) asked me "What is an FPGA?"
> Of course I know what an FPGA is but I didn't have the time to deal with
> the question at the time.  (Late for another appointment...)  He also
> wanted to know if there was a book dealing with the question.  So I
> thought I would ask the newsgroup if anyone was aware of a FAQ on the
> subject.  Also maybe you can recommend a web site he could peruse.
> Perhaps a good book on the subject?
> 
> Thanks for your help,
> Theron Hicks

-- 
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com  or http://www.fpga-guru.com

Article: 28605
Subject: Re: Virtex-II officially launched
From: Bob Perlman <bob@cambriandesign.com>
Date: Thu, 18 Jan 2001 05:48:54 GMT
Links: << >>  << T >>  << A >>
On Wed, 17 Jan 2001 08:04:22 -0800, Austin Lesea
<austin.lesea@xilinx.com> wrote:

>Bob,
>
>The impedance updates are asynchronous, and are done in such a manner that
>the updates trim values are all extremely small.  The resultant dR/dt is
>undetectable in the signal integrity of the output.
>
>They must have really done a bad job in the ASIC's if it affected the SI.
>Too bad that when they do an ASIC they have no time to get it right.
>
>Austin

The ASIC impedance updates are very small, too; that's not the
problem.  The issue is the manner in which you parallel drivers to
achieve adjustable impedance, and how you control the enabling and
disabling of those drivers.

If, for example, you have 16 mini-drivers, all of strength A, and you
adjust impedance by adjusting the number of active drivers, there
should be no problem.  

But this is an expensive solution.  If, on the other hand, you have
drivers of drive strength A, 2A, 4A, and 8A, you can get 15 different
impedances.  But what happens if you make a 1 quanta change by going
from the case in which A, 2A and 4A are on to the case is which only
8A is on?  The change is small, but if the transition isn't handled
properly, you could have a large transient in apparent impedance.  If
this occurs at the wrong time, it's a disaster.  Does Xilinx guarantee
that this can't happen?

Thanks,
Bob Perlman

>
>Bob Perlman wrote:
>
>> On Mon, 15 Jan 2001 10:14:39 -0800, Peter Alfke
>> <peter.alfke@xilinx.com> wrote:
>>
>> >Highest on my list of exciting features is the Digitally Controlled
>> >Impedance, which effectively puts the series termination resistor
>> >right into the output driver, or the parallel termination right into
>> >the input buffer ( all optionally of course). It will be a gods-end
>> >for people putting >500-pin packages on a pc-board, not having to
>> >bother with resistor packs...
>>
>> This will be extremely useful.
>>
>> One question, Peter: some ASIC vendors have been offering this feature
>> for a while, but some implementations are problematic.  Is the Virtex
>> II impedance update mechanism asynchronous to the user's clock?  If
>> so, is there a guarantee that the impedance can't glitch (say, the way
>> a D/A might) at a critical moment?
>>
>> Thanks,
>> Bob Perlman


Article: 28606
Subject: VHDL question
From: #ROBERTUS WAHENDRO ADI# <PH671019@ntu.edu.sg>
Date: Thu, 18 Jan 2001 14:10:15 +0800
Links: << >>  << T >>  << A >>
Hi all,
Can variable be shared between one process to another?
if yes, How to do it?

tia
Robertus Wahendro Adi



Article: 28607
Subject: DSP->FPGA development board
From: bjorn_lindegren@my-deja.com
Date: Thu, 18 Jan 2001 07:36:25 GMT
Links: << >>  << T >>  << A >>
Hi

I'm looking for a development borad whith a DSP and a FPGA 'Xilinx, a
big one....Spartan II or something'.

I want this board to have a A/D and a D/A converter for analog sampling.


If you know any board like this, I will be thankefull for know about it.


Regards

Björn Lindegren


Sent via Deja.com
http://www.deja.com/

Article: 28608
Subject: Development board, DSP->FPGA
From: bjorn_lindegren@my-deja.com
Date: Thu, 18 Jan 2001 07:55:32 GMT
Links: << >>  << T >>  << A >>
Hi


I'm looking for a development board whith a DSP and a FPGA 'Spartan II
or something.
I want this board to have a A/D and a D/A converter.



If you know and board like this, Please tell me.

Regardes

Björn Lindegren




Sent via Deja.com
http://www.deja.com/

Article: 28609
Subject: Re: About programming cables
From: Nial Stewart <nials@sqf.hp.com>
Date: Thu, 18 Jan 2001 08:10:23 +0000
Links: << >>  << T >>  << A >>
John Grider wrote:
> 
> "Juan M. Rivas" wrote:
> >
> > I'm looking for a Progrmming Cables from Xilinx, for a stand alone FPGA
> > proyect:  Does anyone know wher I can by one, and which one is good?
> >
> > I've been looking for the Multilinx, and the Xcheqer,  but I can't
> > decide...Besides I can't find where to find them (Always out of stock)
> >
> > Suggestions???
> >
> > Thanks all
> 
> You could always build your own parallel/jtag cable - the schematics are
> availible from xilinx's web site.  It looks simple, just two 74xxx's and
> a couple diodes, caps, etc.
> -- John

Xilinx couldn't supply any more parrallel cable so the technician here
built a few more.

They work well and are _much_ faster than the multilinx cable (programming
an xcv_1802 takes about 20 seconds as opposed to several minutes with the
multilinx).

Nial.

Article: 28610
Subject: Re: DSP->FPGA development board
From: Dirk Kautz <D.Kautz@omnitron-ag.de>
Date: Thu, 18 Jan 2001 09:18:58 +0100
Links: << >>  << T >>  << A >>
Hi,

take a look at http://www.elektronikladen.de/dsplog.html.

Dirk

bjorn_lindegren@my-deja.com schrieb:
> 
> Hi
> 
> I'm looking for a development borad whith a DSP and a FPGA 'Xilinx, a
> big one....Spartan II or something'.
> 
> I want this board to have a A/D and a D/A converter for analog sampling.
> 
> If you know any board like this, I will be thankefull for know about it.
> 
> Regards
> 
> Björn Lindegren
> 
> Sent via Deja.com
> http://www.deja.com/

Article: 28611
Subject: WTB: Virtex-based board
From: Chai Mee Joon <chaimj@singnet.com.sg>
Date: Thu, 18 Jan 2001 17:50:57 +0800
Links: << >>  << T >>  << A >>
Hi everyone,


If you're upgrading and would like to let go of your 
Virtex-based board, please make me an offer.
(I pay for the shipping too)
 

Thanks for reading.

 
Chai Mee Joon, Lawrence <chaimj@singnet.com.sg>

Article: 28612
Subject: Re: revision control tools ??
From: hamish@cloud.net.au (Hamish Moffatt VK3SB)
Date: Thu, 18 Jan 2001 09:59:29 GMT
Links: << >>  << T >>  << A >>
In comp.lang.vhdl Steve O'Hara-Smith <steve@ams-gw.sohara.org> wrote:
> 	CVS is much better than Clearcase when you have many developers
> geographically separated. Add cvsup to the kit and it is very hard
> to beat for that case.

Well, if you have several sites, ClearCase has multi-site with
synchronization between them. Not too practical if you have many
small sites though (eg developers working from home).


Hamish
-- 
Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>

Article: 28613
Subject: Re: Virtex-II officially launched
From: "Gary Watson" <gary2@nexsan.com>
Date: Thu, 18 Jan 2001 10:22:48 -0000
Links: << >>  << T >>  << A >>

I have a proto design based on the Spartan II and the XC18V01, in master
serial mode.  What I did was to connect CCLK and DOUT to a pair of the I/O
pins on the Spartan II.  I've not connected DONE to CE like the spec
suggests -- I've just pulled up DONE.  The idea is that I use the JTAG port
to load my unique 48 bit serial number into the config prom immediately
after the Spartan II bitstream, and once the FPGA design wakes up, it will
toggle the CCLK line 48 times to milk out my serial number.  I'm not sure it
will actually work when I try it, so I've put a socket on the board for a
93C56 eeprom in case this kludge fails me.

Along these lines, it would have been nice if the Virtex II designers added
another 16 bytes or so of battery-backed up user RAM which could be loaded
via JTAG and read internally like a block RAM...

--

Gary Watson
gary2@nexsan.com  (you should leave off the digit two for email)
Nexsan Technologies Ltd.
Derby DE21 7BF  ENGLAND
UK-based Engineers: See our job postings at
http://www.nexsan.com/pages/careers.htm

"Austin Lesea" <austin.lesea@xilinx.com> wrote in message
news:3A65C3C1.CC4CC096@xilinx.com...
> Gary,
>
> The battery backed up key RAM for the DES keys holds six 56 bit numbers.
>
> If you were to use the BBRAM in the non-secure mode (ie not using the DES
> encryption feature), then these locations are kept and can be written and
read
> through the JTAG port (only) for test purposes (or for any other purpose).
>
> When you set the unit for DES operation, then these keys may be written
to, but
> not read back out.  Any attempt to fiddle with it (ie changing back to
> non-secure mode) wipes out the keys, and cleans out the part's
configuration.
>
> The BBRAM supply is less than 100 pA (room temp), so a 350 mA lithium coin
cell
> would last 15 years.
>
> Austin
>
> Gary Watson wrote:
>
> > In a volume production environment, is there any way to load a unique
serial
> > number into a Virtex-II?  (Assuming that this is a SOC application where
> > there is no external microprocessor...)
> >
> > --
> >
> > Gary Watson
> > gary2@nexsan.com  (you should leave off the digit two for email)
> > Nexsan Technologies Ltd.
> > Derby DE21 7BF  ENGLAND
> > UK-based Engineers: See our job postings at
> > http://www.nexsan.com/pages/careers.htm
> >
> > "Rune Baeverrud" <fpga@no.spam.iname.com> wrote in message
> > news:979567585.218715@news2.cybercity.dk...
> > > Hello,
> > >
> > > Xilinx Virtex-II has now been officially announced.
> > >
> > > Check out the press release:
> > > http://www.xilinx.com/prs_rls/vtx2ship.htm
> > >
> > > and the Virtex-II Handbook:
> > > http://www.xilinx.com/products/virtex/handbook/index.htm
> > >
> > > Some highlights are:
> > > - digitally controlled impedances for input and output pins
> > > - new resources for clock management and clock synthesis
> > > - digital spread spectrum clocking
> > > - encrypted bitstreams
> > > - dedicated multipliers
> > >
> > > Go and see for yourself!
> > >
> > > Regards,
> > > Rune Baeverrud
> > >
> > >
> > >
>
>



Article: 28614
Subject: Re: revision control tools ??
From: Paul Campbell <paul@verifarm.com>
Date: Thu, 18 Jan 2001 10:27:39 +0000
Links: << >>  << T >>  << A >>
Jamie Sanderson wrote:

> <eml@riverside-machines.com.NOSPAM> wrote in message
 
> > 2)
> > The other obvious one - CVS doesn't have reserved checkouts. In fact,
> > I did a quick survey of VCS tools recently, and opinion was divided on
> > whether a tool should support reserved checkouts or not. RCS, SCCS,
> > MKS, Clearcase, WebDAV, Sourcesafe, and Perforce all thought that it
> > should, CVS thought that it shouldn't.
> 
> Isn't this what "cvs admin -l" does?

yes - sort of - but it's not as simple as for other systems (in particular 
you need to have the CVS admin account to turn on the locking thing, it 
can't be done by anyone with normal access)

> > I had an argument with someone recently who had used CVS on a large
> > ASIC project, and their reply was that "this doesn't happen in
> > practice". IMO, it will happen eventually, and the whole point of a
> > management tool is to enforce systems to prevent this sort of thing
> > happening.
 
This is an issue that often inspires almost 'religious' fervor. I've worked 
under both regimes and much prefer  hard locks for large projects.

The main difference between the two ways of working is that taking a hard 
lock serializes design work during updates (between when you check out a 
file, change it, verify the change and commit the change) while the CVS way 
of working people work indepenantly and the any issues get resolved when 
you commit - the upside is that two people can work on the same file at the 
same time - the downside is that your changes might effect each other (CVS 
will also merge files for you - I've seen software schedules missed because 
of bugs introduced by CVS's merging - you have to verify each CVS checkin 
extremely carefully and verify the results AFTER as well as before). 

Hard locking has its downside too - deadlocks are possible if you need to 
check out multiple files (a good rule of thumb is to check out from the top 
of the hierarchy down), also you run the risk of the guy who checks 
something out, forgets an goes on vacation .... you need discipline - plan 
a change, check out the files, make the changes, verify them, check them in 
again - having a good quick system sanity test that people can run is a 
great idea.

In practice people tend to work on their own blocks independantly and CVS 
checkin (or locking) collisions tend not to happen at that level in the 
hierarchy - it's the upper levels of a design hierarchy (mostly wiring) 
that tend to have files that people want to edit at the same time.

Finally - a word in favor of CVS - I use it for (mostly solo) software 
development all the time - it has a secondary function that's really 
usefull - you can use it for backup from a remote server - just do periodic 
commits - if people are used to doing this then it can cause problems if 
you are working an a shared environmant 'at top of tree' (ie everyone's 
developing on the same latest checked in code). 

Finally for a large silicon project you need more than just source code 
control - you need to be able to manage binary files (routed blocks, 
synopsys .db files, etc) and really BIG files (your repository needs to be 
able to be on BIG disks, or have the ability to span multiple drives - and 
you need to be able to back it up). And you need to be able to manage 
multiple versions of files - the time from 
RTL->synopsys->layout->timing->whole-chip-timing/etc is so long that you 
often need to be able to manage multiple 'waves' of a design moving through 
the flow in parallel

Anyway, enough! as I said it's an almost religious issue I've probably 
offended everyone :-)

        Paul Campbell
        paul@verifarm.com

Article: 28615
Subject: Re: revision control tools ??
From: eml@riverside-machines.com.NOSPAM
Date: Thu, 18 Jan 2001 11:14:15 GMT
Links: << >>  << T >>  << A >>
On 17 Jan 2001 15:35:10 +0100, Petter Gustad <dev.null@dev.null.org>
wrote:

>What kind of functionality does MKS provide that CVS do not?

3 things I can think of off-hand:

1)
the obvious one - it's got a GUI. Ok, I'm not in favour of GUIs for
the sake of it, but if any tool needs a GUI then it's a VCS (or any
file manager, come to think of it). You get an immediate view of the
whole project, you can see which files are modified, you can sort on
tags, you can sort on modified files (irrespective of directory) so
that you can check in all modded files at once, you can checkout only
the required files without having to painfully remember and type each
one, or creating a new module name for each set you're likely to want,
you can see who's got what file checked out, and a dozen other things.

2)
The other obvious one - CVS doesn't have reserved checkouts. In fact,
I did a quick survey of VCS tools recently, and opinion was divided on
whether a tool should support reserved checkouts or not. RCS, SCCS,
MKS, Clearcase, WebDAV, Sourcesafe, and Perforce all thought that it
should, CVS thought that it shouldn't.

For those not familiar with reserved checkouts, it basically means
that you can checkout a file and put an exclusive lock on it. This
prevents anyone else checking in a modified version of the file before
you release your lock. If you're doing a mod that involves changing
half a dozen files in unison, and then checking them all in together,
the last thing you want is someone else modifying one of your files
before you've finished. Even if you're modifying one file you don't
want this. CVS's solution is to let anyone do whatever they want; if a
user wants to check in a file that someone else has already changed,
then CVS attempts to merge the 2 files, asking the second user to
confirm changes. Obviously, this is impossible with binary files, or
even with any machine-generated text files, quite apart from being
undesirable (and hardware projects contain a lot more
machine-generated files than software projects).

I had an argument with someone recently who had used CVS on a large
ASIC project, and their reply was that "this doesn't happen in
practice". IMO, it will happen eventually, and the whole point of a
management tool is to enforce systems to prevent this sort of thing
happening.

There's an argument that you can make CVS do reserved checkouts, if
you know how. In fact, there's a Perl script you can use which gets
you some of the way there, and theres a source code patch somewhere on
the web that also claims to do the job. Caveat emptor. I believe that
Cyclic were working on adding exclusive locks to CVS when they were
bought out, but I don't know what the situation is now.

3)
MKS implements a security mechanism in which you can set up projects
and groups, and assign permissions to people in groups, within a given
project. For instance, you may want to give a couple of people write
access to a given project, and give everyone else only read access; or
you may want to make sure that only some people can create or delete
archives. IMO, this is important when you have development groups with
a large range of abilities in them (and in which only a few people, if
any, have previously used a VCS).

>> CVS is pretty much the standard, but it's not for anyone who's got
>> better things to do than trawl through obscure documentation, and
>> control hundreds of files with an antiquated command line interface.
>
>Personally I don't like specilized GUIs to work against my revision
>control system. Most of the time I use CVS from within emacs (the vc
>interface) and the command line interface (from bash) when doing bulk
>type work (e.g. tagging source trees) or from scripts.
>
>> WinCVS does a good job of making CVS more usable, but it's not really
>
>You mean it's more usable because it provides a GUI or does it add
>functionality?

Just the GUI with a 'explorer'-type file manager - no extra features
that I know of. I'm not very keen on the GUI - it doesn't give you a
project view, for example; it simply shows you what files are under
revision control, and whether they've changed. On MKS you can get a
view of your project, and switch between tree and list views - the
list view let you see (and sort) everything, irrespective of
directory.

>I work mainly in a Solaris/Linux environment and I'm very happy with
>CVS. However, I had some problems with the Windows port of CVS. Today
>I tried to check in a netlist and I got:
>
>cvs server: Up-to-date check failed for `PSB63.edf'
>cvs [server aborted]: correct above errors first!
>
>I had to transfer the files over to Solaris and check them in from
>there...

Unfortunately, I occasionally get errors as well

>> finished yet, and it's nowhere near as good as MKS. Security is also a
>> problem.
>
>What's the problem with the CVS/ssh combo? 

I don't mean security as in unauthorised access - I mean project
security, as in making sure that people don't inadvertantly mess up
the project by doing the wrong thing, which can happen if you don't
have exclusive locks, enforced procedures, and so on.

Here's an example from a couple of weeks ago. I wanted to import a
module using WinCVS. The "import module" selection is the next one
down on the menu from "create repository". I clicked "create
repository" by mistake, and then quickly clicked "ok" by mistake,
instead of "cancel". The new repository defaults to the same place as
the old repository - it took several hours to find out what had
happened and to restore from tape afterwards. Ok, you can't make this
mistake from the command line interface, but my point is that project
security is more complex than making sure that you have a secure
connection to the server, and that's one thing that commercial
products do better than CVS.

Evan

Article: 28616
Subject: Re: DSP->FPGA development board
From: plogic1@my-deja.com
Date: Thu, 18 Jan 2001 12:04:53 GMT
Links: << >>  << T >>  << A >>
Here is another good one ...exactley what you need ....

http://www.xilinx.com/ipcenter/catalog/search/alliancecore/gva_gva-250_v
irtex_dsp_hardware_accelerator.htm

Reg
Chipman


In article <3A66A6F2.DC233142@omnitron-ag.de>,
  Dirk Kautz <D.Kautz@omnitron-ag.de> wrote:
> Hi,
>
> take a look at http://www.elektronikladen.de/dsplog.html.
>
> Dirk
>
> bjorn_lindegren@my-deja.com schrieb:
> >
> > Hi
> >
> > I'm looking for a development borad whith a DSP and a FPGA 'Xilinx,
a
> > big one....Spartan II or something'.
> >
> > I want this board to have a A/D and a D/A converter for analog
sampling.
> >
> > If you know any board like this, I will be thankefull for know about
it.
> >
> > Regards
> >
> > Björn Lindegren
> >
> > Sent via Deja.com
> > http://www.deja.com/
>


Sent via Deja.com
http://www.deja.com/

Article: 28617
Subject: Re: FPGA for radar digital downconversion
From: Ken Chapman <ken.chapman@xilinx.com>
Date: Thu, 18 Jan 2001 12:58:11 +0000
Links: << >>  << T >>  << A >>
Dear Tom,

In simple terms, this is about the required horsepower for the application.
If you can really perform all the processing that you need to in a single
DSP processor chip then it does provide you with a very easy way to
prototype your system.

However, at 50MHz sample rate you will soon burn up the available number of
MIPS available to you in a DSP processor. If we consider the
TMS320VC5410-10 device, it has a single 17x17 multiplier clocked at 100MHz.
This would only allow you to perform 2 operations at 50MHz. Obviously you
will be performing down-conversion to carry out most of your work at a
lower sample rate, but this down-conversion in itself will almost certainly
require more than this 100MIPS. These processors are really excellent when
you have lots of time between samples such as in audio. At At 48KHz the
100MIPS provides over 2000 operations per sample.

In contrast, a device such as the Xilinx Spartan-II XC2S150 is a 'blank
sheet' onto which a DSP design can be implemented. It contains 864
Configurable Logic Blocks which could implement 10 full 16x16 multipliers
operating at over 100MHz. That provides over 1000 MIPS. Unlike the fixed
architecture of a processor where flexability is derived via software code
that utilises 'spare' clock cycles (if you have any), the Xilinx route
provides you the flexability to produce any architecture containing
multipliers, adders, comaparitors etc all working in parallel. It is highly
unlikely you will need full 16x16 multipliers and this means that the
effective MIP count can be increase as smaller modules are constructed.

The Spartan devices are in the $5 to $20 range providing a lot of
processing potential per $ compared with a DSP processor. If you have not
looked at Xilinx DSP before then you will need to take some time to look
into it and how designs can be implemented. There are tools that generate
complete FIR filters and NCOs for you as well as the simple blocks.

I have worked on RADAR systems before joining Xilinx, and many times with
Xinlinx customers during my 10 years with the company. Some of the most
successful systems are the ones that combine the merits of both the Xilinx
devices and the DSP processors. The Xilinx device is used to perform the
intensive processing of the data path flow. The DSP processor acts as a
controller and less time critical calculator. In your case the actual beam
forming would probably be done by the FPGA, but the calculation of
coefficients to set the beam pattern would be made by the DSP processor.

There are DSP seminars by Xilinx on the 25th January all over North
America. Try to go to one!

Yours sincerely,

Ken Chapman

Xilinx Applications (UK)



Article: 28618
Subject: Re: Virtex-II officially launched
From: "Gary Watson" <gary2@nexsan.com>
Date: Thu, 18 Jan 2001 13:59:32 -0000
Links: << >>  << T >>  << A >>
Actually, I should have said that I pulled up DONE and put a pulldown on CE.
Just in case, I have a resistor location for a 0 ohm resistor to tie the two
back together just in case my cunning plan fails.

--

Gary Watson
gary2@nexsan.com  (you should leave off the digit two for email)
Nexsan Technologies Ltd.
Derby DE21 7BF  ENGLAND
UK-based Engineers: See our job postings at
http://www.nexsan.com/pages/careers.htm
"Gary Watson" <gary2@nexsan.com> wrote in message
news:ytz96.1655$wL5.32760@NewsReader...
>
> I have a proto design based on the Spartan II and the XC18V01, in master
> serial mode.  What I did was to connect CCLK and DOUT to a pair of the I/O
> pins on the Spartan II.  I've not connected DONE to CE like the spec
> suggests -- I've just pulled up DONE.  The idea is that I use the JTAG
port
> to load my unique 48 bit serial number into the config prom immediately
> after the Spartan II bitstream, and once the FPGA design wakes up, it will
> toggle the CCLK line 48 times to milk out my serial number.  I'm not sure
it
> will actually work when I try it, so I've put a socket on the board for a
> 93C56 eeprom in case this kludge fails me.




Article: 28619
Subject: Re: FAQ for this news group? (or What is an FPGA?)
From: Vikram Pasham <Vikram.Pasham@xilinx.com>
Date: Thu, 18 Jan 2001 06:13:55 -0800
Links: << >>  << T >>  << A >>
Terry,

I am not sure if this newsgroup has a FAQ section but you can find basic
details on Optimagic website. They also have  a FAQ section and discuss
several topics on programmable logic like FPGA, CPLDs, architectures,
programmability differences etc.
Refer Optimagic FAQs at http://www.optimagic.com/faq.html

Unfortunately, they haven't updated this website in last couple of months.

Back in school, I used "Field Programmable Gate Array Technology" by Steve
Trimberger. This book has details on various FPGA architectures, SRAM/
Anti-fuse technology, etc. This book serves as a good reference for
beginners.

-Vikram
Xilinx Applications

Terry Hicks wrote:

> Today a fellow student (Masters level EE) asked me "What is an FPGA?"
> Of course I know what an FPGA is but I didn't have the time to deal with
> the question at the time.  (Late for another appointment...)  He also
> wanted to know if there was a book dealing with the question.  So I
> thought I would ask the newsgroup if anyone was aware of a FAQ on the
> subject.  Also maybe you can recommend a web site he could peruse.
> Perhaps a good book on the subject?
>
> Thanks for your help,
> Theron Hicks


Article: 28620
Subject: what placement and route tool?
From: kkdeep@my-deja.com
Date: Thu, 18 Jan 2001 15:54:03 GMT
Links: << >>  << T >>  << A >>
i have synthesized a design using synopsys fpga compiler II targeted at
xilinx XC4000 family. i want to know
1. what placelment and routing tool i have to use to complete my design
2. what are the different optins available?
3.is there any evaluation version avalable of these tools.
4.i have done the functional simulation at gate level by exporting VHDL
netlist? is there any way to simulate the timing before P & R.

 thankx in anticipation
 --kuldeep


Sent via Deja.com
http://www.deja.com/

Article: 28621
Subject: Re: Virtex-II officially launched
From: Peter Alfke <palfke@earthlink.net>
Date: Thu, 18 Jan 2001 16:09:26 GMT
Links: << >>  << T >>  << A >>


Bob Perlman wrote:

> The ASIC impedance updates are very small, too; that's not the
> problem.  The issue is the manner in which you parallel drivers to
> achieve adjustable impedance, and how you control the enabling and
> disabling of those drivers.
>
> If, for example, you have 16 mini-drivers, all of strength A, and you
> adjust impedance by adjusting the number of active drivers, there
> should be no problem.
>

That's what we are doing.
Thanks for the endorsement.

Peter Alfke


Article: 28622
Subject: fpga-cpu-subscribe @egroups.com
From: Paul Wiercienski <paulw@zucotto.com>
Date: Thu, 18 Jan 2001 11:22:40 -0500
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.
--------------8527958B61DDF2A9D0F8DC4B
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

Please subscribe me to the list. Thanks.

--------------8527958B61DDF2A9D0F8DC4B
Content-Type: text/x-vcard; charset=us-ascii;
 name="paulw.vcf"
Content-Transfer-Encoding: 7bit
Content-Description: Card for Paul Wiercienski
Content-Disposition: attachment;
 filename="paulw.vcf"

begin:vcard 
n:Wiercienski;Paul
x-mozilla-html:FALSE
adr:;;;;;;
version:2.1
email;internet:paulw@zucotto.com
x-mozilla-cpt:;0
fn:Paul Wiercienski
end:vcard

--------------8527958B61DDF2A9D0F8DC4B--


Article: 28623
Subject: Re: Virtex-II officially launched
From: Bob Perlman <bob@cambriandesign.com>
Date: Thu, 18 Jan 2001 16:24:36 GMT
Links: << >>  << T >>  << A >>
On Thu, 18 Jan 2001 16:09:26 GMT, Peter Alfke <palfke@earthlink.net>
wrote:

>
>
>Bob Perlman wrote:
>
>> The ASIC impedance updates are very small, too; that's not the
>> problem.  The issue is the manner in which you parallel drivers to
>> achieve adjustable impedance, and how you control the enabling and
>> disabling of those drivers.
>>
>> If, for example, you have 16 mini-drivers, all of strength A, and you
>> adjust impedance by adjusting the number of active drivers, there
>> should be no problem.
>>
>
>That's what we are doing.
>Thanks for the endorsement.

Always happy to shill for a good idea...

Thanks for the answer.

Take care,
Bob Perlman


Article: 28624
Subject: Re: CRC - from long division to XOR, how?
From: "Jamie Sanderson" <jamie@nortelnetworks.com>
Date: Thu, 18 Jan 2001 11:25:25 -0500
Links: << >>  << T >>  << A >>
<eml@riverside-machines.com.NOSPAM> wrote in message
news:3a65869b.10495826@news.dial.pipex.com...
> On Mon, 15 Jan 2001 15:31:29 -0500, "Jamie Sanderson"
> <jamie@nortelnetworks.com> wrote:
>
> >I will continue searching for the elusive app note... Sounds like just
the
> >thing I need.
> >
> >Regards,
> >Jamie
>
> Found it - 'Implementing parallel CRC for reliable high-speed
> point-to-point communication using TAXI', AMD pub.#12572. There's not
> much more than you already know. It doesn't seem to be on the website,
> so I've scanned the relevant 3 pages to:
>
> www.riverside-machines.com/pub/AMD_12572.zip
>
> Have fun -
>
> Evan

Hi again;

Thanks very much for taking the time to scan this in. In the meantime, I
asked around at work, and got an answer (although I'm still not clear on
certain things). As you intimated earlier, it's a matter of working out the
CRC using symbols, instead of an actual number, and getting some big XOR
equations out of it. Fortunately, every time a symbol re-occurs, it cancels
itself out, thanks to the XOR properties.

Cheers,
Jamie





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