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Messages from 28900

Article: 28900
Subject: Re: Synthesizing Virtex Block Memories with Leonardo v1999.1i = Slooow
From: s_clubb@NOSPAMnetcomuk.co.uk (Stuart Clubb)
Date: Sun, 28 Jan 2001 16:41:45 GMT
Links: << >>  << T >>  << A >>
Memory inferencing speed has been improved hugely in release 2000.1b.

I wrote a note which is slightly out of date due to coregen up dates,
but may help in explaining the flow: 

http://www.saros.co.uk/apps_notes/FPGA%20Advantage%20and%20CoreGen%20-%20VHDL.pdf

Cheers
Stuart

On Sat, 27 Jan 2001 15:58:14 +0000, Brian Drummond
<brian@shapes.demon.co.uk> wrote:

>On Thu, 25 Jan 2001 20:32:33 GMT, Newsbrowser@Newsbrowser.com
>(Newsbrowser) wrote:
>
>>This compilation takes a loooooooooooong time. 
>>
>>It stalls at  the compilation of a dual port 2048x12 sram. 
>>
>>I have a feeling that this software is going through creating this
>>memory 1 cell at a time. 
>
>It does, apparently after an earlier version made assumptions about
>inferring memory and could be caught out. I was told, at the time, they
>were going to fix it in a later release, but I'm not up to date on that.
>
>The other way, of course, is to black box the memory and use (Xilinx)
>CoreGen or (other) to instantiate it. When I do this, I have a wrapper
>around the memory (using Renoir) so that except at the lowest level of
>the hierarchy, the design is still technology independent. (And one can
>substitute the VHDL module for the black box, if desired)
>
>One of the guys (Stuart Clubb?) at their UK distributor, Saros
>Technology, http://www.saros.co.uk was preparing an app note about this.
>
>- Brian
>

For Email remove "NOSPAM" from the address

Article: 28901
Subject: Re: Actel's FPGA : A54SX32A
From: Philip Freidin <philip@fliptronics.com>
Date: Sun, 28 Jan 2001 11:28:00 -0800
Links: << >>  << T >>  << A >>
On Sun, 28 Jan 2001 17:23:53 +0100, "jean-francois hasson"
<jfhasson@club-internet.fr> wrote:

>Hi,
>
>I am about to use an Actel A54SX32A in a FBGA144I package. I am interested
>in people having an experience with Actel's FPGAs and the best would be with
>the SX family. I have used up to know either Altera or Xilinx and I have no
>experience with Actel. Are there any known problems with these devices ?

They are one time programmable. Bug fixes, spec changes and
new features will require removing and replacing the chip.

>Anything specific to look at before starting a design ?

Good test benches and thorough simulation

>Thank you in advance for your time and information.
>
>J.F. Hasson
>

Philip Freidin
Fliptronics

Article: 28902
Subject: Re: UK parts
From: sulimma@my-deja.com
Date: Sun, 28 Jan 2001 23:39:54 GMT
Links: << >>  << T >>  << A >>

> The 10k gate Spartan in an 84 pin PLCC (XCS010somethingorotherPC84)
> was in the £5-10 range which is ok. They didn't say anything about
> programming cables. Anybody found them over here ?

Build your own. The schematics are on the Xilinx website.
(Actually, you do not really need most of the parts.

> The SpartanII is a bit cheaper but of course not so easy for
> prototyping.

Do they have small Spartan-II in Stock? I can only get XC2S200 at £20.

Believe me: PQ208 soldering is no big problem.


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Article: 28903
Subject: C2VHDL
From: szolnoki@my-deja.com
Date: Mon, 29 Jan 2001 00:12:16 GMT
Links: << >>  << T >>  << A >>
Where I can get any C2VHDL freeware, trial, or time limited compiler?
(ArtBuilder,SystemC, etc..)

Thank you,
Tibor Szolnoki
szoszo9@freemail.hu


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Article: 28904
Subject: Is it a timing constraint problem?
From: "Neo Wei Thiam" <neowt@cet.st.com.sg>
Date: Mon, 29 Jan 2001 09:21:39 +0800
Links: << >>  << T >>  << A >>
Hi,
    I started to have problems with my 40k gate Spartan FPGA design as I
added more features.  The FPGA is used mainly as a glue logic, performing
address decoding, clock generation, frame resizing and frame
synchronization.
    Initially when the design is relatively small (about 25% resources
ultilised), the problems I faced was mainly due to my error.  However, as I
added the final protion that is frame synchronization (to frame shift 3 PCM
streams) using shift register buffers, I find that these buffers would not
work. The buffers have been functionally verified to be working. The rest of
the design was still working fine. I have tried 2 implementations for the
buffers shift register type and pointer-loaded type, but both failed.  The
output is not the same as the input.
    I wonder if it is due to the higher ultilization of the FPGA of 50% at
this time?  Would adding a timing constraint file help?  I am not familiar
with timing constraint and would like some advice before I take the plunge
into adding this to the design.  If I were to use a larger FPGA that lowers
the ultization from 50% to 25%, would that help?
    I am using Xilinx Foundation 2.1i

Neo Wei Thiam
CET Technology Pte Ltd
Singapore



Article: 28905
Subject: Re: Encryption is supported in new Virtex II but.....
From: widding@my-deja.com
Date: Mon, 29 Jan 2001 01:43:12 GMT
Links: << >>  << T >>  << A >>
In article <gHLb6.149233$f36.5915847@news20.bellglobal.com>,
  "Dan" <daniel.deconinck@sympatico.ca> wrote:
> Why is it that PCB handling during transport and storage becomes much
> more problematic for soldered versus socketed batteries ?

PCBs with components attached are typically shipped in conductive
bags.  So the battery would be subject to discharge through the
resistance intrinsic to the bag.  This resistance is probably on the
order of 100K to 1M ohms.  I must admit, I have not actually measured
the resistance of a typical anti-static bag.


Erik Widding.

---
Birger Engineering, Inc.  -------------------------------  781.481.9233
38 Montvale Ave #260; Stoneham, MA 02180  ------  http://www.birger.com


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Article: 28906
Subject: Q: VIRTEX experience, multipliers
From: "Alex Sherstuk" <sherstuk@iname.com>
Date: Sun, 28 Jan 2001 22:12:28 -0500
Links: << >>  << T >>  << A >>
Dear colleagues,

   What is your experience: what size of VIRTEX (SPARTAN-2) chip is needed
to implement something like 8 multipliers 16*16 bits, 10 ns per multiply?
100 ns per multiply?

Are there any multipliers in standard XILINX library for Virtex? If not,
where they are?

Thanks,
   Alex Sherstuk
     sherstuk@iname.com




Article: 28907
Subject: Re: Is it a timing constraint problem?
From: Peter Alfke <palfke@earthlink.net>
Date: Mon, 29 Jan 2001 04:15:53 GMT
Links: << >>  << T >>  << A >>
Debug your circuit the normal way:
If the function simulates logically, use the timing analyzer to find critical
paths.
If everything simulates ok, but fails physically:

Lower the clock frequency to see whether you have a real timing problem (
unlikely ).
You can also heat the chip, and increase/decrease Vcc, but stay within the
guaranteed limits.

Peter Alfke, Xilinx Applications
=====================================
Neo Wei Thiam wrote:

> Hi,
>     I started to have problems with my 40k gate Spartan FPGA design as I
> added more features.  The FPGA is used mainly as a glue logic, performing
> address decoding, clock generation, frame resizing and frame
> synchronization.
>     Initially when the design is relatively small (about 25% resources
> ultilised), the problems I faced was mainly due to my error.  However, as I
> added the final protion that is frame synchronization (to frame shift 3 PCM
> streams) using shift register buffers, I find that these buffers would not
> work. The buffers have been functionally verified to be working. The rest of
> the design was still working fine. I have tried 2 implementations for the
> buffers shift register type and pointer-loaded type, but both failed.  The
> output is not the same as the input.
>     I wonder if it is due to the higher ultilization of the FPGA of 50% at
> this time?  Would adding a timing constraint file help?  I am not familiar
> with timing constraint and would like some advice before I take the plunge
> into adding this to the design.  If I were to use a larger FPGA that lowers
> the ultization from 50% to 25%, would that help?
>     I am using Xilinx Foundation 2.1i
>
> Neo Wei Thiam
> CET Technology Pte Ltd
> Singapore


Article: 28908
Subject: Re: Is it a timing constraint problem?
From: "Kang Liat Chuan" <kanglc@agilis.st.com.sg>
Date: Mon, 29 Jan 2001 13:55:38 +0800
Links: << >>  << T >>  << A >>
What is your clock frequency? I am not sure about Spartan but I have worked
on 4000xv series. It seems that 50% CLB usage is be ok if your clock is
about 10-20MHz. I was trying to route a design which utilizes 70% CLB with a
50MHz clock on a xc40150xv. Although some of the signals are clocked at
lower frequencies, I specified all the timing constraints in a ucf file.
Still the PAR cannot satisfy all the signal paths.

If you specify the timing constraints, you can see which signals paths are
difficult to route, and then modify your logic to "help" the compiler.

Regards,
LC

Neo Wei Thiam <neowt@cet.st.com.sg> wrote in message
news:3a74c75e$1@news.starhub.net.sg...
> Hi,
>     I started to have problems with my 40k gate Spartan FPGA design as I
> added more features.  The FPGA is used mainly as a glue logic, performing
> address decoding, clock generation, frame resizing and frame
> synchronization.
>     Initially when the design is relatively small (about 25% resources
> ultilised), the problems I faced was mainly due to my error.  However, as
I
> added the final protion that is frame synchronization (to frame shift 3
PCM
> streams) using shift register buffers, I find that these buffers would not
> work. The buffers have been functionally verified to be working. The rest
of
> the design was still working fine. I have tried 2 implementations for the
> buffers shift register type and pointer-loaded type, but both failed.  The
> output is not the same as the input.
>     I wonder if it is due to the higher ultilization of the FPGA of 50% at
> this time?  Would adding a timing constraint file help?  I am not familiar
> with timing constraint and would like some advice before I take the plunge
> into adding this to the design.  If I were to use a larger FPGA that
lowers
> the ultization from 50% to 25%, would that help?
>     I am using Xilinx Foundation 2.1i
>
> Neo Wei Thiam
> CET Technology Pte Ltd
> Singapore
>
>



Article: 28909
Subject: compatible issue
From: "Nelson Wang" <info@corelink.com.tw>
Date: Mon, 29 Jan 2001 16:30:30 +0800
Links: << >>  << T >>  << A >>
Dose there exist any issue to license a RTL IP which declared the core was
object code compatible with some other existing popular core, such as TI's
C50  or AD2181 DSP. And, who will be in charge of the liability of lawsuit
If we get into production by using the compatible IP? me or the IP vendor?

Nelson Wang
nelsonw@corelink.com.tw



Article: 28910
Subject: Re: UK parts
From: "Martin.J Thompson" <Martin.J.Thompson@trw.com>
Date: Mon, 29 Jan 2001 03:48:03 -0500
Links: << >>  << T >>  << A >>
>
>I seem to be having difficulty finding an online supplier for one off
>quantities of Xilinx FPGA/CPLDs in the UK. Specifically Spartans. And
>preferebly at =A3few like their press release implies !
>
>I've found are the XC95xxx on RS and that's about it.
>
>Xilinx's site suggests two online suppliers, one of which's page
>doesn't seem to work and the other only delivers in the U.S.
>
>Any suggestions ?
>
>Or another make with free development tools (but not Actel because
>their desktop SW didn't agree with me) ?
>

Altera ACEX 1K ? Pretty cheap and available in 1-2 weeks last time I asked =
from Impact Memec in the UK.  http://www.impact.uk.memec.com/=20

Cheers,
Martin


--=20
Martin Thompson BEng(Hons) CEng MIEE
TRW Automotive Advanced Product Development,        =20
Stratford Road, Solihull, B90 4GW. UK
Tel: +44 (0)121-627-3569=20
mailto:martin.j.thompson@trw.com




 Sent via Deja.com http://www.deja.com/
 Before you buy.

Article: 28911
Subject: Re: XtremeDSP seminar comments -- Virtex-II 4xPowerPC chip multiprocessor!
From: kolja@prowokulta.org
Date: Mon, 29 Jan 2001 09:52:58 GMT
Links: << >>  << T >>  << A >>
In article <G9kc6.1332$23.181745@dfiatx1-snr1.gtei.net>,
  "Jan Gray" <jsgray@acm.org> wrote:

> 6. Erich Goetting, Xilinx VP, revealed the forthcoming Virtex-II with
> PowerPC and multiple 3.125 Gbps links will be called Virtex-II Pro.
>
> 7. The Virtex-II Pro's Conexant-licensed 3.125 Gbps links (nice eye
> diagrams) are driven at 32-bits at 78 MHz. That looks easy enough to
> interface to.

Did they give a rough timeline, when the Virtex-II Pro will be released?

Kolja Sulimma


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Article: 28912
Subject: set/reset
From: noelia <design17rojo@yahoo.es>
Date: Mon, 29 Jan 2001 02:00:23 -0800
Links: << >>  << T >>  << A >>
I have a sequential design in the
Xilinx design manager. In it I have
a reset and after mapping a warning appears telling me I must used the
global set/reset by mean the STARTUP component. How can I do to use this
line global set/reset without introducing this component in the VHDL code?

Article: 28913
Subject: Re: grey code counters
From: Nial Stewart <nials@sqf.hp.com>
Date: Mon, 29 Jan 2001 14:04:26 +0000
Links: << >>  << T >>  << A >>
Rick Collins wrote:
> 
> Nial Stewart wrote:
> >
> > Peter Alfke wrote:
> > >
> > > Theoretically correct,
> > > but in reality it depends on the complexity of the Grey-control logic.
> > > In the design I am touting, there is actually a binary counter enclosed.
> > > Bye-bye power saving.
> > >
> > > Peter Alfke
> > >
> > > Theron Hicks wrote:
> > >
> > > > Also, the switching noise may be substantially less as only one bit is changing
> > > > at a time.
> > > >
> >
> > But it could be a usefule technique if driving the address
> > lines of a bank of external parrallel memory devices.
> >
> > Nial.
> 
> I don't know that the power savings is tremendous. On the average a
> binary counter has two bits changing on each clock cycle. The lsb
> changes on every cycle, then next bit changes on every other, the next
> every fourth,... This series approaches 2 as the number of bits gets
> large. The Gray code counter has one bit changing on each clock. So the
> difference is a factor of two, useful, but not huge.

Except where you're driving the address bus of a parralel bank of say
4 128K*8 Rams. 

If you had an instance where the address rolled over from 0 to 2^17
you'd be driving a load of 72 pins from 0 -> 1. This could potentially
give you bad ground bounce problems.

If you were driving the address bus with a grey code counter (and it's
ram so you may as well) you'll always only be driving a load of 4 
inputs on each address transition.

It'll not help with power consumption, but might help but EMC/grounding 
issues.


Nial.

Article: 28914
Subject: Xilinx NODELAY attribute question
From: Jakab Tanko <jtanko@ics-ltd.com>
Date: Mon, 29 Jan 2001 14:41:10 GMT
Links: << >>  << T >>  << A >>
Hi all,

I run into a little problem trying to control the setup time of an input 
pin to an XC4044XLA
device . Here it goes:
I want to specify a NODELAY attribute to an input pin to minimize the 
setup time.
I want to do it in the UCF file. I used the syntax : NET "DATA_IN<0>" 
NODELAY; and it was
ignored by the software (Alliance 3.1)?. When I look in the Constraints 
Editor
of the Alliance, the delay constraint shown is the same as my clock 
period instead of the
zero I was expecting with the NODELAY constraint..
I was able to control the setup time to the same pin before with the line :
NET "DATA_IN<0>" OFFSET = IN 5 ns BEFORE "SAMPLE_CLK"; in the UCF file.
Could anyone please tell me how to get this working?

Thanks,
jakab


Article: 28915
Subject: Re: Xilinx NODELAY attribute question
From: "Brendan Lynskey" <brendan.lynskey@pace.co.uk>
Date: Mon, 29 Jan 2001 15:20:27 -0000
Links: << >>  << T >>  << A >>

I think the 'NODELAY' attribute refers to the 'delay element' in the IOBs;
not to a *value* of routing delay. By default synthesizers include this in
the signal path.

"Jakab Tanko" <jtanko@ics-ltd.com> wrote in message
news:3A758269.3000507@ics-ltd.com...
> Hi all,
>
> I run into a little problem trying to control the setup time of an input
> pin to an XC4044XLA
> device . Here it goes:
> I want to specify a NODELAY attribute to an input pin to minimize the
> setup time.
> I want to do it in the UCF file. I used the syntax : NET "DATA_IN<0>"
> NODELAY; and it was
> ignored by the software (Alliance 3.1)?. When I look in the Constraints
> Editor
> of the Alliance, the delay constraint shown is the same as my clock
> period instead of the
> zero I was expecting with the NODELAY constraint..
> I was able to control the setup time to the same pin before with the line
:
> NET "DATA_IN<0>" OFFSET = IN 5 ns BEFORE "SAMPLE_CLK"; in the UCF file.
> Could anyone please tell me how to get this working?
>
> Thanks,
> jakab
>



Article: 28916
Subject: Re: Is it a timing constraint problem?
From: Ray Andraka <ray@andraka.com>
Date: Mon, 29 Jan 2001 15:33:16 GMT
Links: << >>  << T >>  << A >>
FLoorplanning and designing to the architecture will let yo do much better. 
I've 
done a large number of 4000 and derivative designs that are more than 85% full
and yet
run at several times the 10-20MHz clock you are citing.  For example, my HDTV
descrambler
core is guaranteed to run at 75 MHz in any of the 4000XV parts.  In the small
parts, it fills 
most of the device.  The data sheet for that design is available on my website.

Kang Liat Chuan wrote:
> 
> What is your clock frequency? I am not sure about Spartan but I have worked
> on 4000xv series. It seems that 50% CLB usage is be ok if your clock is
> about 10-20MHz. I was trying to route a design which utilizes 70% CLB with a
> 50MHz clock on a xc40150xv. Although some of the signals are clocked at
> lower frequencies, I specified all the timing constraints in a ucf file.
> Still the PAR cannot satisfy all the signal paths.
> 
> If you specify the timing constraints, you can see which signals paths are
> difficult to route, and then modify your logic to "help" the compiler.
> 
> Regards,
> LC
> 
> Neo Wei Thiam <neowt@cet.st.com.sg> wrote in message
> news:3a74c75e$1@news.starhub.net.sg...
> > Hi,
> >     I started to have problems with my 40k gate Spartan FPGA design as I
> > added more features.  The FPGA is used mainly as a glue logic, performing
> > address decoding, clock generation, frame resizing and frame
> > synchronization.
> >     Initially when the design is relatively small (about 25% resources
> > ultilised), the problems I faced was mainly due to my error.  However, as
> I
> > added the final protion that is frame synchronization (to frame shift 3
> PCM
> > streams) using shift register buffers, I find that these buffers would not
> > work. The buffers have been functionally verified to be working. The rest
> of
> > the design was still working fine. I have tried 2 implementations for the
> > buffers shift register type and pointer-loaded type, but both failed.  The
> > output is not the same as the input.
> >     I wonder if it is due to the higher ultilization of the FPGA of 50% at
> > this time?  Would adding a timing constraint file help?  I am not familiar
> > with timing constraint and would like some advice before I take the plunge
> > into adding this to the design.  If I were to use a larger FPGA that
> lowers
> > the ultization from 50% to 25%, would that help?
> >     I am using Xilinx Foundation 2.1i
> >
> > Neo Wei Thiam
> > CET Technology Pte Ltd
> > Singapore
> >
> >

-- 
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com  or http://www.fpga-guru.com

Article: 28917
Subject: Re: Synthesizing Virtex Block Memories with Leonardo v1999.1i = Slooow
From: Newsbrowser@Newsbrowser.com (Newsbrowser)
Date: Mon, 29 Jan 2001 16:18:59 GMT
Links: << >>  << T >>  << A >>
On Sun, 28 Jan 2001 16:41:45 GMT, s_clubb@NOSPAMnetcomuk.co.uk (Stuart
Clubb) wrote:

>Memory inferencing speed has been improved hugely in release 2000.1b.
>
>I wrote a note which is slightly out of date due to coregen up dates,
>but may help in explaining the flow: 
>
>http://www.saros.co.uk/apps_notes/FPGA%20Advantage%20and%20CoreGen%20-%20VHDL.pdf
>
>Cheers
>Stuart
>
>On Sat, 27 Jan 2001 15:58:14 +0000, Brian Drummond
><brian@shapes.demon.co.uk> wrote:
>
>>On Thu, 25 Jan 2001 20:32:33 GMT, Newsbrowser@Newsbrowser.com
>>(Newsbrowser) wrote:
>>
>>>This compilation takes a loooooooooooong time. 
>>>
>>>It stalls at  the compilation of a dual port 2048x12 sram. 
>>>
>>>I have a feeling that this software is going through creating this
>>>memory 1 cell at a time. 
>>
>>It does, apparently after an earlier version made assumptions about
>>inferring memory and could be caught out. I was told, at the time, they
>>were going to fix it in a later release, but I'm not up to date on that.
>>
>>The other way, of course, is to black box the memory and use (Xilinx)
>>CoreGen or (other) to instantiate it. When I do this, I have a wrapper
>>around the memory (using Renoir) so that except at the lowest level of
>>the hierarchy, the design is still technology independent. (And one can
>>substitute the VHDL module for the black box, if desired)
>>
>>One of the guys (Stuart Clubb?) at their UK distributor, Saros
>>Technology, http://www.saros.co.uk was preparing an app note about this.
>>
>>- Brian
>>
>
>For Email remove "NOSPAM" from the address

thanks for the info 


Ralph Watson 
Return Email Address is: 
ralphwat dot home at excite dot com 
just type the address in like it should look like

Article: 28918
Subject: Re: Foundation - Source Constraints
From: David Hawke <dhawke@xilinx.com>
Date: Mon, 29 Jan 2001 16:33:03 +0000
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.
--------------A71CA6A49086A416C0A5EE35
Content-Type: text/html; charset=us-ascii
Content-Transfer-Encoding: 7bit

<!doctype html public "-//w3c//dtd html 4.0 transitional//en">
<html>
Steve,
<p>Foundation will not generate those constraints for you. If you have
modules in the design that were compiled using any other Synthesiser you
will see an NCF file. I guess that somewhere along the line the NCF file
has been produced.
<p>If you do not want them then delete the NCF.
<p>Also, if you compiled one module through Synopsys then this will generate
constraints that live in the EDIF...If this is the case, then simply recompile
with Export Timing Constraints turned off..
<p>Dave
<p>steve@sk-tech.com wrote:
<blockquote TYPE=CITE>Hello all,
<p>I have a existing design that has been going through the design flow
<br>just fine for months. All of a sudden the placer and router scores
<br>went through the roof! To the point where my design won't compile.
<br>When I look at my UCF file with the Constraint's Editor I see a tab
at
<br>the bottom called "Source Constraints". I click on that tab and look
<br>at the contents in the window. I see several TIMESPEC statements that
<br>I have not added and they are causing my design to not compile
<br>properly. the TIMESPECs added were things like PADS to PADS and PADS
<br>to FFS, etc. The values they are using are too fast. I do not know
why
<br>this started and how to get rid of them. Some things in the design
are
<br>not constrained and that is intended. It seems like the tools are
<br>trying to force 100% coverage by added these TIMESPECs??? I have all
<br>the most recent Service Patches installed. Any clues would be most
<br>appreciated.
<p>Thank you,
<br>Steve
<br>S&amp;K Electronics</blockquote>
</html>

--------------A71CA6A49086A416C0A5EE35
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--------------A71CA6A49086A416C0A5EE35--


Article: 28919
Subject: Re: set/reset
From: Andy Peters <"apeters <"@> noao [.] edu>
Date: Mon, 29 Jan 2001 09:50:19 -0700
Links: << >>  << T >>  << A >>
noelia wrote:
> 
> I have a sequential design in the
> Xilinx design manager. In it I have
> a reset and after mapping a warning appears telling me I must used the
> global set/reset by mean the STARTUP component. How can I do to use this
> line global set/reset without introducing this component in the VHDL code?

Make sure ALL of the flops in your design use the same reset net, and
STARTUP will be inferred by the tools.

-a

Article: 28920
Subject: Re: looping and ranges
From: Mark Curry <mcurry@ti.cat.com>
Date: Mon, 29 Jan 2001 09:36:43 -0800
Links: << >>  << T >>  << A >>


Rick Collins wrote:
> 
> Stephen Williams wrote:
> >
> > always @(bar)
> >   for (j=1; j<14; j=j+1)
> >     foo[j] <= bar[423-((13-j)*8):423-((13-j)*8)-7];
> >
> > Nope.
> >
> > Part selects (that is, ranges of bits) must have constant indices in
> > Verilog. Verilog 200? relaxes this constraint. An in addition, you
> > cannot address single bits of vector arrays. Verilog 200? relaxes this
> > restriction as well.
> >
> > However, for what you want to do, you can probably make more use of
> > parameter expressions to make the unrolled version more manageable.
> 
> Thanks. I ended up using Paul's suggestion of using the loop index to
> select individual bits of BAR and concatenating 8 of them into a byte.
> Works ok and is a compromise of readability.
> 
> But now I want to do the same thing on the receive side where we need to
> use the bit vector on the left side and the byte vector on the right. So
> how do I do that without driving the compiler nuts?
> 
> output [53*8-1:0] bar;
> 
> reg[7:0] foo[1:13];
> 
> always @(bar)
>   for (j=1; j<14; j=j+1)
>      bar[423-((13-j)*8):423-((13-j)*8)-7] <= foo[j];
> 
> I can't do this, and I can't concatenate BAR into a byte. So am I only
> left with the original method of individual explicit byte assignments?
> 

Another way of doing both directions is to use shifts and masks.
So, for making a large vector out of an array:

always @( ... ) /* See below for comments on this! */
begin
  bar = 0; 
   for( j = 13; j > 0; j = j - 1 )
   begin
     bar = bar | foo[ j ];   /* Important - don't use <= !!!! */
     if( j != 1 )
       bar = bar << 8;
   end
end

For the other direction:
always @( bar )
  for( j = 1; j < 14; j = j + 1 )
    foo[ j ] = bar >> ( ( j - 1 ) * 8 );

Now for the first case sensitivity list.  You've got a problem
there.  You mistyped in your question.  You probably wanted
always @( foo ) not bar.  Problem is verilog doesn't like
an array as part of your sensitivity list. So, unless
you can make bar a bank of flops ( hence the sensitivity list is
@( posedge clk ), you're stuck.

That last point's really a stickler.  We've tried doing things
like this in our code - using the array notation for easier
indexing into cells like you're doing can be really convenient.
But alas, we usually end up "blasting" the arrays into
long wires for the whole process.  

We've seen all the wonderful things like this that should
be fixed in verilog 2000.  We're just waiting for 
someone to actually implement them!

Regards,

Mark


-- 
Mark Curry           
mcurry@ti.cat.com  Remove the animal from the domain to reply.

Article: 28921
Subject: Xilinx JEDEC files to SVF format
From: Mikko <mheikker@cc.hut.fi>
Date: 29 Jan 2001 18:18:43 GMT
Links: << >>  << T >>  << A >>
Does anyone know how to create .scf file from a jedec (.jed) file generated by
Xilinx Foundation program? I noticed there is an EZTag-program by Xilinx, but 
it seems quite old (newest version of July, 1998) and according to its manual
it supports only families XC9536, XC95108 and XC95216. And it seems to be
designed for Win95.

Regards,
Mikko Heikkerö,
mheikker@cc.hut.fi
-- 

Article: 28922
Subject: Re: Xilinx JEDEC files to SVF format
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Mon, 29 Jan 2001 21:31:30 +0000
Links: << >>  << T >>  << A >>


Mikko wrote:

> Does anyone know how to create .scf file from a jedec (.jed) file generated by
> Xilinx Foundation program? I noticed there is an EZTag-program by Xilinx, but
> it seems quite old (newest version of July, 1998) and according to its manual
> it supports only families XC9536, XC95108 and XC95216. And it seems to be
> designed for Win95.
>
> Regards,
> Mikko Heikkerö,
> mheikker@cc.hut.fi
> --

EZTag died off some time ago & has been replaced by a thing called the ``JTAG
Programmer'' which can be downloaded as part of the free WebPack tools. It can can
handle all the XC95K devices [as well as being able to load those FPGAs that are
JTAG loadable] and generate SVF files.

JTAGProgrammer runs under WinNT but not, I think, under Win95/98/ME [certainly the
1.5i version didn't & I haven't tried since then].



Article: 28923
Subject: Re: Encryption is supported in new Virtex II but.....
From: z80@ds2.com (Peter)
Date: Mon, 29 Jan 2001 22:23:21 +0000
Links: << >>  << T >>  << A >>

>But: There is a self-discharge mechanism that is the real limitation.
>Good 3-V Lithium batteries have a shelf life of 15 years or more.

This is a much bigger issue than it first appears. I have designed a
number of very low power products powered by lithium watch-type cells,
did a lot of evaluations of different cells, and it was amazing to
find how bad some cells were. One make (European) had a shelf life
consistently of about 1 year (to <20% capacity), the best Japanese
makes were probably >10 years, but "bad batches" happen right across
the board. 

I would be very unhappy relying on a shelf life of 10-15 years for a
critical application, e.g. where loss of battery power would make a
product *permanently* (i.e. even if the battery is replaced)
non-functional. All you need is a bad batch of cells and maybe 5 years
later you get a whole lot of extremely unhappy customers...


Peter.
--
Return address is invalid to help stop junk mail.
E-mail replies to zX80@digiYserve.com but remove the X and the Y.
Please do NOT copy usenet posts to email - it is NOT necessary.

Article: 28924
Subject: Re: Xilinx JEDEC files to SVF format
From: Greg Neff <gregneff@my-deja.com>
Date: Mon, 29 Jan 2001 23:00:58 GMT
Links: << >>  << T >>  << A >>
In article <3A75E132.DB7A9BD1@algor.co.uk>,
  Rick Filipkiewicz <rick@algor.co.uk> wrote:
>
>
> Mikko wrote:
>
> > Does anyone know how to create .scf file from a jedec (.jed) file
generated by
> > Xilinx Foundation program? I noticed there is an EZTag-program by
Xilinx, but
> > it seems quite old (newest version of July, 1998) and according to
its manual
> > it supports only families XC9536, XC95108 and XC95216. And it seems
to be
> > designed for Win95.
> >
> > Regards,
> > Mikko Heikkerö,
> > mheikker@cc.hut.fi
> > --
>
> EZTag died off some time ago & has been replaced by a thing called
the ``JTAG
> Programmer'' which can be downloaded as part of the free WebPack
tools. It can can
> handle all the XC95K devices [as well as being able to load those
FPGAs that are
> JTAG loadable] and generate SVF files.
>
> JTAGProgrammer runs under WinNT but not, I think, under Win95/98/ME
[certainly the
> 1.5i version didn't & I haven't tried since then].
>
>

The WebPack JTAG programmer runs OK on our Win98 machines (Win98, OTOH,
is another matter...):

http://www.xilinx.com/products/software/we_detail.htm#dpt

--
Greg Neff
VP Engineering
*Microsym* Computers Inc.
greg@guesswhichwordgoeshere.com


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