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Messages from 29425

Article: 29425
Subject: Re: 5 Clocks in a spartan-II
From: Kent Orthner <korthner@hotmail.nospam.com>
Date: 21 Feb 2001 09:57:03 +0900
Links: << >>  << T >>  << A >>

Thanks for the response, Chris.


chris@cgschneider.com (Chris G. Schneider) writes:
> Clock skew may be a problem. One time I used a secondary clock for
> a clock with 39 MHz (without intension) and it worked with no problems.
> There were a lot of really large counters driven by this "clock" net.

Well, I was hoping for "Don't be silly, there won't be a problem", 
but if you had lot of really large counters, then that makes me 
feel a bit better.

> As far as I remember, trace calculates the clock skew as well.

That's a good thing.  So at least I'll know if I have problems.

> We do it that way, too. This saves a lot of time. It just reqiures good 
> communication between FPGA and PCB designers.

In this case, it looks like I'm going to be both.  <grin>


> You did not mention your application, but the four nearly identical
> clock just raise the question whether you can combine them. External
> phase differnce may be comensated by using the DLLs, but ask the experts
> on this subject. 

Sadly, I don't see how.
The 52MHz clock is the system clock coming from the motherboard, and 
driving everything in the system.  So I have no control over that.

The 77.76MHz clock is for SONEt . . one is my transmit clock, and 
one is my receive clock, multiplied by two ports.

The receive clock will be locked to the rx data, so I can't 
control that, and the Tx clock will be locked to the rx data 
or synthesized from a reference clock.  

> One other thig is that 52Mhz * 1.5 = 78 MHz approx 
> 77.76 MHz. Can you derive the 52 MHz from 77.76 MHz? Or why don't you 
> use 77.76 MHz for your processor interface?  

The processor is a special-purpose network processor that connects 
to the switch fabric using the 52MHz system clock.  So I don't have 
a lot of flexibility as far as clocking is concerned.

-Kent

Article: 29426
Subject: Virtex E:Sample price
From: "Neo WT" <neowt@cet.st.com.sg>
Date: Tue, 20 Feb 2001 17:30:47 -0800
Links: << >>  << T >>  << A >>
Can anyone advice me of a reasonable sample price for XCV1000E-8HQ240?  I was quoted about US$1900 per piece for 5 pcs.  Is this the market rate?

Neo WT

Article: 29427
Subject: Re: Configuration of FPGA using SPROM
From: radhika <radhikamurahari@yahoo.co.uk>
Date: Tue, 20 Feb 2001 17:57:14 -0800
Links: << >>  << T >>  << A >>
hi chris!
 yeah even we feel it is high time we replace the chip.I have checked the connections a number of times and found no error.So we are plannig to ahead and do the entire thing beginning from the scratch.If you have done the configuration using sprom , could you please send the schematic and the control signal details to my email given above or if u could give me ur mail id i might send u my schematic in attachment.
thank you for all the help
radhika

Article: 29428
Subject: Re: Virtex E:Sample price
From: Dave Vanden Bout <devb@xess.com>
Date: Tue, 20 Feb 2001 22:30:07 -0500
Links: << >>  << T >>  << A >>
> Can anyone advice me of a reasonable sample price for XCV1000E-8HQ240?  I was quoted about US$1900 per piece for 5 pcs.  Is this the market rate?

I just checked at http://www.avnetmarshall.com/dynamic/search and the 1-25 piece price was listed as $2031 so it looks like your price is not
outrageous.


--
|| Dr. Dave Van den Bout   XESS Corp.               (919) 387-0076 ||
|| devb@xess.com           2608 Sweetgum Dr.        (800) 549-9377 ||
|| http://www.xess.com     Apex, NC 27502 USA   FAX:(919) 387-1302 ||



Article: 29429
Subject: Re: Virtex E:Sample price
From: pratipm@hotmail.com (Pratip Mukherjee)
Date: Wed, 21 Feb 2001 03:39:04 GMT
Links: << >>  << T >>  << A >>
According to www.findchips.com, Insight should be charging you $1847.000 for 1 
to 20 pcs.

In article <ee6fc19.-1@WebX.sUN8CHnE>, "Neo WT" <neowt@cet.st.com.sg> wrote:
>Can anyone advice me of a reasonable sample price for XCV1000E-8HQ240?  I was
> quoted about US$1900 per piece for 5 pcs.  Is this the market rate?
>
>Neo WT

Article: 29430
Subject: Xilinx CoreGen problem.
From: "Sang-hee Lee" <shlee@impresstek.co.kr>
Date: Wed, 21 Feb 2001 14:02:20 +0900
Links: << >>  << T >>  << A >>
Hi, all.

I'm using Xilinx core generator
to use the dual-port RAM of virtex-1000 in my design.
However, the generated EDN file includes the followings:
  (net (rename N2 "addr<0>")
  ...
  (net (rename N2 "clka")
  ...

As shown above, the name N2 is duplicated.
When I load the EDN file in some other projects,
error messages saying that appear.
Could you confirm it is OK ?

Alan




Article: 29431
Subject: Re: Spartan II power
From: Rick Collins <spamgoeshere4@yahoo.com>
Date: Wed, 21 Feb 2001 01:21:21 -0500
Links: << >>  << T >>  << A >>
Paul Smith wrote:
> 
> How are people handling the large (500 mA) startup current for a Spartan
> II device?
> The data sheet implies this can be reduced by ramping the power supply
> up over 50 mS, but doesn't say what the startup current will be reduced
> to.  Is anyone doing this?
> 
> Also, maybe I'm not looking in the right place, but I can't find
> anything about how to estimate the power needed for a running device.
> There must be some algorithm that lets one estimate this based on clock
> frequency and percentage of device switching?
> 
> Paul Smith
> Indiana University Physics

This is a question that has appeared here several times already. The
Xilinx people can give you a lot of data, which they may have done
offline as they did with me. But none of it helps me to get around the
500 mA requirement. The new board I am building will have 5 FPGAs on a
very small board. To have to supply 2.5 Amps, even for a brief moment at
startup, is a very hard thing to do on this board since it makes it's
own 2.5 volts. 

I never got the info on what the Spartan II would do if you could only
supply 400 mA, for example. They will tell you that different Vdd ramp
speeds require different supply currents. But they do not have any hard
data to tell you that a specific ramp rate will only require X mA of
supply current. 

But then I keep hearing how you can't get them anyway, so how does it
matter what current they draw?


-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX
URL http://www.arius.com

Article: 29432
Subject: Re: Integrated Conf.EPROM / smaller Footprints?
From: "Thorsten Bunte" <t.bunte@beckhoff.de>
Date: Wed, 21 Feb 2001 08:36:44 +0100
Links: << >>  << T >>  << A >>
Hi,

A smaller footprint of config devices would be very nice. The EPC1441TC32 is
as big as the EPF6016AFC100 we use. Altera told us that it is impossible to
go to a smaller package due to the die size of the memory device.

Integrating the config memory does make sense if You use an FPGA as a stand
alone device.

In some of our case we use a C and load the configuration through the C.
So, there is no need for a prom. We do not want to buy memory which we do
not need.

If You like to save the space for a prom use an FPGA of Actel. They use
antifuse tech. Problem is that you can program it only once.

Thorsten

"C.Schlehaus" <carlhermann.schlehaus@t-online.de> schrieb im Newsbeitrag
news:96d1mr$b78$03$1@news.t-online.com...
> Hi,
> as the FPGA chip itself is permanently shrinking (still have
> designs with a RQFP240 with less capacity than my BGA in newer
> designs), I'd like to have similar trends by Conf-Eproms.
> Unfortunately the only changes are EPROMS with more capacity
> to fit the needs of greater devices, but no smaller footprints.
> Comparing a Fine-Line BGA 256Pin and the Conf.EPROM, the Eprom
> is too great IMHO. I'd like to have a conf.EPROM in SO8 or even
> better being integrated on Chip in the FPGA (no more external
> devices).
> As e.g. the EPC2 of ALTERA are programmable by JTAG, they are
> ISP and thus there seems to be no need for cases which could be
> put into separate programmers.
>
> What's Your opinion about this?
>
> CU, Carlhermann
>
>



Article: 29433
Subject: Re: Altera process change....
From: Nial Stewart <nials@sqf.hp.com>
Date: Wed, 21 Feb 2001 09:14:18 +0000
Links: << >>  << T >>  << A >>
"Joe C." wrote:
> 
> Arcane question, but...
> Has anyone had trouble with Altera's 10K50V devices following the
> process change from E50 to F51 over the course of last year?
> We have 10-for-10 bad pcbs that have F51s, that work with E50s.
> They went from 3 to 4-layer metal, same fabs/geometry.
> Thanks!
> Joe Curren

Joe,

Do the devices that fail completely fail, or periodically?

A few years ago I was working on a system that had to be 
enviromentally tested to (I think) -20 Deg C.

After Xilinx did a process change on the devices we were
using some of them started failing when powerd up at -20.
It turned out that the dimensions of the internal pullups
had changed and the 10K resistors we were using on the mode
pins weren't pulling low strongly enough, we had to go to 
4K7 for reliable operation.

This was from a geometry change though, but something to
bear in mind for the future.


Nial.

Article: 29434
Subject: Short Course Announcement
From: Sally Verkaik <s.verkaik@ic.ac.uk>
Date: Wed, 21 Feb 2001 10:11:27 +0000
Links: << >>  << T >>  << A >>

--------------64EB7FA30C34399AB7DD011F
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

Advances in Digital Signal Processing
12 - 16 March 2001 @ Imperial College, London, UK

Advances in VLSI technology have facilitated the introduction of fast
and specialised Digital Signal Processors (DSP) and associated
Integrated Circuits, which can be used in a wide range of communication
and multimedia applications.  This two parts modular course has been
developed to provide engineers a "hands-on" introduction to the
fundamentals of DSP and with a broad view of some of the key issues
involved in DSP and its application in modern communication systems,
focussing on key topic areas for DSP, namely speech, image and video
processing and FPGAs.  Presented  by leading experts from Imperial
College.

We would be most grateful if you could pass this information on to your
colleagues who might be interested.

Further details from:  Ulrika Wernmark,  Centre for Continuing
Education, Imperial College, Room 526 Sherfield Building, Exhibition
Road, London SW7 2AZ, UK.

Tel: +44(0)20 7594 6886;  Fax: +44(0)20 7594 6883;
Email: u.wernmark@ic.ac.uk,

http://www.ad.ic.ac.uk/cpd/dsp.htm

--------------64EB7FA30C34399AB7DD011F
Content-Type: text/html; charset=us-ascii
Content-Transfer-Encoding: 7bit

<HTML>
<B><FONT SIZE=+1>Advances in Digital Signal Processing</FONT></B>
<BR><B><FONT SIZE=+1>12 - 16 March 2001 @ Imperial College, London, UK</FONT></B>

<P>Advances in VLSI technology have facilitated the introduction of fast
and specialised Digital Signal Processors (DSP) and associated Integrated
Circuits, which can be used in a wide range of communication and multimedia
applications.&nbsp; This two parts modular course has been developed to
provide engineers a "hands-on" introduction to the fundamentals of DSP
and with a broad view of some of the key issues involved in DSP and its
application in modern communication systems, focussing on key topic areas
for DSP, namely speech, image and video processing and FPGAs.&nbsp; Presented&nbsp;
by leading experts from Imperial College.

<P>We would be most grateful if you could pass this information on to your
colleagues who might be interested.

<P>Further details from:&nbsp; Ulrika Wernmark,&nbsp; Centre for Continuing
Education, Imperial College, Room 526 Sherfield Building, Exhibition Road,
London SW7 2AZ, UK.

<P>Tel: +44(0)20 7594 6886;&nbsp; Fax: +44(0)20 7594 6883;
<BR>Email: u.wernmark@ic.ac.uk,<FONT SIZE=+1></FONT>

<P><FONT SIZE=+1><A HREF="http://www.ad.ic.ac.uk/cpd/dsp.htm">http://www.ad.ic.ac.uk/cpd/dsp.htm</A></FONT></HTML>

--------------64EB7FA30C34399AB7DD011F--


Article: 29435
Subject: clock divider by 1.5
From: Goran <goran_metlic@yahoo.com>
Date: Wed, 21 Feb 2001 02:25:12 -0800
Links: << >>  << T >>  << A >>
Im beginer in vhdl and i need to create a clock divider by 1.5.I have found such one in edn magazine (on the web) but it didnt help me.Does someone have better idea then the one in edn magsine.

If someone wants to look at the design in edn : http://www.ednmag.com/ednmag/reg/1996/101096/21di_05.htm

Article: 29436
Subject: Re: RSA on FPGA
From: "Bjrn B Larsen" <bjorn.b.larsen@fysel.ntnu.no>
Date: Wed, 21 Feb 2001 14:57:32 +0100
Links: << >>  << T >>  << A >>
"ajd" <ajadu76@hotmail.com> wrote in message
news:3a923ef7$1@news.star.co.uk...
>
> Anyone ever done it? Which bits of the algorithm were implemented?
>
> Andrew
>

Yes.

3 student groups made one such beast each. (3 devices.) One of the groups
even won the Mentor 200 HDL Design Contest with their design.

There vere more groups from around the world participating in the contest,
so there should be some solutions or attemted solutions out there.



Bjrn BL.
Associate Professor
NTNU



Article: 29437
Subject: Second Source For ALTERA EPC1 ?
From: "Tom" <te@wiese.de>
Date: Wed, 21 Feb 2001 15:43:34 -0000
Links: << >>  << T >>  << A >>
Does someone know a second source for the ALTERA EPC1 configuration PROM ?

-Tom




Article: 29438
Subject: Programming Altera CPLD?
From: "Jon S." <ads@begone.com>
Date: 21 Feb 2001 10:07:03 -0600
Links: << >>  << T >>  << A >>
Could someone tell me how to program a MAX7032 (which does not have JTAG
capability), i.e. what signals to apply where, when?  Altera's documentation
seems to only discuss JTAG programming.



Article: 29439
Subject: Xilinx tools: RLOC hierarchy with HDL design?
From: Reinoud <dus@wanabe.nl>
Date: Wed, 21 Feb 2001 17:17:04 +0100
Links: << >>  << T >>  << A >>

Hi,

Is it possible to use a hierachy of RLOC constraints for a HDL
(Verilog) design with instantiated primitives?

The documentation indicates that it is possible to do RLOC placement
not only on primitives, but also on sets of primitives, in a nicely
hierarchical fashion (adding relative positions down the hierarchy). 
I don't see how to make this work with UCF file statements for a
Verilog module hierarchy, though.  Is there a way, or does this only
work with library macros or schematics?

Thanks!

- Reinoud

----

Spam goes to wanabe, mail to wanadoo.

Article: 29440
Subject: Clocks
From: Frode Vatvedt Fjeld <frodef@acm.org>
Date: 21 Feb 2001 17:24:33 +0100
Links: << >>  << T >>  << A >>
Having played around a bit with VHDL programming for FPGAs, the time
has comed to try it out on real devices. Not being much of an
electronics engineer, my first obstacle is how do I generate a clock
signal? I have set up some simple clocks with an RC config and
inverters, but I'm not confident this would work well for the MHz
range.

So, I'm looking for pointers to information on designing clock
generators (suitable for driving FPGAs). What do you all use?

Thanks,
-- 
Frode Vatvedt Fjeld

Article: 29441
Subject: Re: Infering DPRAM with both outputs
From: "Jaan Sirp" <jaan.sirp@mail.ee>
Date: Wed, 21 Feb 2001 09:30:12 -0800
Links: << >>  << T >>  << A >>
ram16x1d Ram (
		.we (we),
		.d (di),
		.wclk (clk),
		.a0 (waddr[0]),
		.a1 (waddr[1]),
		.a2 (waddr[2]),
		.a3 (waddr[3]),
		.dpra0 (raddr[0]),
		.dpra1 (raddr[1]),
		.dpra2 (raddr[2]),
		.dpra3 (raddr[3]),
		.dpo (do),
		.spo (do_at_wa)
		);

>I'm using Foundation Express, may be Leonardo Spectrum haven't ram16x1d lybrary component.

The question refers to dual ported memory inferring using
Leonardo Spectrum for synthesis and targeting Xilinx' Spartan XL device:

How to infer both outputs of a dual ported memory's element
(namely SPO and DPO of RAM16X1D) from plain Verilog.

An attempt to write:
//+++
module memdp64x1( raddr, waddr, do, do_at_wa, di, we, clk );
....
always @(posedge clk)
   if (we) mem[waddr] = di;
assign do = mem[raddr];
assign do_at_wa = mem[waddr];
//---
results in 'plain' logic (sea of DFFs and LUTs).

Article: 29442
Subject: Re: clock divider by 1.5
From: Peter Alfke <peter.alfke@xilinx.com>
Date: Wed, 21 Feb 2001 09:41:02 -0800
Links: << >>  << T >>  << A >>

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You have two different choices:

If your incoming clock has a 50% duty cycle, just use both edges, as described in
http://www.xilinx.com/xcell/xl33/xl33_30.pdf

If   you don't want to trust the duty cycle, you must first double the clock frequency, then divide by 3.
All Virtex devices have a clock-frequency doubler in their DLL, so the solution is trivial.

Peter Alfke, Xilinx Applications
========================
Goran wrote:

> Im beginer in vhdl and i need to create a clock divider by 1.5.I have found such one in edn magazine (on the web) but it didnt help me.Does someone have better idea then the one in edn magsine.
>
> If someone wants to look at the design in edn : http://www.ednmag.com/ednmag/reg/1996/101096/21di_05.htm

--------------AB47E340E30D2EC32E473855
Content-Type: text/html; charset=us-ascii
Content-Transfer-Encoding: 7bit

<!doctype html public "-//w3c//dtd html 4.0 transitional//en">
<html>
You have two different choices:
<p>If your incoming clock has a 50% duty cycle, just use both edges, as
described in
<br><u><A HREF="http://www.xilinx.com/xcell/xl33/xl33_30.pdf">http://www.xilinx.com/xcell/xl33/xl33_30.pdf</A></u>
<p>If&nbsp;&nbsp; you don't want to trust the duty cycle, you must first
double the clock frequency, then divide by 3.
<br>All Virtex devices have a clock-frequency doubler in their DLL, so
the solution is trivial.
<p>Peter Alfke, Xilinx Applications
<br>========================
<br>Goran wrote:
<blockquote TYPE=CITE>Im beginer in vhdl and i need to create a clock divider
by 1.5.I have found such one in edn magazine (on the web) but it didnt
help me.Does someone have better idea then the one in edn magsine.
<p>If someone wants to look at the design in edn : <a href="http://www.ednmag.com/ednmag/reg/1996/101096/21di_05.htm">http://www.ednmag.com/ednmag/reg/1996/101096/21di_05.htm</a></blockquote>
</html>

--------------AB47E340E30D2EC32E473855--


Article: 29443
Subject: Re: to you sir Peter Alfke...
From: Falk Brunner <Falk.Brunner@gmx.de>
Date: Wed, 21 Feb 2001 18:51:16 +0100
Links: << >>  << T >>  << A >>
erika churchil schrieb:
> 
> Hello,
> 
> Last week, i asked if a disabled FDC still consumes power or now.
> The answer of  PETER said that a disabled FDC consumes as much power as a
> clocked FDC but with a constant input.
> 
> could you tell me how,generally ,we compute  a power ?, and what's the ratio
> between the power consumed by a disabled FDC and the power consumed by an
> FDC  fed by an input that toggles continuosely between 1 and 0 ?
> 

Havce a look at the xilinx homepage.

www.xilinx.com   -> Products -> Design Tools -> Xpower

-- 
MFG
Falk

Article: 29444
Subject: Re: Clocks
From: Falk Brunner <Falk.Brunner@gmx.de>
Date: Wed, 21 Feb 2001 18:57:11 +0100
Links: << >>  << T >>  << A >>
Frode Vatvedt Fjeld schrieb:
> 

> So, I'm looking for pointers to information on designing clock
> generators (suitable for driving FPGAs). What do you all use?

Simply go out and buy one. Just connect power to it and you will get a
nice square wave out of it.
Ranges from 32 kHz to 100MHz++.

-- 
MFG
Falk

Article: 29445
Subject: Re: Clocks
From: Frode Vatvedt Fjeld <frodef@acm.org>
Date: 21 Feb 2001 19:08:51 +0100
Links: << >>  << T >>  << A >>
Falk Brunner <Falk.Brunner@gmx.de> writes:

> Frode Vatvedt Fjeld schrieb:
> 
> > So, I'm looking for pointers to information on designing clock
> > generators (suitable for driving FPGAs). What do you all use?
> 
> Simply go out and buy one. Just connect power to it and you will get
> a nice square wave out of it.  Ranges from 32 kHz to 100MHz++.

Sounds very good. Could you name some example devices? I'm not quite
sure which keywords to search for.

-- 
Frode Vatvedt Fjeld

Article: 29446
Subject: Re: Fine Phase Shift in VirtexII
From: Heinrich Fonfara <fonfarah@ibmt.fhg.de>
Date: Wed, 21 Feb 2001 19:20:40 +0100
Links: << >>  << T >>  << A >>



>
> Thanks for all suggestions you wrote, there are some good hints for me to
> think about.
>
> But maybe my explanation was not precise enough what I want to achieve.
> The phase should be stepped forwards in fixed increments of  X ns, its
> the
> same function as already implemented in DCM, but with much larger steps. I
> use
>  frequencies of about 1 to 20MHz and the shifting steps must be a 1/4,
> 1/8,or 1/16 of the period.
>
> In the past design I made that with a loadable counter operated as a clock
> divider. The counter
> was driven with 120MHz and loaded with its own TC. The load data was
> switched between two
> values every time a phase shift was needed. So I achieved shift
> increments  X/16 of a period.
>
> That was not the finest method for my application because I want to
> generate a clock for
> ADC and fifo in order to delay signals digitally. The clock becomes
> additional delay by
> passing the interconnections on the way to the output pins. When creating
> this for more
> channels I get clocks that are delayed to each other, so the calculated
> phase shift did not match.
>
> Regards
>
> Heinrich Fonfara


Article: 29447
Subject: Re: Clocks
From: eteam <eteam@aracnet.com>
Date: Wed, 21 Feb 2001 10:30:37 -0800
Links: << >>  << T >>  << A >>
manufacturers of self-contained crystal oscillators include:

epson   http://www.eea.epson.com/products/qd/qd.htm (north america site)
fox     http://www.foxonline.com/
citizen http://www.citizencrystal.com/
connor  http://www.conwin.com/products/clock.html
cts     http://www.ctscorp.com/reeves/
ecs     http://www.ecsxtal.com/

There are more, but this should get you started.

In the future, try going to a distributor site like www.digikey.com, search for
keywork "oscillator", and see what happens.

-- Bob Elkind

Frode Vatvedt Fjeld wrote:
> 
> Falk Brunner <Falk.Brunner@gmx.de> writes:
> 
> > Frode Vatvedt Fjeld schrieb:
> >
> > > So, I'm looking for pointers to information on designing clock
> > > generators (suitable for driving FPGAs). What do you all use?
> >
> > Simply go out and buy one. Just connect power to it and you will get
> > a nice square wave out of it.  Ranges from 32 kHz to 100MHz++.
> 
> Sounds very good. Could you name some example devices? I'm not quite
> sure which keywords to search for.
> 
> --
> Frode Vatvedt Fjeld

Article: 29448
Subject: Re: Integrated Conf.EPROM / smaller Footprints?
From: "C.Schlehaus" <carlhermann.schlehaus@t-online.de>
Date: Wed, 21 Feb 2001 20:06:12 +0100
Links: << >>  << T >>  << A >>
Hi,

"Thorsten Bunte" <t.bunte@beckhoff.de> schrieb im Newsbeitrag
news:96vr66$n6cep$1@ID-22362.news.dfncis.de...
> Hi,
>
> A smaller footprint of config devices would be very nice. The EPC1441TC32
is
> as big as the EPF6016AFC100 we use. Altera told us that it is impossible
to
> go to a smaller package due to the die size of the memory device.

That means, that the EPROM has a greater or at least comparable size than
the die in the FPGA. That seems to be astonishing, as the EPC2 which has
more storage isn't greater either. The EPC16 seems to be a nice approach,
as it ships in an BGA package, but I'd really like to see an EPC1 or EPC2
in a SO8 package or smaller.
Unfortunately the Configuration EPROMs storage is increased to fit the
demand of the growing FPGAs, but if You are working with the smaller
devices, You didn't need 16MBit...

> Integrating the config memory does make sense if You use an FPGA as a
stand
> alone device.
>
> In some of our case we use a C and load the configuration through the C.
> So, there is no need for a prom. We do not want to buy memory which we do
> not need.
>

That's correct, but I wouldn't prognose the FPGA with integrated PROM
to cost as much as FPGA+PROM, as You could incorporate the EPROM on the
same die, eliminating the need for a separate housing. But it would
be more expensive than the FPGA without PROM like it's available now.

> If You like to save the space for a prom use an FPGA of Actel. They use
> antifuse tech. Problem is that you can program it only once.

I already asked ACTEL for the comparable ACTEL FPGA which could replace
my EP1K100, but the device they told me is more expensive. And as you
already wrote, it's a one-way-ticket. I need reprogrammability.

CU, Carlhermann



Article: 29449
Subject: Re: Spartan II power
From: Paul Smith <ptsmith@indiana.edu>
Date: Wed, 21 Feb 2001 14:11:49 -0500
Links: << >>  << T >>  << A >>
Hi Rick,

No, no one from Xilinx has answered this question, either on the
newsgroup, or offline.  I also searched the Xilinx website without
finding anything about this.

I was able to get 10 pcs of XC2S50-5TQ144 without too much trouble.

Paul Smith



Rick Collins wrote:
> 
> Paul Smith wrote:
> >
> > How are people handling the large (500 mA) startup current for a Spartan
> > II device?

> 
> This is a question that has appeared here several times already. The
> Xilinx people can give you a lot of data, which they may have done
> offline as they did with me. But none of it helps me to get around the
> 500 mA requirement. The new board I am building will have 5 FPGAs on a
> very small board. To have to supply 2.5 Amps, even for a brief moment at
> startup, is a very hard thing to do on this board since it makes it's
> own 2.5 volts.
> 
> I never got the info on what the Spartan II would do if you could only
> supply 400 mA, for example. They will tell you that different Vdd ramp
> speeds require different supply currents. But they do not have any hard
> data to tell you that a specific ramp rate will only require X mA of
> supply current.
> 
> But then I keep hearing how you can't get them anyway, so how does it
> matter what current they draw?
> 
> --
>



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