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Messages from 29575

Article: 29575
Subject: Re: I want to learn sth about FPGA
From: Ray Andraka <ray@andraka.com>
Date: Tue, 27 Feb 2001 13:21:55 GMT
Links: << >>  << T >>  << A >>
FPGA design is really just well disciplined synchronous digital design.  There
are some extra constraints thrown in to account for the granularity of the FPGA
structure in order to get the design efficiency/density up.  For stareters
though, if  you have a background in digital design you can pull off successful
FPGA designs.  You might start with one of the starte kit boards such as those
sold by XESS.   Some of these come with lab manuals to give you whatever amount
of handholding you need to get started.  Once you start playing with them, you
can look into improving your designs to use the features and structure of the
PFGA.

Chengping Zhang wrote:
> 
> I have some background in micro controller circuit design and now wants to
> learn how to use FPGA in designing circuits. Can anyone give me some
> recommendation on how to start? Do you think it is difficult to learn?

-- 
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com  or http://www.fpga-guru.com

Article: 29576
Subject: Re: Spartan II power
From: "Simon Bacon" <simonb@tile.demon.co.cuthis.uk.>
Date: Tue, 27 Feb 2001 13:25:00 -0000
Links: << >>  << T >>  << A >>

"Ray Andraka" <ray@andraka.com> wrote in message
news:3A9BAA34.E21C2155@andraka.com...

> (if it is not, then you can
> usually use serial or time multiplex techniques to get into a smaller part
with
> a smaller boot current).

Virtex data sheet has single boot current, irrespective of device size.



Article: 29577
Subject: Re: DLL jitter "bake-off" vs. PLL
From: Ray Andraka <ray@andraka.com>
Date: Tue, 27 Feb 2001 13:27:40 GMT
Links: << >>  << T >>  << A >>
Rick,

You've apparently discovered one of (what I consider to be) the major advantages
to the xilinx architecture.  The SRL16/CLB ram capability of the Xilinx
architectures has enormous potential for reducing the size of a design compared
to any other FPGA out there.  I've also mentioned the limitations of the carry
chain implementation in Altera families here before, as cmpared to the Xilinx
carry structure.  From a silicon standpoint, the Xilinx architecture is superior
for data path and signal processing designs.  As for the 622MHz I/O, be cautious
of the claims of any vendor. There are plenty of caveats.  Also, even if the IO
pins support it, make sure you understand the clocking structure as well, as the
clock is often the limiting factor rather than the IOBs.



Rick Collins wrote:
> 
> Falk Brunner wrote:
> >
> > Austin Lesea schrieb:
> > >
> > > For those interested:
> > >
> > >  http://www.xilinx.com/products/virtex/techtopic/vtt013.pdf
> >
> > ;-))) This is getting funny.
> >
> > > Comments are appreciated,
> >
> > Hmm, what should we expect?? That Altera says the Xilinx parts are
> > better??
> > And Xilinx says the Altera parts are better??
> > Both "experiments" have their points, but they both have the smell of
> > marketing and influenced by company policy.
> > Its like the Pepsi and Coca fight . . .
> > After all, both devices must prove their qualities in real world
> > appllication, its alwas possible to bring a good device down on the
> > knees with a heavy test (and vica versa ;-))
> >
> > --
> > MFG
> > Falk
> 
> Yes, and this also ignores the many other issues involved in picking an
> FPGA vendor. I am working with a company that does not commit to a
> single vendor. They do their FPGA designs in HDL and do not use heavily
> the proprietary features unless necessary. They then pick the chip for
> the board at the final stage before building the prototype. This
> maximizes their leverage and gets them the best price for their boards.
> 
> Of course there are times that they have to pick one or the other based
> on technical features. A new design with 10 Gbps fiber interface was
> just not doable in a Xilinx part because of the high speed (622 MHz)
> data path. The Altera part does this with a single clock. The Xilinx
> solution was to use a clock for every two data pins. They would have
> then needed fifos to resync the data to a common clock. The designers
> felt this was not workable.
> 
> I personally am more impressed with the Xilinx parts. I recently found
> that the low cost ACEX parts from Altera (based on the 10K arch) does
> not let you use the LUTs as RAM. I see this as a major drawback when you
> need many small fifos.
> 
> But again a non-technical issue of supply may force me to use the ACEX
> instead of the Spartan II parts.
> 
> --
> 
> Rick "rickman" Collins
> 
> rick.collins@XYarius.com
> Ignore the reply address. To email me use the above address with the XY
> removed.
> 
> Arius - A Signal Processing Solutions Company
> Specializing in DSP and FPGA design      URL http://www.arius.com
> 4 King Ave                               301-682-7772 Voice
> Frederick, MD 21701-3110                 301-682-7666 FAX

-- 
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com  or http://www.fpga-guru.com

Article: 29578
Subject: Programming Vertex-II FPGAs.
From: "Vincent Monroe" <vimonroe@home.com>
Date: Tue, 27 Feb 2001 13:27:55 GMT
Links: << >>  << T >>  << A >>
Does anyone know if there is any freeware for the optimization and
programming of Vertex-II devices?  Just the smaller ones in the 40K to 500K
gate range.  I got the free WebPack tools but the only seem to be able to
route Spartan-II or earlier FPGAs.  Am I going to have to try and find a
copy of foundation or alliance on the sly?  If so are there any webpages out
there that trade in such things.  Feel free to email me.

vimonroe@home.com



Article: 29579
Subject: Re: Spartan II power
From: Magnus Homann <d0asta@licia.dtek.chalmers.se>
Date: 27 Feb 2001 15:35:23 +0100
Links: << >>  << T >>  << A >>
Rick Collins <spamgoeshere4@yahoo.com> writes:

> BTW, I am not aware of any 500 mA LDO regulators in the SC70 (2mm x 2mm)
> package you describe. The highest current I have found in this small
> package is about 100 mA. SOT-23 packages boost that up to about 150 to
> 200 mA and you can get 300 or better from a MSOP8 package, 3mm x 5mm.

I'm _not_ experienced in power supply design, but I found the Micrel MIC5219 in
a SOT-23-5 (3x3mm). "Startup inrush current" max 500mA, continous 150-200 mA.

So, 200 mA at 0.8V is 160mW continous. With thetaJA of 220 (ouch!)
that makes 35 degrees. Not bad. I'm not sure if the thetaJA is relevant for the
startup current.

Do you think such a device would be apropriate?

Homann
-- 
Magnus Homann, M.Sc. CS & E


Article: 29580
Subject: Re: Xilinx tools: RLOC hierarchy with HDL design?
From: "Jan Gray" <jsgray@acm.org>
Date: Tue, 27 Feb 2001 14:47:56 GMT
Links: << >>  << T >>  << A >>
"Reinoud" <dus@wanabe.nl> wrote in message
news:3A9B9181.F9E4A148@wanabe.nl...
>
> Jan, Ray: thanks.  So hierarchy works with attributes in source (and
> most Verilog synthesis tools support attributes in some way
> nowadays).

Be careful.  The last time I looked (3.1? 3.2?) FPGA Express discarded
explicit instantiation of FMAPs, of all things.  See
www.fpgacpu.org/usenet/rope_pushing.html.  This shortcoming was scheduled to
be fixed for a long time -- has it been fixed?  (Not according to
http://www.xilinx.com/techdocs/4395.htm.)

The workaround (defining and using my own FMAP_.edn) was untenable too.  So
now I use Synplify.

It would be nice if Xilinx would work with the synthesis vendors to define
1) a common attribute syntax and 2) a common and convenient notation to map
an assign to a LUT/FMAP.  Now with XST they have a bully pulpit.  (Of course
this won't happen as it would reduce vendor lock-in.)

(Synplify lets you map an assign to a LUT/FMAP, but since you have to move
the assign to its own module, I do not consider it a *convenient* notation.)

Jan Gray, Gray Research LLC




Article: 29581
Subject: Re: cpul vs vhdl
From: Bertram Geiger <bgeiger@aon.at>
Date: Tue, 27 Feb 2001 16:49:11 +0100
Links: << >>  << T >>  << A >>

> > CUPL is bad comparad to vhdl?
> 
> CUPL is a _toy_ compared to VHDL.
> 
> "Bad" is a little more subjective...
> 
> ---Joel Kolstad

Sometimes its nice to have toys ... ;-)

So - i like my ABEL Toy

Bertram

-- 
Bertram Geiger,  bgeiger@aon.at
HTL Bulme Graz-Goesting - AUSTRIA

Article: 29582
Subject: Re: Partial Reconfig using JBits
From: "Antti Lukats" <antti@case2000.org>
Date: Tue, 27 Feb 2001 20:47:33 +0200
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.

------=_NextPart_000_0011_01C0A0FE.8274BD80
Content-Type: text/plain;
	charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable

You are right with JBits you need to work on pretty low level, i.e. you =
can use any VHDL file here.

BIG Question: Where did you get JBits SDK? I know it exists but cant =
figure out how to get the tool/docs

tnx
Antti
  ""Jaimeet Aneja"" <JAneja@nuron.com> wrote in message =
news:00b201c0a049$bc6f2030$1b0aa8c0@nuron.com...
  I need help with partial reconfig of a virtex Chip. JBits has been =
suggested to me.
  From what I understand of JBits I am under the impression that VHDL, =
BDE source files cannot be used with JBits. Is this true ?=20

  Jaimeet Aneja

------=_NextPart_000_0011_01C0A0FE.8274BD80
Content-Type: text/html;
	charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable

<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META http-equiv=3DContent-Type content=3D"text/html; =
charset=3Diso-8859-1">
<META content=3D"MSHTML 5.50.4134.600" name=3DGENERATOR>
<STYLE></STYLE>
</HEAD>
<BODY bgColor=3D#ffffff>
<DIV><FONT face=3DArial size=3D2>You are right with JBits you need to =
work on pretty=20
low level, i.e. you can use any VHDL file here.</FONT></DIV>
<DIV><FONT face=3DArial size=3D2></FONT>&nbsp;</DIV>
<DIV><FONT face=3DArial size=3D2>BIG Question: Where did you get JBits =
SDK? I know=20
it exists but cant figure out how to get the tool/docs</FONT></DIV>
<DIV><FONT face=3DArial size=3D2></FONT>&nbsp;</DIV>
<DIV><FONT face=3DArial size=3D2>tnx</FONT></DIV>
<DIV><FONT face=3DArial size=3D2>Antti</FONT></DIV>
<BLOCKQUOTE dir=3Dltr=20
style=3D"PADDING-RIGHT: 0px; PADDING-LEFT: 5px; MARGIN-LEFT: 5px; =
BORDER-LEFT: #000000 2px solid; MARGIN-RIGHT: 0px">
  <DIV>""Jaimeet Aneja"" &lt;<A=20
  href=3D"mailto:JAneja@nuron.com">JAneja@nuron.com</A>&gt; wrote in =
message <A=20
  =
href=3D"news:00b201c0a049$bc6f2030$1b0aa8c0@nuron.com">news:00b201c0a049$=
bc6f2030$1b0aa8c0@nuron.com</A>...</DIV>
  <DIV><FONT face=3DArial size=3D2><FONT face=3DArial size=3D2>I need =
help with partial=20
  reconfig of a virtex Chip. JBits has been suggested to =
me.</FONT></FONT></DIV>
  <DIV><FONT face=3DArial size=3D2><FONT face=3DArial size=3D2>From =
what&nbsp;I=20
  understand&nbsp;of JBits I am under the impression that VHDL, BDE =
source files=20
  cannot be used with JBits. Is this true ? </FONT></FONT></DIV>
  <DIV><FONT face=3DArial size=3D2></FONT>&nbsp;</DIV><FONT face=3DArial =
size=3D2>
  <DIV><FONT face=3DArial size=3D2>
  <DIV><FONT face=3DArial size=3D2>Jaimeet=20
Aneja</FONT></DIV></FONT></DIV></BLOCKQUOTE></FONT></BODY></HTML>

------=_NextPart_000_0011_01C0A0FE.8274BD80--


Article: 29583
Subject: Re: Xilinx tools: RLOC hierarchy with HDL design?
From: "Chris G. Schneider" <chris@cgschneider.com>
Date: 27 Feb 2001 20:59:41 +0100
Links: << >>  << T >>  << A >>
"Jan Gray" <jsgray@acm.org> writes:

> Be careful.  The last time I looked (3.1? 3.2?) FPGA Express discarded
> explicit instantiation of FMAPs, of all things.  See
> www.fpgacpu.org/usenet/rope_pushing.html.  This shortcoming was scheduled to
> be fixed for a long time -- has it been fixed?  (Not according to
> http://www.xilinx.com/techdocs/4395.htm.)

Yes FPGA Express 3.5 can do it now. I am not sure on the older
versions of FPGA Express, however. FPGA Express warns that it
has no compontent assiciated with the FMAP, but it passes this 
information to the edif file. And the Xilinx tools know what to do. 
I am not sure about Verilog support.
 
-- 
Chris

Article: 29584
Subject: Re: Samll quantities ordering
From: Eric Smith <eric-no-spam-for-me@brouhaha.com>
Date: 27 Feb 2001 11:59:45 -0800
Links: << >>  << T >>  << A >>
Ray Andraka <ray@andraka.com> writes:
> Try Avnet or Insight.  I'm pretty sure you can get XC2S50's fairly
> readily now, at least in the fg256 packaging. I've got several
> customers using these parts, and they do not seem to be having any
> trouble getting them any more.

Search results for XC2S50 on www.avnetmarshall.com:

	2 variants listed as "Not available for ordering"
	12 variants listed as "No Stock"
	All 14 give a lead time of "No information available"

Search results for XC2S50 on www.arrow.com:

	0 results - strange, they've had them in the database before

Search results for XC2S50 on www.insight-electronics.com:

	13 variants list "Qty Avail" as "Ask"
        1 variant (XC2S50-5PQ208C lists "Qty Avail" as 317 and
                Unit Cost as $14.75

Wow, success!!!!  (Now someone else will buy them all before I do.)

In other news, just yesterday I received the BED-SPARTAN2+ kit I ordered
from Burch Electronic Designs on the 16th.  Not bad for getting a
product from Australia to the US.  They said allow 4-10 working days,
and it's been eight.

I haven't fired it up yet, but it looks like a pretty useful eval board.
It has an XC2S200PQ208.  I'm not sure how to match the rest of the
markings to the part numbers from the data sheet.  There's a "5C" by
itself on the last line, so I'm guessing that the actual part numer is
XC2S200-5PQ208C.

The pins are brought out to dual-row square pin headers, and there's a
fair bit of pad-per-hole prototyping space.  There are two voltage
regulators, a 24 MHz oscillator (socketed), a socket for a config
EEPROM, and a download header.  It also comes with a parallel download
cable, and a mini CD-ROM of the WebPack ISE software.  (Of course, you
can download that free from the Xilinx web site, but in a misguided
attempt to make that easy, they've constructed a complicated download
manager that makes it difficult.)

Seems like quite a value for about US $120.

I'm surprised to see from Burch's web site that this product is now
completely sold out, and that they're introducing a new model on March
9.  I wonder what will be different.

Anyhow, sorry if my message sounds like an advertisement, I don't
actually have any affiliation with Burch's.  I'm just happy to finally
get my hands on a Spartan II for development.

Article: 29585
Subject: Xilinx P&R problem?
From: "Chris G. Schneider" <chris@cgschneider.com>
Date: 27 Feb 2001 20:59:56 +0100
Links: << >>  << T >>  << A >>

Assume the following situation:


                    Pin1                    Pin2   
    -----------------O-----------------------O-----------
                    /                       /
                   /                       /
                  /                       /
                 /                       /
                CLB------>------>-------/ 
               / |
              /  |
         TIG /   | TIG
            /    |
           /     |


There is a critcal path constraint form pin1 to pin2, the
other CLB inputs are constaint as TIG's. 

The placer does not manage to place the CLB near pin1, 
even if there is no other CLB used in this area of the 
FPGA. Why?

Yes I can do floorplaning, but I just thought that this 
situation is so obvious that even the placer finds a
solution, with ease.
               
-- 
Chris

Article: 29586
Subject: Re: Samll quantities ordering
From: Reinoud <dus@wanabe.nl>
Date: Tue, 27 Feb 2001 21:12:36 +0100
Links: << >>  << T >>  << A >>
Eric Smith wrote:
> In other news, just yesterday I received the BED-SPARTAN2+ kit I ordered
> from Burch Electronic Designs on the 16th.
> ...
> Seems like quite a value for about US $120.

Yep, really nice board and service, unbelievable price :-).  You even get
a Xilinx-compatible parallel download cable with it...  The only thing
I have doubts about is how long the company can stay afloat this way ;-).

Needless to say, I'm not being paid to write this.

- Reinoud

Article: 29587
Subject: ASIC ASIC ASIC - CANADA - ASIC ASIC ASIC ASIC ASIC
From: "InGenius Engineering" <Ellen@ingeniusengineering.com>
Date: Tue, 27 Feb 2001 20:12:40 GMT
Links: << >>  << T >>  << A >>
Do you have minimum three years ASIC design experience? Not advancing in
your current position? Ready for a change?

We have some of the best clients in the ASIC industry, with several exciting
opportunities for ASIC Engineers.

Send a resume in confidence, with a note stating your area of interest and
expertise, or contact us directly at: (613) 729-6400 x 241 and we will be
happy to review some of our current openings with you.

Email: ellen@ingeniusengineering.com

____________________________________
**************************************

Ellen Ann Nichol - Staffing Consultant -

InGenius Engineering

30 Rosemount Ave.Ottawa, Ontario

K1Y 1P4

Phone: (613) 729-6400 x 241

Fax: (613) 729-6770
www.ingeniusengineering.com

****************************************





ellen@ingeniusengineering.com








Article: 29588
Subject: Interfacing Xilinx 4003 to an IDE Hard Disk interface.
From: Bard_64 <Bard_64@ntlworld.com>
Date: Tue, 27 Feb 2001 20:21:25 +0000
Links: << >>  << T >>  << A >>



                 Hello Everyone.

                 I am currently doing backgroud reading on a project
involving the
                 interfacing of a Hard disk to a Palm Pilot.

                 I was wondering could it be possible to access the IDE
interface
                 using an FPGA (specifically the X4003).

                 Thanks

                 Daniel


Article: 29589
Subject: Re: cpul vs vhdl
From: <NOSPAM@NOSPAM.NOSPAM>
Date: Tue, 27 Feb 2001 20:32:17 +0000
Links: << >>  << T >>  << A >>
Hi

I cannot see any circumstances whatsoever where time spent learning CUPL
would not be completely and utterly wasted. 

If you want a skill that will make you more attractive to an employer,
then go for VHDL (AFIK there is a free compiler on Altera's site).

If you want to familarise yourself with CPLDs & FPGAs go to Altera's
site, download MAXPLUS2 and get yourself into AHDL. If possible get hold
of the Altera Maxplus2 AHDL printed manual... and read it. 

If you want bleeding edge technology, go to Xylinx.

Specific problems with CUPL :

1. No longer even listed on Logical Devices web site. It looks although
Protel bought the code.

2. From Protel's site (http://www.protel.com/eproduct/protel99sefeatures
_home.html): "Includes specialized fitters for; Altera Max, AMD MACH,
Atmel High Density EPLDs, Cypress, Intel FLEX, ICT EPLD/FPGAs, Lattice,
National MAPL, Motorola, Philips PML, Xilinx EPLD " Now we all know that
many of these companies have given up on PLDs all together. Would you
trust a product who's marketing department has such a loose grip on
reality ?

3. No support for Hierarchal Design last time I looked.

4. No support for parametarisation last time I looked.

5. The fitters included in 2 above are those available for free from the
manufacturer's.




In article <9786bv$62b$1@news.inet.tele.dk>, Will <dont@mail.me> writes
>Got my hands on protel which supports cupl and not vhdl, but now i am
>wondering if its a waste of time to learn cupl.
>As i understand, from another question i posted somewhere, cupl is not as
>wide a standard as vhdl, so will i just end up with knowing a language which
>is not used anywhere? or will it be a sound investment of time?
>
>
>

-- 
Steve Dewey

Article: 29590
Subject: Re: programmable coefficient fir filter?
From: Ray Andraka <ray@andraka.com>
Date: Tue, 27 Feb 2001 20:39:39 GMT
Links: << >>  << T >>  << A >>
If you use Xilinx Virtex, you can reload the coefficients of a distributed
arithmetic filter at a rate of 4 clocks per coefficient by using SRL16 elements
instead of the LUTs.  A 100 MHz sample rate will require a parallel or at most a
2 clock per sample design.  If the 32 tap filter is symmetric, you'll save some
area by using the symmetry.  In any event, the filter is going to be reasonably
large.  Both Altera and Xilinx have filter generators that should help you in
the design process.  I think you will find that the 100 MHz sample rate will be
easier to achieve in the Xilinx parts, but may still require some floorplanning.

wayne wrote:
> 
> The coef change every 5 seconds, the sample rate is 100MHz, the filter outputs the result every clock cycle. There are 2 channels and 4 such filters per channel. To fit into 1 FPGA chip, the speed and area is hard for me to achieve.
> Thank you very much.

-- 
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com  or http://www.fpga-guru.com

Article: 29591
Subject: Re: cpul vs vhdl
From: Jim Granville <jim.granville@designtools.co.nz>
Date: Wed, 28 Feb 2001 10:09:35 +1300
Links: << >>  << T >>  << A >>
Will wrote:
> 
> > You can download free software from both Xilinx and Altera to design
> > FPGAs in VHDL or Verilog. So why both learning CUPL? You don't need to
> > be limimted by your software.
> 
> CUPL is bad comparad to vhdl?

They are different, it's a bit like comparing Structured Assembler, and
Visual Basic.

The Simple Hardware Description Languages like CUPL, Abel, Altera
flavour AHDL,
and Philips Flavour PHDL target mainly PLD family devices, but I know
designers
using Altera AHDL on quite complex designs.

It all depends on the target device and design complexity

For  16V8/20V8/22V10 design flows, VHDL is not well supported, but for
1MegaGate
FPGA's I don't think anyone would use CUPL.

We have designs squeezed into CPLD's using CUPL, that would not have
been possible
using VHDL.

- jg

Article: 29592
Subject: Re: Spartan II power
From: rk <stellare@nospamplease.erols.com>
Date: Tue, 27 Feb 2001 16:29:54 -0500
Links: << >>  << T >>  << A >>
Austin Lesea wrote:

> I believe we are the only FPGA company to specify and test every part for power on
> behavior, and perform extensive characterization in the lab on a regular basis and after
> every process or design change.

I believe you are correct.  I haven't seen other vendors put this as
part of the specification.  Actel, for example, does do characterization
and provides numbers over a variety of power supply ramp rates as well
as some sample data in their application notes and reports.

-- soapbox mode on

All specifications should be in the data sheets as limits so that when
every condition is met in the data sheet, the part works.  Every time. 
And for every part.

Metastable state parameters should be in there too.  ;-)

-- soapbox mode off

-----------------------------------------------------------------------
rk                               Micromanaging leads to macro f'ups.
stellar engineering, ltd.        -- Richard Marcinko, Seal Team Six
stellare@erols.com.NOSPAM        
Hi-Rel Digital Systems Design

Article: 29593
Subject: Re: Partial Reconfig using JBits
From: Neil Franklin <neil@franklin.ch.remove>
Date: 27 Feb 2001 23:03:21 +0100
Links: << >>  << T >>  << A >>
"Antti Lukats" <antti@case2000.org> writes:

> BIG Question: Where did you get JBits SDK? I know it exists but cant =
> figure out how to get the tool/docs

Send mail to jbits@xilinx.com

They will then send you an URL and an password to download it.


Please do not mail and post a question. Most people read their personal
mail first and answer questions it it. They then read news and have to
answer the same question again for the group. This wastes their time
with double work.


> ------=_NextPart_000_0011_01C0A0FE.8274BD80
> Content-Type: text/html;
>       charset="iso-8859-1"
> Content-Transfer-Encoding: quoted-printable
>
> <!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
> <HTML><HEAD>
> <META http-equiv=3DContent-Type content=3D"text/html; =
> charset=3Diso-8859-1">

Please do not sent HTML to news groups or personal mail boxes, unless
you know that the recipient(s) have explicitely stated that they can
and like to recieve it. There are still many people using non-HTML
mailers and newsreaders who dislike having to dig a few lines of
message out of many lines of crap like the above ones. Particularly if
they have to first download the crap over an pay-connect-time phone line.


--
Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/
Hacker, Unix Guru, El Eng FH/BSc, Sysadmin, Roleplayer, LARPer, Mystic

Article: 29594
Subject: Re: Re: Partial Reconfig using JBits
From: JAneja@nuron.com ("Jaimeet Aneja")
Date: 28 Feb 2001 01:09:18 +0100
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.

------=_NextPart_000_0005_01C0A0D6.294F1CF0
Content-Type: text/plain;
	charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable

you can jbits from xilinx email jbits@xilinx.com
and they will get in touch with you.

jaimeet

------=_NextPart_000_0005_01C0A0D6.294F1CF0
Content-Type: text/html;
	charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable

<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
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http-equiv=3DContent-Type>
<META content=3D"MSHTML 5.00.3103.1000" name=3DGENERATOR>
<STYLE></STYLE>
</HEAD>
<BODY bgColor=3D#ffffff>
<DIV><FONT face=3DArial size=3D2>you can jbits from xilinx email <A=20
href=3D"mailto:jbits@xilinx.com">jbits@xilinx.com</A></FONT></DIV>
<DIV><FONT face=3DArial size=3D2>and they will get in touch with =
you.</FONT></DIV>
<DIV>&nbsp;</DIV>
<DIV><FONT face=3DArial size=3D2>jaimeet</FONT></DIV></BODY></HTML>

------=_NextPart_000_0005_01C0A0D6.294F1CF0--


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Posted from mail.nuron.com [63.100.168.245] 
via Mailgate.ORG Server - http://www.Mailgate.ORG

Article: 29595
Subject: Re: Spartan II power
From: Austin Lesea <austin.lesea@xilinx.com>
Date: Tue, 27 Feb 2001 17:54:13 -0800
Links: << >>  << T >>  << A >>
Rick,

The kick is not intended to be in parallel.  There is no reason that this can not be used
with a switcher, in fact, that is even better from an efficiency point of view: the micro
power comparator/reference (is in the tiny package I gave dimensions for) would be used to
hold off the switcher for the 2.5 Vdc until the cap ahead of it was charged up.  Most
switchers can be set to integrate the current limiting so they can supply a transient of
many times what they can supply continuously.

The LDO is bigger than what I said, but I was assuming it was already there.

You make an excellent point about the smaller packages: they can't dissipate much power at
all without glowing in the dark.  I know people want to use them, but cs144, fg256 style
packages are not really good at getting rid of the heat.  One should always run thru the
power estimator excrcise -- especially in these thermally challenged packages!

Austin

Rick Collins wrote:

> Austin Lesea wrote:
> >
> > Rick,
> >
> > Call it what you will.
> >
> > It is intended to aid those that have less than the 500 mA available.
> >
> > Initially, we thought, "anyone using this IC will probably run it at a clock speed,
> > and with enough IO's that 500 mA will be required for its normal operation."
> > Obviously, there is a smaller contingent of users that do not use the fast clock
> > rates, or the large drive strengths, and need to get by with 200 or so mA.
> >
> > To help those users, we are working on the kick start circuit.
> >
> > As I said before, it is now being built, and we hope to have some results to report
> > by next week.
> >
> > The area we are talking about here is pretty tiny.  Surface mount caps are required
> > anyway for good bypassing.  The comparator is a tiny three leaded surface mount part
> > (2 X 2 mm?).  Resistors are pretty tiny as well.  I can't see them anymore (getting
> > old).
> >
> > The LDO will supply the voltage to the Vccint from the big capacitor, and at the
> > output of the LDO, the power will be rising monotonically.  The 3.3 Vdc may droop
> > (that is why it is better if available to run the core voltage LDO off 5 Vdc), but
> > the droop is something one engineers (I=C dV/dt) to be small.
> >
> > The monotonicity "rule" is not a hard rule.  We care about the voltage rising
> > through the POR trip point, and not falling back down after once passing through the
> > POR trip point.  I believe this is stated in a number of tech notes/tech tips.  It
> > may also be stated in the configuration section of the data sheet similar to how I
> > have stated it above.  This is even to be relaxed at some point in the future Virtex
> > II as we designed it to not care about this point in the power on ramp.  This is
> > something we will later test and verify as not being a problem.  As well, Virtex II
> > power on is in the tens of mA range, so we do try to improve in every subsequent
> > generation.
> >
> > Austin
>
> I think this is an issue that is a bit too complex to iron out in the
> newsgroup, so I will wait for the app note. I think one point I may be
> missing is that this circuit is not in addition to the 2.5v supply that
> I have on my board for the FPGAs, but rather is in place of them. So I
> lose the efficiency of the switcher that I planned to use and instead
> would get the efficiency of a lossy LDO, 75% vs 95% or worse, 50% if
> powered by 5v.
>
> The loss in efficiency is a problem for me. I am designing a board that
> is intended to be very low power when required. The only LDO on the
> board is for the DSP core voltage which is less than 100 mA.
>
> But I do understand the concept that you are using a current limited
> regulator for startup. Or did I miss your meaning and the "kick start"
> circuit is intended to parallel the main regulator?
>
> BTW, I am not aware of any 500 mA LDO regulators in the SC70 (2mm x 2mm)
> package you describe. The highest current I have found in this small
> package is about 100 mA. SOT-23 packages boost that up to about 150 to
> 200 mA and you can get 300 or better from a MSOP8 package, 3mm x 5mm.
> The caps you mention, 1000 uF may come in surface mount, but they are
> hardly tiny as the resistors are. This cap is likely bigger than the
> regulator. So the total area will be nearly as large as the FPGA in my
> application (FG256, 17mm sq or CS144 12mm sq).
>
> I am also puzzled that Xilinx felt that these chips would not often be
> used with low power requirements. The smaller XC2S chips are available
> in CS144 packages that are quite tiny and have a limited power capacity.
> With a theta JA of 35C/W, 500 mA will put the junction temp at 125C with
> an ambient temp of just 81C. This is not much of a margin of saftey. The
> TQ100 package is potentially much worse with a theta JA of up to 47C/W.
> This puts the maximum ambient at 66C.
>
> I am glad to hear the the Virtex II chips have reduced the startup
> current to below 100 mA. This is much more workable. Now if we could
> only get the low price combined with the low current!
>
> --
>
> Rick "rickman" Collins
>
> rick.collins@XYarius.com
> Ignore the reply address. To email me use the above address with the XY
> removed.
>
> Arius - A Signal Processing Solutions Company
> Specializing in DSP and FPGA design      URL http://www.arius.com
> 4 King Ave                               301-682-7772 Voice
> Frederick, MD 21701-3110                 301-682-7666 FAX


Article: 29596
Subject: Re: Interfacing Xilinx 4003 to an IDE Hard Disk interface.
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Wed, 28 Feb 2001 02:08:27 +0000
Links: << >>  << T >>  << A >>


Bard_64 wrote:

>                  Hello Everyone.
>
>                  I am currently doing backgroud reading on a project
> involving the
>                  interfacing of a Hard disk to a Palm Pilot.
>
>                  I was wondering could it be possible to access the IDE
> interface
>                  using an FPGA (specifically the X4003).
>
>                  Thanks
>
>                  Daniel

Question: What i/f has the PP got ? There are basically 3 ``levels'' of
IDE:

(1) PIO: Programmed I/O i.e. the disk is just treated as a dumb ISA
peripheral & you read/write data via some polled/int driven s/w routine.
[NB the data port is 16 bits wide but all the other registers are 8].

(2) DMA: Old fashioned 80?? DMA. Single transfer at a time.

(2a) MultiDMA: As above but you can do bursts as long as the DMA req's
active.

(3) UDMA: A  ``source synchronous'' abomination but it can get very high
data rates, UDMA66 up to 133MBytes/sec. Hard to design & get right since
the h/w protocol is both async wrt your system clock & tediously
complicated.

For something like a PP I would not have thought you'd need to go beyond 2a
if that.


Article: 29597
Subject: Re: Spartan II power
From: Rick Collins <spamgoeshere4@yahoo.com>
Date: Tue, 27 Feb 2001 21:55:04 -0500
Links: << >>  << T >>  << A >>
I don't follow the thinking that a fully utilized FPGA requires a lot of
power. In an earlier thread I was told that the startup current is the
largest in the smallest Spartan II parts. An XC2S15 should not require a
lot of operating current in many applications. This is also a function
of clock speed. 

Not all designs require the highest clock speed and many have large
parts of the circuit that do not cycle on every clock edge. BTW, not
every design is systolic or serially calculable. Much of my current
designs take a serial data stream and perfrom DMA to/from memory. By
definition there is not much I can do to trade off logic for speed
either way. 

The board I am currently selling has a total power consumption of 3
watts. Over half of that is in the DSP and memory, about .5 Watts are in
the IO section. This leaves less than a Watt in the four FPGAs on the
board for an average of 75 mA at 3.3 volts. The smaller parts are
utilized at about 80%. So where is the under utilization coming in? 

I don't see how requiring a 500 mA X 4 power supply is what I need on my
board. I really don't see how I need to add booster supplies or staging
switches to allow the FPGAs to boot in sequence. What I need is an FPGA
that does not require up to 2 Amps of startup current in the industrial
temperature range. 

Unfortunately every FPGA I have looked at has drawbacks. But then that
is what makes it engineering, right? Anyone can choose a solution that
is clearly better. It is harder to pick between two different tradeoffs. 


Ray Andraka wrote:
> 
> IIRC, you can get around the monotonicity requirement by holding the program pin
> until the power is stable.
> As to the boot current, this should not be a problem if you are really using the
> FPGA to its potential, as
> the operating current for a well utilized FPGA is higher than the boot current
> (if it is not, then you can
> usually use serial or time multiplex techniques to get into a smaller part with
> a smaller boot current).
> 
> Austin Lesea wrote:
> >
> > Rick,
> >
> > Call it what you will.
> >
> > It is intended to aid those that have less than the 500 mA available.
> >
> > Initially, we thought, "anyone using this IC will probably run it at a clock speed,
> > and with enough IO's that 500 mA will be required for its normal operation."
> > Obviously, there is a smaller contingent of users that do not use the fast clock
> > rates, or the large drive strengths, and need to get by with 200 or so mA.
> >
> > To help those users, we are working on the kick start circuit.
> >
> > As I said before, it is now being built, and we hope to have some results to report
> > by next week.
> >
> > The area we are talking about here is pretty tiny.  Surface mount caps are required
> > anyway for good bypassing.  The comparator is a tiny three leaded surface mount part
> > (2 X 2 mm?).  Resistors are pretty tiny as well.  I can't see them anymore (getting
> > old).
> >
> > The LDO will supply the voltage to the Vccint from the big capacitor, and at the
> > output of the LDO, the power will be rising monotonically.  The 3.3 Vdc may droop
> > (that is why it is better if available to run the core voltage LDO off 5 Vdc), but
> > the droop is something one engineers (I=C dV/dt) to be small.
> >
> > The monotonicity "rule" is not a hard rule.  We care about the voltage rising
> > through the POR trip point, and not falling back down after once passing through the
> > POR trip point.  I believe this is stated in a number of tech notes/tech tips.  It
> > may also be stated in the configuration section of the data sheet similar to how I
> > have stated it above.  This is even to be relaxed at some point in the future Virtex
> > II as we designed it to not care about this point in the power on ramp.  This is
> > something we will later test and verify as not being a problem.  As well, Virtex II
> > power on is in the tens of mA range, so we do try to improve in every subsequent
> > generation.
> >
> > Austin
> >
> > Rick Collins wrote:
> >
> > > Austin,
> > >
> > > I don't mean to be rude, but is this circuit intended to be a "fix" to
> > > the power up issue?
> > >
> > > I can just as easily increase the surge capacity of my power converter
> > > than to add a secondary circuit to handle the few mS of startup current.
> > > The cost of this added startup circuit may be small, but it uses a lot
> > > of board space. By the time you account for the power requirement of the
> > > I grade, the board space of the chip has doubled.
> > >
> > > The other issue that I would raise with this circuit is the requirement
> > > that the voltage at startup be increased monotonically. If you depend on
> > > capacitors to provide current to the load, then the voltage will sag
> > > during that time. Perhaps the parts are not affected by a small voltage
> > > droop, hence the huge capacitor requirement. But doesn't the data sheet
> > > say that the voltage must increase monotonically? I can't find that now.
> > > Perhaps I saw it in an app note or the data sheet for the Virtex parts?
> > > Or am I mistaken about this?
> > >
> > > Austin Lesea wrote:
> > > >
> > > > Rick & Paul,
> > > >
> > > > Been out on vacation, so I missed this question.
> > > >
> > > > Spartan II is a Virtex derivative, so it has the same behavior during power up
> > > > as the Virtex family.  Now this is about 2.5 years old, so it is a pretty well
> > > > known behavior.
> > > >
> > > > The ramp up time has a secondary effect on the amount of current required.
> > > > The shortest ramps require more current than the longer ramps, but as they get
> > > > close to 50 ms (the spec), the currents may start going back up again.
> > > > Current increases as temperature decreases.
> > > >
> > > > The current is required at about twice the Vt of the transistors (~0.7  to 1.0
> > > > Vdc), and lasts perhaps as long as 200 us in the smaller parts of Spartan.
> > > >
> > > > We are now building the "kick start" circuit I had previously described.  It
> > > > uses a 500 mA current limited LDO regulator with an enable pin.
> > > >
> > > > The enable pin comes from a micro power comparator /voltage reference ( we
> > > > abandoned the simple RC -- too unpredictable).
> > > >
> > > > When the input voltage (3.3 or 5 Vdc) passes a set threshold (set by two
> > > > resistors), the LDO is enabled.
> > > >
> > > > Ahead of the LDO is a ~1,000 uF 6.3 V cap that stores the necessary current to
> > > > start up the part.
> > > >
> > > > For four devices, this same technique can be extended to a larger cap, and a 2
> > > > ampere LDO.
> > > >
> > > > The idea is quite simple: use the stored charge in the big cap to provide the
> > > > necessary kick to get all the parts started.  For the I grade, at -40C, you
> > > > need 2 amps per part, and again, it is bigger capacitor, and larger regulators
> > > > (better is a low voltage switcher enabled by the comparator).
> > > >
> > > > The added cost is the mico power comparator / reference (less than 1$), two
> > > > resistors, and a big cap (<25 cents for a good aluminium electrolytic of large
> > > > value).  (This assumes you have to provide a 2.5 V power supply regulator
> > > > anyway).
> > > >
> > > > In the meantime, the Spartan designers continue to optimize process / design /
> > > > test to improve the startup behavior.
> > > >
> > > > As soon as we have tested the kick starter with all process corner silicon, I
> > > > will publish it as a note.
> > > >
> > > > Again, I apologize for the delays,
> > > >
> > > > Austin
> > >
> > > --
> > >
> > > Rick "rickman" Collins
> > >
> > > rick.collins@XYarius.com
> > > Ignore the reply address. To email me use the above address with the XY
> > > removed.
> > >
> > > Arius - A Signal Processing Solutions Company
> > > Specializing in DSP and FPGA design      URL http://www.arius.com
> > > 4 King Ave                               301-682-7772 Voice
> > > Frederick, MD 21701-3110                 301-682-7666 FAX
> 
> --
> -Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930     Fax 401/884-7950
> email ray@andraka.com
> http://www.andraka.com  or http://www.fpga-guru.com


-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 29598
Subject: Virtex ambit support
From: Kelvin =?big5?B?Q0hFVU5HL9XFvNLOsC+xaa5hsLY=?=
Date: Wed, 28 Feb 2001 14:00:37 +0800
Links: << >>  << T >>  << A >>
Hi,

We are looking for Virtex library for Ambit to do synthesis (alf or tlf).  However, what we can find is only synopsys .db files.  Please help.

Thanks.

Kelvin


Article: 29599
Subject: Re: Virtex ambit support
From: Muzaffer Kal <muzaffer@dspia.com>
Date: 28 Feb 2001 06:10:58 GMT
Links: << >>  << T >>  << A >>
Kelvin CHEUNG/żΰ/ia  <cheungkw@solomon-systech.com> wrote:

>Hi,
>
>We are looking for Virtex library for Ambit to do synthesis (alf or tlf).  However, what we can find is only synopsys .db files.  Please help.
>
>Thanks.
>
>Kelvin

Ambit is strictly an ASIC synthesis tool. I don't believe it supports
any FPGA devices. You're much better off with Synplicity tools for
Virtex anyway.

Muzaffer

FPGA DSP Consulting
http://www.dspia.com



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