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Messages from 29750

Article: 29750
Subject: Re: SRAM fpga cell
From: Utku Ozcan <ozcan@netas.com.tr>
Date: Wed, 07 Mar 2001 16:17:59 +0200
Links: << >>  << T >>  << A >>
Tim Boescke wrote:

> > Does Xilinx plan to use the single transistor SRAM? See <www.mosysinc.com> for
> more info about it.
>
> About about checking out the page byself ?
>
> The mosys 1T sram is dram with a clever refresh scheme. Nothing that could
> be used in a FPGA.

As a counterexample, will it be technologically possible to have
reconfigurable FPGA-like control system in DRAMs, so that
we can get rid of RDRAM, SDRAM, EDO, ZBT etc.? :)

Utku



Article: 29751
Subject: ERROR in Xilinx softaware !
From: "Seb C" <Seb@stien.bizland.com>
Date: Wed, 07 Mar 2001 14:41:10 GMT
Links: << >>  << T >>  << A >>
HI,

Someone answer to my question but i don't understand exactly,  i've an error
after the beginning of the implementation, the software say to me, input or
output PDA missing, or miss as'save', what is PDA or how i can repair this
error, because all pins are connected !!

SEB

--

****************************
Seb@stien.bizland.com
****************************



Article: 29752
Subject: Re: Programming a CPLD
From: Bertram Geiger <bgeiger@aon.at>
Date: Wed, 07 Mar 2001 18:37:20 +0100
Links: << >>  << T >>  << A >>
"A. dhermies" schrieb:
> 
> i used the x-checker with xc9572PC44
> and ..it doesn't work well.
> JTAG is not good! (The IDcode is wrong!)
> But the xchecker was good with a virtex...
> 
> I used my home made // cable, and it was the same... Even with a new chip!
> 
> Can the PC be the cause of this problem?
> 
> I don't think I have done mistakes on the board, and electric signals are visible on logic analyser...
> Can someboy help me?
> thank you.

Once i faced problems with different LPT Modes, try a more conservative
one

regards  Bertram


-- 
Bertram Geiger,  bgeiger@aon.at
HTL Bulme Graz-Goesting - AUSTRIA

Article: 29753
Subject: Re: ERROR in Xilinx softaware !
From: Tim Jaynes <tim.jaynes@xilinx.com>
Date: Wed, 07 Mar 2001 10:56:10 -0800
Links: << >>  << T >>  << A >>
Hello Sir,
What you probably mean is that the Input/Output PADs are missing, which would
result in your entire design getting trimmed out during map.
There's a switch in ngdbuild (-a) that inserts IO pads on all top-level ports.
Ensure that the switch is turned on if your synthesis tool does not do this
insertion for you.  The switch can also be set in the GUI in the translate
section of the implementation options.
Hope this helps.
Regards,
Tim

Seb C wrote:

> HI,
>
> Someone answer to my question but i don't understand exactly,  i've an error
> after the beginning of the implementation, the software say to me, input or
> output PDA missing, or miss as'save', what is PDA or how i can repair this
> error, because all pins are connected !!
>
> SEB
>
> --
>
> ****************************
> Seb@stien.bizland.com
> ****************************


Article: 29754
Subject: Re: SRAM fpga cell
From: Austin Lesea <austin.lesea@xilinx.com>
Date: Wed, 07 Mar 2001 12:44:45 -0800
Links: << >>  << T >>  << A >>
Utku,

The DRAM process is different from the CMOS process, and making an IC with logic and
DRAM is a significant challenge (foundries and companies have failed trying to do
so).  One can not take advantage of the latest technology, and one finds oneself a few
years behind (i.e. death of company to be late!!!)

Moore's Law goes: 0.18 -> 0.15u -> 0.12u -> 0.10u -> 0.07u -> ???

If you are not making silicon at the tiny end by now....it may be too late for you as
a chip vendor.

When it is a standard offered process (DRAM + logic), or even a prototype process that
is available from a foundry in the world, we will be ready,

Austin

Utku Ozcan wrote:

> Tim Boescke wrote:
>
> > > Does Xilinx plan to use the single transistor SRAM? See <www.mosysinc.com> for
> > more info about it.
> >
> > About about checking out the page byself ?
> >
> > The mosys 1T sram is dram with a clever refresh scheme. Nothing that could
> > be used in a FPGA.
>
> As a counterexample, will it be technologically possible to have
> reconfigurable FPGA-like control system in DRAMs, so that
> we can get rid of RDRAM, SDRAM, EDO, ZBT etc.? :)
>
> Utku


Article: 29755
Subject: Re: More detailed Spartan II CLB drawings?
From: Neil Franklin <neil@franklin.ch.remove>
Date: 07 Mar 2001 22:08:22 +0100
Links: << >>  << T >>  << A >>
Eric Smith <eric-no-spam-for-me@brouhaha.com> writes:

> Is there any document that gives more detailed logic drawings of
> the Spartan II CLBs?

Get the Virtex data sheet (Virtex are bitstream-identical with
Spartan-II, for equivalent sizes, so the CLB is identical):

http://www.xilinx.com/partinfo/ds003.pdf

Page 7, Figure 5 is what you want to look at.


>  The description and diagram in the data sheet
> are sort of, well, spartan.

:-)


> I'm trying to figure out whether I can do certain things like
> simultaneously route the carry out both to the carry-in of the CLB above
> *and* to the GRM or to the CLB on the right.

Yes, both of these connections are fixed wired actually.


> These details aren't considered proprietary trade secrets, are they?

No. They are published.


--
Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/
Hacker, Unix Guru, El Eng FH/BSc, Sysadmin, Roleplayer, LARPer, Mystic

Article: 29756
Subject: Re: How to get Xilinx FPGA demo board?
From: "Austin Franklin" <austin@dark99room.com>
Date: Wed, 7 Mar 2001 16:08:39 -0500
Links: << >>  << T >>  << A >>
> Laurent for Amontec
> www.amontec.com
> -----------------------------------
> Amontec introduces a new easy PCI development system.
> Build your own PCI board in 2 weeks! A reality with Amontec.

I went to that web site, and there was really no real information on this
'product'.  The products section said 'We are working on this page.", and
the front page, though it mentioned this PCI product, has no links that I
could find for any more information.  Perhaps I am looking in the wrong
place, would you mind posting more information on this 'product'?





Article: 29757
Subject: Re: More detailed Spartan II CLB drawings?
From: Eric Smith <eric-no-spam-for-me@brouhaha.com>
Date: 07 Mar 2001 14:49:33 -0800
Links: << >>  << T >>  << A >>
Chris Dunlap <cdunlap@xilinx.com> writes:
> You can always look in FPGA editor.  Nothing can be left out there.  If its
> routed or routable, its there.

I don't seem to have an FPGA editor.  Is it supposed to be available
in WebPACK ISE, or is it only in the "real" software?

Thanks!
Eric

Article: 29758
Subject: CHES 2001 registration!
From: Christof Paar <christof@ece.wpi.edu>
Date: Wed, 7 Mar 2001 20:22:05 -0500
Links: << >>  << T >>  << A >>
The CHES registration is up and running. You can go to the CHES main page
at
         www.chesworkshop.org

and download the registration form.

A list with hotels with special CHES rates will become available very
soon.

Regards,  Christof

PS: For those who want to make travel plans: The CHES 2001 program starts
on the morning of Monday, May 14, with pre-registration on Sunday evening.
CHES ends on Wednesday, May 16, at NOON.


! WORKSHOP ON CRYPTOGRAPHIC HARDWARE AND EMBEDDED SYSTEMS (CHES 2001) !
!                  Paris, France, May 13-16, 2001                     !
!                       www.chesworkshop.org                          !

***********************************************************************
                 Christof Paar,  Assistant Professor
          Cryptography and Information Security (CRIS) Group
      ECE Dept., WPI, 100 Institute Rd., Worcester, MA 01609, USA
fon:(508) 831 5061  email: christof@ece.wpi.edu   
fax:(508) 831 5491  www: http://www.ece.wpi.edu/People/faculty/cxp.html
***********************************************************************


Article: 29759
Subject: Re: Parallel Port EPP
From: edick@hotmail.com (Richard Erlacher)
Date: Thu, 08 Mar 2001 04:55:21 GMT
Links: << >>  << T >>  << A >>
While the approach that's described in the some of these other posts
is sound, I've found it's easier and more convenient to form a
boundary between the PC/EPP port farther into the logic than has been
suggested.  The port decoding can be combinatorially done, with the
exception of the handshake timing which requires only two flip-flops
in order to generate a valid RDY signal.  If you use transparent
latches for the data and addresses in your primary interface, the
downstream registers (edge-triggered with the decoded port signals)
will always have "at least plenty" of setup and hold time because you
use the rising edge of RDY to clock them and data is always valid
before the occurrence of the first strobe (nDS, nAS, nWS). That
reduces the logic, ensures you have sufficient setup, and since you're
latched, you have essentially infinite hold time.  The EPP standard
that's been floating around for some time is paced to match the ISA
transfer rates, so timing is exceedingly generous.  

There's no telling what the behavior of the true PCI EPP will be,
though and it may require a mite more care.  

Dick


On Mon, 05 Mar 2001 10:11:55 +0100, Marc Reinert
<reinert@tu-harburg.de> wrote:

>I' like to use a CPLD/FPGA (Xilinx) to receive data from the parallel
>port (EPP-mode) of my PC.
>
>Is it a good style to react direct on the edges of the port signals (e.
>g. adress/data strobes) or would it be better to use a fast PLD-Clock to
>sample the port and then to evaluate the signals in a clocked logic?
>
>Marc
>
>


Article: 29760
Subject: Spartan II: POWERDOWN MODE WAS DELETED!!!
From: "Dan Rudolf" <drudolf@voyager.net>
Date: Thu, 8 Mar 2001 04:52:40 -0800
Links: << >>  << T >>  << A >>
We designed a product around the Spartan II PWDN (powerdown) pin and are in production. I just downloaded a new version of the data sheet and found that Xilinx deleted all reference to the PWDN pin on 11/02/00 from all the datasheets. We are screwed if this is true. Anyone have any info? There is nothing in the answers database.

Article: 29761
Subject: Re: Spartan II: POWERDOWN MODE WAS DELETED!!!
From: Dave Vanden Bout <devb@xess.com>
Date: Thu, 08 Mar 2001 08:11:41 -0500
Links: << >>  << T >>  << A >>
Dan Rudolf wrote:

> We designed a product around the Spartan II PWDN (powerdown) pin and are in production. I just downloaded a new version of the data sheet and found that Xilinx deleted all reference to the PWDN pin on 11/02/00 from all the datasheets. We are screwed if this is true. Anyone have any info? There is nothing in the answers database.

My distributor told me a few months ago that the power-down pins were being removed from Spartan2 and the modification and production ramp-up time for the modified chip was the reason for their shortage.  It's anecdotal, but it correlates with your experience.  I wasn't monitoring the Xilinx announcements on Spartan2 but I assume
they made it known well in advance that this change was coming, although I expect you have a very different opinion on that.


--
|| Dr. Dave Van den Bout   XESS Corp.               (919) 387-0076 ||
|| devb@xess.com           2608 Sweetgum Dr.        (800) 549-9377 ||
|| http://www.xess.com     Apex, NC 27502 USA   FAX:(919) 387-1302 ||



Article: 29762
Subject: Re: Spartan II: POWERDOWN MODE WAS DELETED!!!
From: Ray Andraka <ray@andraka.com>
Date: Thu, 08 Mar 2001 13:20:03 GMT
Links: << >>  << T >>  << A >>
You're screwed.  The powerdown is only in the ES (engineering sample) parts.  I
thought I had seen something in the answers database about a year ago on it.
Can't find it right now though.  The database page is not responding.  IIRC,
there was a yield issue.  Perhaps it is related to the delay in availability of
parts.  

Dan Rudolf wrote:
> 
> We designed a product around the Spartan II PWDN (powerdown) pin and are in production. I just downloaded a new version of the data sheet and found that Xilinx deleted all reference to the PWDN pin on 11/02/00 from all the datasheets. We are screwed if this is true. Anyone have any info? There is nothing in the answers database.

-- 
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com  or http://www.fpga-guru.com

Article: 29763
Subject: Re: SRAM fpga cell
From: krw@btv.ibm.com (Keith R. Williams)
Date: Thu, 08 Mar 2001 13:39:11 GMT
Links: << >>  << T >>  << A >>
On Wed, 07 Mar 2001 12:44:45 -0800, Austin Lesea
<austin.lesea@xilinx.com> wrote:

>Utku,
>
>The DRAM process is different from the CMOS process, and making an IC with logic and
>DRAM is a significant challenge (foundries and companies have failed trying to do
>so).  One can not take advantage of the latest technology, and one finds oneself a few
>years behind (i.e. death of company to be late!!!)
>
>Moore's Law goes: 0.18 -> 0.15u -> 0.12u -> 0.10u -> 0.07u -> ???
>
>If you are not making silicon at the tiny end by now....it may be too late for you as
>a chip vendor.
>
>When it is a standard offered process (DRAM + logic), or even a prototype process that
>is available from a foundry in the world, we will be ready,

Well...

http://www.chips.ibm.com/products/asics/products/edram/index.html

Bring cash. ;-)

----
  Keith R. Williams
  IBM Microelectronics
  (however, not speaking for IBM - don't do ASICs)


Article: 29764
Subject: Re: More detailed Spartan II CLB drawings?
From: "Brian Davis" <brimdavis@nospam.aol.com>
Date: Thu, 8 Mar 2001 05:43:29 -0800
Links: << >>  << T >>  << A >>
Eric Smith wrote:
>Chris Dunlap <cdunlap@xilinx.com> writes:
>> You can always look in FPGA editor. Nothing can be left out there. If its
>> routed or routable, its there.
>
>I don't seem to have an FPGA editor. Is it supposed to be available
>in WebPACK ISE, or is it only in the "real" software?
>

   WebPACK 3.2WP3.0 includes neither the FPGA Editor nor the
 Xilinx Design Language (XDL) ASCII <-> NCD conversion utility.
 Other than not being able to see what the CLB's look like, 
 these omissions also make it very difficult to find and work 
 around the inevitable tool bugs.

 ( But it's free! )

> Is there any document that gives more detailed logic drawings of
> the Spartan II CLBs?

   Other than the slice drawing in the Virtex datasheet, slightly
 more information can also be found in the 3.x Libraries Guide 
 "Design Elements" chapters, under MULT_AND, XORCY, and MUXCY. 
 ( Unfortunately, the section titled  "Carry Logic in Other 
 Architectures" in the "Attributes, Constraints, and Carry Logic" 
 chapter is also quite spartan, consisting of only a paragraph or 
 so for Spartan-II).

Brian Davis

Article: 29765
Subject: Re: Spartan II: POWERDOWN MODE WAS DELETED!!!
From: "Dan Rudolf" <drudolf@xilinx.com>
Date: Thu, 8 Mar 2001 06:33:45 -0800
Links: << >>  << T >>  << A >>
WE ARE SCREWED!!!!!
I found a solution record:
http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=10500
We have been using the production XC2S150's with the power down since September. 
I am REALLY pissed at Xilinx because we went through a large amount of back and forth on exactly how much power the chip would use during powerdown because it was very important in our project. We finally got them to commit on a number and then looking at the real parts it was about 10X less. We were fat dumb and happy..... until today.
Dan

Dan Rudolf
Sapphire Computers, Inc.
(937) 767-1062

Article: 29766
Subject: GSM Baseband Chipset??
From: "news.pavilion.net" <chris@goldgroup.co.uk>
Date: Thu, 8 Mar 2001 15:32:21 -0000
Links: << >>  << T >>  << A >>
Hi,
Is there anyone I can talk to about FPGA development for GSM baseband
chipsets??
please respond to chris@goldgroup.co.uk

Regards
Chris



Article: 29767
Subject: Re: SRAM fpga cell
From: Austin Lesea <austin.lesea@xilinx.com>
Date: Thu, 08 Mar 2001 08:16:41 -0800
Links: << >>  << T >>  << A >>
Keith,

Thanks.

I sat in on the presentation from IBM to Xilinx.  The 0.18u is already two years old, but
the .11u does look interesting.

 http://www.xilinx.com/prs_rls/ibmpartner.htm

I suppose if you actually read all the press releases, and read between the lines, one
could almost guess at where things might be going.

It is pretty wild, that is for sure.

Austin


"Keith R. Williams" wrote:

> On Wed, 07 Mar 2001 12:44:45 -0800, Austin Lesea
> <austin.lesea@xilinx.com> wrote:
>
> >Utku,
> >
> >The DRAM process is different from the CMOS process, and making an IC with logic and
> >DRAM is a significant challenge (foundries and companies have failed trying to do
> >so).  One can not take advantage of the latest technology, and one finds oneself a few
> >years behind (i.e. death of company to be late!!!)
> >
> >Moore's Law goes: 0.18 -> 0.15u -> 0.12u -> 0.10u -> 0.07u -> ???
> >
> >If you are not making silicon at the tiny end by now....it may be too late for you as
> >a chip vendor.
> >
> >When it is a standard offered process (DRAM + logic), or even a prototype process that
> >is available from a foundry in the world, we will be ready,
>
> Well...
>
> http://www.chips.ibm.com/products/asics/products/edram/index.html
>
> Bring cash. ;-)
>
> ----
>   Keith R. Williams
>   IBM Microelectronics
>   (however, not speaking for IBM - don't do ASICs)


Article: 29768
Subject: Problem with Xilinx 3.3-sp7
From: "Mike H." <mikeh@spamlessimageproc.com>
Date: Thu, 8 Mar 2001 17:51:11 -0000
Links: << >>  << T >>  << A >>
Hello everybody,

I just installed Xilinx 3.3i Service Pack 7 for Alliance-PC,
and it crashes every time I use the mapper on Virtex-E parts.
Seems to be OK on Spartan.

I get the good ol' Windows error box and a message:
"protection fault in module LIBLMCIRCUIT.DLL".

Doesn't matter if I execute the mapper from command
prompt or the flow engine. It stops at exactly the same
point, after "Reading NGD file...".

Funny thing is, my colleague installed the exact same
upgrade on his (identical) PC and it works just fine.

I've done (several!) clean installs from the original
CDs, upgrading through 3.1, 3.2sp5, 3.3sp6 etc
and every version works perfectly OK until
service pack bloody 7 which crashes consistently
in the MAP.

Anybody any ideas? Have I got the wrong version of
MFC42.DLL or some such thing????

Thanks

Mike H.




Article: 29769
Subject: Foundation RLOC - help!
From: =?iso-8859-1?Q?Pawe=B3?= J. Rajda <pjrajda@uci.agh.edu.pl>
Date: Thu, 08 Mar 2001 19:20:43 +0100
Links: << >>  << T >>  << A >>
I made simple design: put two COMPCM8 macros, attached
RLOC attributes to them (let's say: R0C0.S0 and R10C0.S0),
then I created a Macro Symbol from this schematic, put the
macro onto top schematic, attached an RLOC_ORIGIN
attribute (R10C10), and run the implementation.
During MAP I got 32 errors like:
ERROR:Map:1 - "RLOC" suffix on MUXCY_L symbol "H1/$I51/$1I1710" (output
   signal=H1/$I51/$1I1710/O) conflicts with one higher in the design.
and a final error:
ERROR:Map:52 - Problem encountered processing RPMs.

What am I doing wrong with RLOC's ?

Regards,
Pawel J. Rajda


Article: 29770
Subject: Foundation ISE Evaluation Kit - how to order?
From: Eric Smith <eric-no-spam-for-me@brouhaha.com>
Date: 08 Mar 2001 10:47:32 -0800
Links: << >>  << T >>  << A >>
Has anyone managed to get (or at least order) a Foundation ISE Evaluation
Kit?  According to a Xilinx press release of 21-Feb-2001, it is available
free for a 60-day trial period.  But there's no part number given, and
my distributor hasn't heard of it.

Thanks!
Eric

Article: 29771
Subject: Re: Foundation ISE Evaluation Kit - how to order?
From: Eric Smith <eric-no-spam-for-me@brouhaha.com>
Date: 08 Mar 2001 10:50:04 -0800
Links: << >>  << T >>  << A >>
I wrote:
> Has anyone managed to get (or at least order) a Foundation ISE Evaluation
> Kit?  According to a Xilinx press release of 21-Feb-2001, it is available

I should have included the URL:

http://www.xilinx.com/prs_rls/0111iseeval.htm

Article: 29772
Subject: Fanout
From: ritchie99_uk@yahoo.com (=?iso-8859-1?q?peter=20ritchie?=)
Date: 8 Mar 2001 23:22:52 +0100
Links: << >>  << T >>  << A >>
Hi all

target Xilinx FPGA.

If a signal is routed through the longline, does the
high fanout of this signal, affect its final speed, or
no ?
Say a transpose filter structure , the input is
broadcasted to all the multpliers, i know this
architecture is more optimised, at least in term of
area, than the direct form, but will this long line
broadcast not affect the final performance ?

If we have a high  fanout signal coming from  the CLB
output. How far the degradation will be in function of

of the fanout. can this output be swicthed to the
longline ?


                   <~> Peter <~>
 

__________________________________________________
Do You Yahoo!?
Get email at your own domain with Yahoo! Mail. 
http://personal.mail.yahoo.com/

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Posted from web1602.mail.yahoo.com [128.11.23.202] 
via Mailgate.ORG Server - http://www.Mailgate.ORG

Article: 29773
Subject: Re: Problem with Xilinx 3.3-sp7
From: Ray Andraka <ray@andraka.com>
Date: Thu, 08 Mar 2001 22:25:24 GMT
Links: << >>  << T >>  << A >>
Have you tried more than one design?  Could be something in your design the
mapper doesn't like.

"Mike H." wrote:
> 
> Hello everybody,
> 
> I just installed Xilinx 3.3i Service Pack 7 for Alliance-PC,
> and it crashes every time I use the mapper on Virtex-E parts.
> Seems to be OK on Spartan.
> 
> I get the good ol' Windows error box and a message:
> "protection fault in module LIBLMCIRCUIT.DLL".
> 
> Doesn't matter if I execute the mapper from command
> prompt or the flow engine. It stops at exactly the same
> point, after "Reading NGD file...".
> 
> Funny thing is, my colleague installed the exact same
> upgrade on his (identical) PC and it works just fine.
> 
> I've done (several!) clean installs from the original
> CDs, upgrading through 3.1, 3.2sp5, 3.3sp6 etc
> and every version works perfectly OK until
> service pack bloody 7 which crashes consistently
> in the MAP.
> 
> Anybody any ideas? Have I got the wrong version of
> MFC42.DLL or some such thing????
> 
> Thanks
> 
> Mike H.

-- 
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com  or http://www.fpga-guru.com

Article: 29774
Subject: Re: Spartan XL & Spartan II Slave Serial Configuration
From: Vikram Pasham <Vikram.Pasham@xilinx.com>
Date: Thu, 08 Mar 2001 16:07:29 -0800
Links: << >>  << T >>  << A >>
Brian,

Try isolating INIT and DONE pins of Spartan-II and Spartan-XL devices. This helps in debugging daisy chain configurations and we can figure out which device is failing configuration by monitoring INIT pins
separately. It seems like you are able to configure the Spartan-XL device but not Spartan-II.

Spartan-II devices configuration starts after it sees the 32-bit sync word (0xAA995566). Probe the DOUT of Spartan-XL to see if its passing this sync word onto Spartan-II device.

You may also try using a 4.7Kohm resistor on INIT and 300 ohm resistor on DONE pin of the
Spartan-II device. Another good resource would be to check out Configuration problem solver
on Xilinx support website at  http://support.xilinx.com/support/troubleshoot/psolvers.htm

Hope this helps !!!

-Vikram

Brian Carruthersq wrote:

> I have an application that uses a 95144XL as an interface from firmware to program a XCS40XL and a XC2S150 in Slave serial mode.
>
> The Spartan XL is the lead device in the daisy chain to the Spartan II. The bitstreams for the two devices are combined using the prom generator. After the firmware has sent all of the configuration data the DONE line stays low, and the INIT stays high.
>
> To verify that the logic in the CPLD and the functionality of the firmware, I removed the Spartan II from my PCB. We re-ran the program to only send the bitstream for the Spartan XL. This works perfectly.
>
> The problem seems to be that when the Spartan II is on the PCB it keeps the DONE low.
>
> The configuration for the Spartan II is set so that the DONE has the Active pullup option selected.
>
> Any suggestions that you may have would be appreciated.




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