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Messages from 29775

Article: 29775
Subject: Re: More detailed Spartan II CLB drawings?
From: Kent Orthner <korthner@hotmail.nospam.com>
Date: 09 Mar 2001 10:13:32 +0900
Links: << >>  << T >>  << A >>

Hey, Eric.

Seeing as you don't have the FPGA Editor, I'd try emailing Xilinx, 
asking for the JBits package.  There's a email address you have to 
send your reauest to, then they ask you a question or two, and 
then give you access to the package.

Part of the JBits package includes an explanation of th Virtex/
Spartan-II architacture.  It's not as detailed as FPGA editor, but 
it's much better than the databook.

HTH,
-Kent


Eric Smith <eric-no-spam-for-me@brouhaha.com> writes:
> Is there any document that gives more detailed logic drawings of
> the Spartan II CLBs?  The description and diagram in the data sheet
> are sort of, well, spartan.
> 
> I'm trying to figure out whether I can do certain things like
> simultaneously route the carry out both to the carry-in of the CLB above
> *and* to the GRM or to the CLB on the right.  Figure 3 in the data sheet
> shows a slice, but it has big unexplained blocks like "Carray and Control
> Logic".  Also, the possible routing choices for signals are not obvious.
> 
> The text talks about the F5 and F6 multipliexers, but they don't appear
> in the drawing at all.
> 
> These details aren't considered proprietary trade secrets, are they?
> That would make it hard for me to figure out how to best design for
> this part.

Article: 29776
Subject: JBits on Red Hat 7.0? (was Re: More detailed Spartan II CLB drawings?)
From: Eric Smith <eric-no-spam-for-me@brouhaha.com>
Date: 08 Mar 2001 18:11:47 -0800
Links: << >>  << T >>  << A >>
Kent Orthner <korthner@hotmail.nospam.com> writes:
> Seeing as you don't have the FPGA Editor, I'd try emailing Xilinx, 
> asking for the JBits package.  There's a email address you have to 
> send your reauest to, then they ask you a question or two, and 
> then give you access to the package.

OK, I've done that.  This brings up my next question:  has
anyone successfully installed and run JBits 2.5 on Red Hat Linux 7.0?

Xilinx says they test JBits with the Sun JDK 1.2.2.  However, JDK 1.2.2
won't run on Red Hat 7.0, and Sun recommends using JDK 1.3 instead.  So I
installed JDK 1.3, but when I try to install JBits, I get:

  % /usr/java/jdk1.3/bin/java JBits2_5.class
  Exception in thread "main" java.lang.NoClassDefFoundError: JBits2_5/class
  %

I thought maybe the problem was not having the JDK bin directory in my
PATH, so I added that, but I get the same results.

Any idea what might be wrong?

Thanks!
Eric

Article: 29777
Subject: Re: Foundation ISE Evaluation Kit - how to order?
From: Vikram Pasham <Vikram.Pasham@xilinx.com>
Date: Thu, 08 Mar 2001 20:14:51 -0800
Links: << >>  << T >>  << A >>
The evaluation kit is available for free through Xilinx distributors.
Check with your local distributor and if need further info refer
http://www.xilinx.com/products/software/ise_eval.htm

-Vikram
Xilinx Applications.


Eric Smith wrote:

> I wrote:
> > Has anyone managed to get (or at least order) a Foundation ISE Evaluation
> > Kit?  According to a Xilinx press release of 21-Feb-2001, it is available
>
> I should have included the URL:
>
> http://www.xilinx.com/prs_rls/0111iseeval.htm


Article: 29778
Subject: Re: Fanout
From: Austin Lesea <austin.lesea@xilinx.com>
Date: Thu, 08 Mar 2001 20:17:17 -0800
Links: << >>  << T >>  << A >>

--------------7475764B730FED8AD0CDEDBF
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

Peter,

In the 4K family, this is taken into account during place and route in
order to meet the constraints.  You do not have to think about how we
implement the route: you do have to place constraints on it so the
software knows what to do.

The trace report then tells you what is happening, in the worst of all
possible combinations of voltage, temperature, and process.

In order to make the software run faster (which it does every time we
update it), we also designed the Virtex architecture to have less delay
variation with load (more buffered paths).

You still have to set your constraints!

This has reached the complete endpoint in Virtex II where all
interconnect is buffered.  There is still a secondary effect of loading,
but it is now much less, and easier to model.

Austin

peter ritchie wrote:

> Hi all
>
> target Xilinx FPGA.
>
> If a signal is routed through the longline, does the
> high fanout of this signal, affect its final speed, or
> no ?
> Say a transpose filter structure , the input is
> broadcasted to all the multpliers, i know this
> architecture is more optimised, at least in term of
> area, than the direct form, but will this long line
> broadcast not affect the final performance ?
>
> If we have a high  fanout signal coming from  the CLB
> output. How far the degradation will be in function of
>
> of the fanout. can this output be swicthed to the
> longline ?
>
>                    <~> Peter <~>
>
>
> __________________________________________________
> Do You Yahoo!?
> Get email at your own domain with Yahoo! Mail.
> http://personal.mail.yahoo.com/
>
> --
> Posted from web1602.mail.yahoo.com [128.11.23.202]
> via Mailgate.ORG Server - http://www.Mailgate.ORG

--------------7475764B730FED8AD0CDEDBF
Content-Type: text/html; charset=us-ascii
Content-Transfer-Encoding: 7bit

<!doctype html public "-//w3c//dtd html 4.0 transitional//en">
<html>
Peter,
<p>In the 4K family, this is taken into account during place and route
in order to meet the constraints.&nbsp; You do not have to think about
how we implement the route: <i>you do have to place constraints</i> on
it so the software knows what to do.
<p>The trace report then tells you what is happening, in the worst of all
possible combinations of voltage, temperature, and process.
<p>In order to make the software run faster (which it does every time we
update it), we also designed the Virtex architecture to have less delay
variation with load (more buffered paths).
<p>You still have to set your constraints!
<p>This has reached the complete endpoint in Virtex II where all interconnect
is buffered.&nbsp; There is still a secondary effect of loading, but it
is now much less, and easier to model.
<p>Austin
<p>peter ritchie wrote:
<blockquote TYPE=CITE>Hi all
<p>target Xilinx FPGA.
<p>If a signal is routed through the longline, does the
<br>high fanout of this signal, affect its final speed, or
<br>no ?
<br>Say a transpose filter structure , the input is
<br>broadcasted to all the multpliers, i know this
<br>architecture is more optimised, at least in term of
<br>area, than the direct form, but will this long line
<br>broadcast not affect the final performance ?
<p>If we have a high&nbsp; fanout signal coming from&nbsp; the CLB
<br>output. How far the degradation will be in function of
<p>of the fanout. can this output be swicthed to the
<br>longline ?
<p>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
&lt;~> Peter &lt;~>
<br>&nbsp;
<p>__________________________________________________
<br>Do You Yahoo!?
<br>Get email at your own domain with Yahoo! Mail.
<br><a href="http://personal.mail.yahoo.com/">http://personal.mail.yahoo.com/</a>
<p>--
<br>Posted from web1602.mail.yahoo.com [128.11.23.202]
<br>via Mailgate.ORG Server - <a href="http://www.Mailgate.ORG">http://www.Mailgate.ORG</a></blockquote>
</html>

--------------7475764B730FED8AD0CDEDBF--


Article: 29779
Subject: Re: Problem with Xilinx 3.3-sp7
From: Nicolas Matringe <nicolas.matringe@IPricot.com>
Date: Fri, 09 Mar 2001 09:04:43 +0100
Links: << >>  << T >>  << A >>
"Mike H." wrote:
> 
> Hello everybody,
> 
> I just installed Xilinx 3.3i Service Pack 7 for Alliance-PC,
> and it crashes every time I use the mapper on Virtex-E parts.
> Seems to be OK on Spartan.
> 
> I get the good ol' Windows error box and a message:
> "protection fault in module LIBLMCIRCUIT.DLL".

Hi
I got a similar problem last week. I can't remember exactly what error I
got but I traced it to the -c option of the mapper. If I didn't use it
it worked fine.
I haven't tried another design to see if it passed

-- 
Nicolas MATRINGE           IPricot European Headquarters
Conception electronique    10-12 Avenue de Verdun
Tel +33 1 46 52 53 11      F-92250 LA GARENNE-COLOMBES - FRANCE
Fax +33 1 46 52 53 01      http://www.IPricot.com/

Article: 29780
Subject: Re: Problem with Xilinx 3.3-sp7
From: "Mike H." <mikeh@spamlessimageproc.com>
Date: Fri, 9 Mar 2001 09:17:45 -0000
Links: << >>  << T >>  << A >>

"Ray Andraka" <ray@andraka.com> wrote in message news:3AA8080D.EF078DAA@andraka.com...
> Have you tried more than one design?  Could be something in your design the
> mapper doesn't like.


Yes, I've tried 3 or 4 different designs, all of which were
working perfectly OK with the previous software release.
Plus, I've compiled the exact same design on my PC (crashes)
and on my colleagues PC (works OK).

I'm pretty sure it's one of these damn Microsoft DLL
issues - I had the same problem a year or so ago,
but I can't remember what I did to fix it!

For now, I'm sticking with 3.3sp6 which works OK.

MH.



Article: 29781
Subject: $HOT JOBS$ ASIC / FPGA / VLSI designers needed - Canada
From: "PROCOM" <derekw@procom.ca>
Date: Fri, 9 Mar 2001 08:48:57 -0500
Links: << >>  << T >>  << A >>
Our client is the leading provider of highly integrated silicon solutions
that enable broadband digital transmission of voice, video, and data. Using
proprietary technologies and advanced design methodologies, the company
designs, develops and supplies integrated circuits for a number of the most
significant broadband communications markets, including the markets for
cable set-top boxes, cable modems, high-speed local, metropolitan and wide
area networks, home networking, Voice over Internet Protocol (VoIP),
residential broadband gateways, direct broadcast satellite and terrestrial
digital broadcast, optical networking, digital subscriber lines (xDSL) and
wireless communications.

They are currently seeking ASIC Designers with the following...

Required Skills and Experiences:

BSEE or equivalent; MSEE preferred, plus 5+ years' of VLSI hardware design
experience.
Position requires working knowledge of Verilog and Synopsys.
Experience with back-end CAE, layout tools, 3D, video, and DSP is a plus.


Responsibilities:

Responsibilities include: definitions of the molecules specifications based
on the system specification; RTL development and debugging, test bench
development; design validation as part of an overall system, system
integration; synthesis of the RTL at a certain clock speed; Implementation
of the test strategy, scan insertion, ATPG test vectors generation.


PROCOM: Established in 1978, Professional Computer Consultants Group Ltd.
(Procom) is a national leader in the provision of Computer personnel on a
contract
and full-time basis. Our clients are comprised of the largest national and
international corporations that utilize technical resources extensively
across a wide range of disciplines. In the Financial Post (March 1999)
Procom was ranked as the 6th largest professional Services Company in
Canada. In November of 1999, Procom was named a Regional finalist in Canada'
s 50 Best Managed Private companies. Our track record is proven with more
than 180 consultants servicing Ottawa's high tech community and more than
1600 Procom consultants currently on assignment throughout. North America.
For further information on this and other opportunities please visit our web
site at www.procom.ca.

Interested candidates are invited to forward their resumes or questions in
confidence to:



Derek Weber
PROCOM

300 March Rd Suite 600
Kanata, Ontario
K2K-2E2
613-270-9339 x231
613-270-9449 (FAX)

derekw@procom.ca
www.procom.ca





Article: 29782
Subject: Re: Foundation RLOC - help!
From: Ivar <ivar@stantech.dk>
Date: Fri, 9 Mar 2001 05:53:29 -0800
Links: << >>  << T >>  << A >>
Hi
I think that You must add RLOC to each muxcy_L AND change the XOR to
XORCY with its own RLOC. Remember to annotate the design.
best regards
Ivar

Article: 29783
Subject: Re: rising_edge() on virtex
From: Stephan Schirrmann <schirrmann@gmx.de>
Date: Fri, 09 Mar 2001 15:49:05 +0100
Links: << >>  << T >>  << A >>

Nicolas Matringe wrote:

> > ERROR:MapLib:93 - Illegal LOC on symbol "SW1.PAD" (pad
> > signal=SW1) or BUFGP symbol "C15" (output signal=SW1_BUFGPed),
> > IPAD-IBUFG should only be LOCed to GCLKIOB site.
>
> ...
> I think your synthesis tool (FPGA Express ?) automatically inserted the
> global buffer on the clock line. There is a switch somewhere to disable
> this.

Yup, thanx! This was the case. In Xilinx Foundation F3.1i the switch is
located in

->Versions View
->Ver<x>
->ContextMenu "Edit Synthesis Constraints"
->Tab "Ports"
->Column "Global buffer"

Great thank you also goes to Michael Böhnel!

Stephan

Article: 29784
Subject: Spartan-II Evaluation Board
From: Christian Plessl <cplessl@gmx.net>
Date: Fri, 09 Mar 2001 16:49:24 +0100
Links: << >>  << T >>  << A >>
Hi Everybody

I'm looking for an evaluation board for Xlininx Spartan-II FPGAs. Does
any body know where to get a eval board that is not too expensive. 

Something like the XESS boards www.xess.com would be nice, but
unfortunately there is no Board with larger Spartan FPGAs, I'm looking
for a board that provides to least a XC2S50, better XC2S100 or even
larger.

Does anybody have any good pointers to manufacturers, distributors?

Greetings,
Chris

Article: 29785
Subject: Re: Foundation RLOC - help!
From: =?iso-8859-1?Q?Pawe=B3?= J. Rajda <pjrajda@uci.agh.edu.pl>
Date: Fri, 09 Mar 2001 19:18:09 +0100
Links: << >>  << T >>  << A >>
Ivar wrote:

> I think that You must add RLOC to each muxcy_L AND change the XOR to
> XORCY with its own RLOC. Remember to annotate the design.

I don't understand why should I change anything in library macros.
I don't think it's the way...

The problem is more general: I have 3 levels of design (top, mid, bot)
Bot is the compcm8 library macro (with original RLOCs). The macro
is placed on mid level with RLOC attached. This level is converted to
another macro within my design's library and put on the top level with
RLOC_ORIGIN parameters. This gives errors - WHY ?
When I move RLOC_ORIGIN to mid level everything is ok, except...
this is not what I want to do.

Pawel J. Rajda


Article: 29786
Subject: Snug presentation on verification in VHDL and Verilog
From: vhdlcohen@aol.com (VhdlCohen)
Date: 09 Mar 2001 19:44:18 GMT
Links: << >>  << T >>  << A >>
I am pleased to post a copy of my snug 2001 presentation on "Component
Verification by Example".   This paper presents, by example, some of the key
features of the front-end processes for specifying the planning of both the
implementation and verification  of a design to ensure that the
implemented design meets its intended requirements and costs.
Presentation and code is available at my site: http://www.vhdlcohen.com 
under "Models and Papers"
File: verifxmpl.zip. SNUG 2001 Presentation + VHDL approaches + 
              Verilog Code on Verification by example 
              using transaction based methods 

--------------------------------------------------------------------------
------------------------------------------
Ben Cohen     Publisher, Trainer, Consultant    (310) 721-4830
http://www.vhdlcohen.com/                 vhdlcohen@aol.com  
Author of following textbooks: 
* Component Design by Example ... a Step-by-Step Process Using 
  VHDL with UART as Vehicle",  2001 isbn  0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
--------------------------------------------------------------------------
------------------------------------------

Article: 29787
Subject: Re: Spartan-II Evaluation Board
From: Eric Smith <eric-no-spam-for-me@brouhaha.com>
Date: 09 Mar 2001 11:45:13 -0800
Links: << >>  << T >>  << A >>
Christian Plessl <cplessl@gmx.net> writes:
> I'm looking for an evaluation board for Xlininx Spartan-II FPGAs. Does
> any body know where to get a eval board that is not too expensive. 
> 
> Something like the XESS boards www.xess.com would be nice, but
> unfortunately there is no Board with larger Spartan FPGAs, I'm looking
> for a board that provides to least a XC2S50, better XC2S100 or even
> larger.

Burch sells a very inexpensive board with an XC2S200, the BED-SPARTAN2+.
The cost is AU $220, which is approximately US $120.  They are out of
stock of the current version, but will have a new version available on
March 19th.  I've used the old version and am very happy with it.

Article: 29788
Subject: Re: Foundation RLOC - help!
From: "Simon Bacon" <simonb@tile.demon.co.cut_this.uk.>
Date: Fri, 9 Mar 2001 20:24:52 -0000
Links: << >>  << T >>  << A >>

"Pawe³ J. Rajda" <pjrajda@uci.agh.edu.pl> wrote in message
news:3AA91E60.498810E4@uci.agh.edu.pl...

> The problem is more general: I have 3 levels of design (top, mid, bot)
> Bot is the compcm8 library macro (with original RLOCs). The macro
> is placed on mid level with RLOC attached. This level is converted to
> another macro within my design's library and put on the top level with
> RLOC_ORIGIN parameters. This gives errors - WHY ?
> When I move RLOC_ORIGIN to mid level everything is ok, except...
> this is not what I want to do.

Try looking in the EDIF file generated by your netlist software.
This can be a lot of work, but you may be able to spot something
wierd in the EDIF which correlates with the problem.



Article: 29789
Subject: Springboard design contest
From: James Horn <jimhorn@svn.net>
Date: 9 Mar 2001 14:33:01 -0800
Links: << >>  << T >>  << A >>
I just read that Handspring, Xilinx, and Portable Design magazine are
jointly sponsoring a Springboard module design contest.  Details are at
www.xilinx.com/contest.

I don't work for any of the above but can't help but wonder what goodies
will come of it.  There are a lot of sharp CPLD whizzes on this group and
the Springboard design looks straightforward.  Biggest question for me is
- what to design?

Best of luck to all!

Jim Horn, WB9SYN/6 (just enjoy cranking telecom via programmable logic)

Article: 29790
Subject: Using LVDS I/O buffers on Virtex-II
From: "Aldo Mastrosimone" <Aldo.Mastrosimone@usa.xerox.com>
Date: Fri, 9 Mar 2001 17:37:45 -0500
Links: << >>  << T >>  << A >>
Anyone using LVDS I/O on Virtex-II ? We're having trouble getting Edif2NGD
to correctly expand the lower level primitives (IOBUF_LVDS). We're using
Synplicity V6.13, Alliance 3.3i (w/ Service Pack 7). Not sure if we have all
the files we're supposed to. When Edif2NGD fails, we get an error 432. It
appears that it's looking for a .NGO file for the IOBUF_LVDS primitive. Any
ideas ??




Article: 29791
Subject: Re: $HOT JOBS$ ASIC / FPGA / VLSI designers needed - Canada
From: "S. Ramirez" <sramirez@cfl.rr.com>
Date: Sat, 10 Mar 2001 01:06:40 GMT
Links: << >>  << T >>  << A >>
"PROCOM" <derekw@procom.ca> wrote in message
news:98amoj$db1$1@news.igs.net...
> Our client is the leading provider of highly integrated silicon solutions
> that enable broadband digital transmission of voice, video, and data.
Using
> proprietary technologies and advanced design methodologies, the company
> designs, develops and supplies integrated circuits for a number of the
most
> significant broadband communications markets, including the markets for
> cable set-top boxes, cable modems, high-speed local, metropolitan and wide
> area networks, home networking, Voice over Internet Protocol (VoIP),
> residential broadband gateways, direct broadcast satellite and terrestrial
> digital broadcast, optical networking, digital subscriber lines (xDSL) and
> wireless communications.
>
> They are currently seeking ASIC Designers with the following...
>
> Required Skills and Experiences:
>
> BSEE or equivalent; MSEE preferred, plus 5+ years' of VLSI hardware design
> experience.
> Position requires working knowledge of Verilog and Synopsys.
> Experience with back-end CAE, layout tools, 3D, video, and DSP is a plus.
>
>
> Responsibilities:
>
> Responsibilities include: definitions of the molecules specifications
based
> on the system specification; RTL development and debugging, test bench
> development; design validation as part of an overall system, system
> integration; synthesis of the RTL at a certain clock speed; Implementation
> of the test strategy, scan insertion, ATPG test vectors generation.
>
> PROCOM: Established in 1978, Professional Computer Consultants Group Ltd.
> (Procom) is a national leader in the provision of Computer personnel on a
> contract
> and full-time basis. Our clients are comprised of the largest national and
> international corporations that utilize technical resources extensively
> across a wide range of disciplines. In the Financial Post (March 1999)
> Procom was ranked as the 6th largest professional Services Company in
> Canada. In November of 1999, Procom was named a Regional finalist in
Canada'
> s 50 Best Managed Private companies. Our track record is proven with more
> than 180 consultants servicing Ottawa's high tech community and more than
> 1600 Procom consultants currently on assignment throughout. North America.
> For further information on this and other opportunities please visit our
web
> site at www.procom.ca.
>
> Interested candidates are invited to forward their resumes or questions in
> confidence to:
>
> Derek Weber
> PROCOM
>
> 300 March Rd Suite 600
> Kanata, Ontario
> K2K-2E2
> 613-270-9339 x231
> 613-270-9449 (FAX)
>
> derekw@procom.ca
> www.procom.ca

*************************************************************
Derek,
     This is an outstanding ad, espcially compared to some I've seen on
comp.arch.fpga and comp.lang.verilog.
     Keep up the good work and good luck finding the right candidates.
Simon Ramirez, Consultant
Synchronous Design, Inc.
Oviedo, FL  USA




Article: 29792
Subject: Re: Metastability
From: Magnus Homann <d0asta@licia.dtek.chalmers.se>
Date: 10 Mar 2001 02:17:18 +0100
Links: << >>  << T >>  << A >>
Rick Collins <spamgoeshere4@yahoo.com> writes:

> Muzaffer Kal wrote:
> > 
> > On 04 Mar 2001 00:25:08 +0100, Magnus Homann
> > <d0asta@mis.dtek.chalmers.se> wrote:
> > 
> > >Ray Andraka <ray@andraka.com> writes:
> > >
> > >[Simons wisdom deleted]
> > >
> > >> Simon failed to point out that using the state machine as the second
> > >> flip flop should only be done if the possibly metastable signal
> > >> affects only one flip-flop in the state machine.  If if affects more
> > >> than one flip-flop, there is a potential for a metastable event to
> > >> be detected as different levels by the multiple flip-flops that
> > >> depend on its condition.  Simon, I'm sure this was your intention, I
> > >> just wanted to make sure your short response didn't mislead anyone.
> > >
> > >Really? Hmm, the idea is that FF1 would settle within the cycle
> > >time. Now, if it doesn't, does it really matter if one or several of
> > >the statemachines FFs wil go into metastability?
> > >
> > >The idea is that the cycle time will be enough for all metastability
> > >to vanish. If it hasn't, is there anything you can do to save your FSM
> > >from running amok?
> > >
> > >Your advice might be god, but probably mostly due to the fact that having
> > >only one FF after FF1  usaully reduces the routing delay, and
> > >hence increases the available settling time (iff you have the same
> > >cycle time in both cases).
> > >
> > >Comments invited.
> > >
> > >Homann
> > 
> > I think that "two FFs" was just a rule of thumb which ensured a
> > certain MTBF under certain conditions (which are probably not valid in
> > < .25u processes anymore). You can further reduce the probability of
> > metastability by adding more FFs. The metastability never vanishes
> > completely. There is always a non-zero probability that the metastable
> > event will pass through all the FFs. It can be made arbitrarily small
> > though. That's where the MTBF comes from.
> > 
> > Muzaffer
> 
> Homann and Muzaffer,
> 
> The factor that settles metastability is not FFs, but rather time. The
> need for the second FF is a function of the speed of the clock. As
> Homann says, using the second FF separates the metastability settling
> time from the time used for routing and logic prop delay. So you get the
> entire clock cycle for settling. 

My point was that I don't think it matters if the second FF is just
one or if its several copies. Only the time matters between FF1 and FF2(1..n).
At least, it's the most important issue..

Thanks,
Homann
-- 
Magnus Homann, M.Sc. CS & E
d0asta@dtek.chalmers.se

Article: 29793
Subject: Re: Metastability
From: Ray Andraka <ray@andraka.com>
Date: Sat, 10 Mar 2001 04:37:44 GMT
Links: << >>  << T >>  << A >>
It does matter if you've used up most of your clock cycle in routing & logic
delays.  In that case, you leave yourself very little time to resolve the
metastabiltiy, and unequal delays to multiple flip-flops makes it fairly likely
to have the two FF's resolve different levels at the next clock edge.  Time is
critical for metastability, and time propagating to the next FF's doesn't
count.  Depending on the implementation, the metastability in the first flop,
which is guaranteed to happen with an async input, can manifest itself as an
oscillation, a runt pulse, a slow rise/fall time or a delayed edge.  I've even
seen a case (not in an FPGA) where a metastable event triggered a
self-sustaining oscillation that would continue until the register was clocked
again.

It all comes down to clock rate, or more specifically, the slack time before the
data is clocked into the next flip-flop.  If you have plenty of slack, one
flip-flop will usually do it.  If not, then be careful!

Magnus Homann wrote:
> 
>
> My point was that I don't think it matters if the second FF is just
> one or if its several copies. Only the time matters between FF1 and FF2(1..n).
> At least, it's the most important issue..
> 
> Thanks,
> Homann
> --
> Magnus Homann, M.Sc. CS & E
> d0asta@dtek.chalmers.se

-- 
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com  or http://www.fpga-guru.com

Article: 29794
Subject: Re: Metastability
From: Rick Collins <spamgoeshere4@yahoo.com>
Date: Sat, 10 Mar 2001 02:18:28 -0500
Links: << >>  << T >>  << A >>
Magnus Homann wrote:
> 
> Rick Collins <spamgoeshere4@yahoo.com> writes:
> 
> > Muzaffer Kal wrote:
> > >
> > > On 04 Mar 2001 00:25:08 +0100, Magnus Homann
> > > <d0asta@mis.dtek.chalmers.se> wrote:
> > >
> > > >Ray Andraka <ray@andraka.com> writes:
> > > >
> > > >[Simons wisdom deleted]
> > > >
> > > >> Simon failed to point out that using the state machine as the second
> > > >> flip flop should only be done if the possibly metastable signal
> > > >> affects only one flip-flop in the state machine.  If if affects more
> > > >> than one flip-flop, there is a potential for a metastable event to
> > > >> be detected as different levels by the multiple flip-flops that
> > > >> depend on its condition.  Simon, I'm sure this was your intention, I
> > > >> just wanted to make sure your short response didn't mislead anyone.
> > > >
> > > >Really? Hmm, the idea is that FF1 would settle within the cycle
> > > >time. Now, if it doesn't, does it really matter if one or several of
> > > >the statemachines FFs wil go into metastability?
> > > >
> > > >The idea is that the cycle time will be enough for all metastability
> > > >to vanish. If it hasn't, is there anything you can do to save your FSM
> > > >from running amok?
> > > >
> > > >Your advice might be god, but probably mostly due to the fact that having
> > > >only one FF after FF1  usaully reduces the routing delay, and
> > > >hence increases the available settling time (iff you have the same
> > > >cycle time in both cases).
> > > >
> > > >Comments invited.
> > > >
> > > >Homann
> > >
> > > I think that "two FFs" was just a rule of thumb which ensured a
> > > certain MTBF under certain conditions (which are probably not valid in
> > > < .25u processes anymore). You can further reduce the probability of
> > > metastability by adding more FFs. The metastability never vanishes
> > > completely. There is always a non-zero probability that the metastable
> > > event will pass through all the FFs. It can be made arbitrarily small
> > > though. That's where the MTBF comes from.
> > >
> > > Muzaffer
> >
> > Homann and Muzaffer,
> >
> > The factor that settles metastability is not FFs, but rather time. The
> > need for the second FF is a function of the speed of the clock. As
> > Homann says, using the second FF separates the metastability settling
> > time from the time used for routing and logic prop delay. So you get the
> > entire clock cycle for settling.
> 
> My point was that I don't think it matters if the second FF is just
> one or if its several copies. Only the time matters between FF1 and FF2(1..n).
> At least, it's the most important issue..
> 
> Thanks,
> Homann
> --
> Magnus Homann, M.Sc. CS & E
> d0asta@dtek.chalmers.se

As Ray pointed out, metastability is resolved not in the cycle time, but
in the slack time. So the more places you have to route to, the less
slack time you are left with. So what you say is basicially true, you do
have to watch your cycle time vs the routing time. If the routing eats
up too much of the cycle time you will degrade your metastability
resolution. 

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 29795
Subject: Questions about Xilinx Web Pack ISE
From: "llandre" <andmars@tin.it>
Date: Sat, 10 Mar 2001 13:00:11 GMT
Links: << >>  << T >>  << A >>
I have just received the Xilinx Web Pack ISE v. 3.2.
I tried to synthesize the code released by Xilinx itself
associated with an Application Note describing how to
implement an asynchronous FIFO using Spartan II devices.
I have some questions:
1) how to locate the pins? I think I have to use the "attribute"
reserved word, but which is the precise syntax?
2) The code uses some device-dependent components (i.e. BUFGB).
The synthesizer messages say that it generates black-box for these
components. In other words, it seems it can not understant what component
to instantiate. How to solve it (missing libraries???)?

Thanks a lot in advance.

--
llandre
 e-mail : andmars@tin.it
 web    : http://www.dei.unipd.it/~patch






Article: 29796
Subject: Re: Spartan-II Evaluation Board
From: "llandre" <andmars@tin.it>
Date: Sat, 10 Mar 2001 13:08:35 GMT
Links: << >>  << T >>  << A >>


> I'm looking for an evaluation board for Xlininx Spartan-II FPGAs. Does
> any body know where to get a eval board that is not too expensive.
>
> Something like the XESS boards www.xess.com would be nice, but
> unfortunately there is no Board with larger Spartan FPGAs, I'm looking
> for a board that provides to least a XC2S50, better XC2S100 or even
> larger.
>
> Does anybody have any good pointers to manufacturers, distributors?
>
Have a look here: www.insight-electronics.com.
I think they have a board for $130 or something like that, equipped
with XC2S100.

--
llandre
 e-mail : andmarsNOSPAM@tin.it
 web    : http://www.dei.unipd.it/~patch




Article: 29797
Subject: Re: Spartan-II Evaluation Board
From: Simon <simon@unique-id.com>
Date: Sat, 10 Mar 2001 14:15:38 +0000
Links: << >>  << T >>  << A >>
llandre wrote:
> 
> > I'm looking for an evaluation board for Xlininx Spartan-II FPGAs. Does
> > any body know where to get a eval board that is not too expensive.
> >
> > Something like the XESS boards www.xess.com would be nice, but
> > unfortunately there is no Board with larger Spartan FPGAs, I'm looking
> > for a board that provides to least a XC2S50, better XC2S100 or even
> > larger.
> >
> > Does anybody have any good pointers to manufacturers, distributors?
> >
> Have a look here: www.insight-electronics.com.
> I think they have a board for $130 or something like that, equipped
> with XC2S100.

The best I've found is the BurchEd board (XCS200 for $120 US, works
with WebPack). Found no problems :-))

ATB,
	Simon.
-- 
Freedom ? What's that ? (see http://www.domesday.co.uk/ )

Article: 29798
Subject: Re: Metastability
From: rk <stellare@nospamplease.erols.com>
Date: Sat, 10 Mar 2001 13:24:16 -0500
Links: << >>  << T >>  << A >>
Rick Collins wrote:

> As Ray pointed out, metastability is resolved not in the cycle time, but
> in the slack time. So the more places you have to route to, the less
> slack time you are left with. So what you say is basicially true, you do
> have to watch your cycle time vs the routing time. If the routing eats
> up too much of the cycle time you will degrade your metastability
> resolution.

And by a lot.  MTBF is not linear with slack time but exponential.

-----------------------------------------------------------------------
rk                               Micromanaging leads to macro f'ups.
stellar engineering, ltd.        -- Richard Marcinko, Seal Team Six
stellare@erols.com.NOSPAM        
Hi-Rel Digital Systems Design

Article: 29799
Subject: Re: Metastability, Asynchronous Signals, & Asynchronous design
From: rk <stellare@nospamplease.erols.com>
Date: Sat, 10 Mar 2001 13:28:41 -0500
Links: << >>  << T >>  << A >>
glen herrmannsfeldt wrote:

> The old story about Huygens hanging multiple pendulum clocks on the
> same wall and noticing that they would phase lock.

Interesting and a bit ironic.  I note that on the probe to Saturn named
after him, there is a problem since the probe's transmitter and receiver
on the spacecraft can't lock, as the doppler shift wasn't accounted for
properly.

-----------------------------------------------------------------------
rk                               Micromanaging leads to macro f'ups.
stellar engineering, ltd.        -- Richard Marcinko, Seal Team Six
stellare@erols.com.NOSPAM        
Hi-Rel Digital Systems Design



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