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Messages from 30025

Article: 30025
Subject: BG575 socket recommendation?
From: Luke Roth <roth@narn.cse.psu.edu>
Date: Tue, 20 Mar 2001 22:56:39 -0500
Links: << >>  << T >>  << A >>
	After hearing all the whiz-bang new features of the Virtex-II
series, we'd like to migrate our university project over (currently
running original Virtex).  However, BGA packages are beyond our
capabilities.  Does anybody have any recommendations for a
BG575-to-something-reasonable (PGA would be ideal) socket?
	It's too bad Xilinx is making things more difficult for those of
us with limited resources.  Nothing that we shouldn't be able to work
around, though.
	Thanks,
	Luke


Article: 30026
Subject: Looking for Skew information
From: Kent Orthner <korthner@hotmail.nospam.com>
Date: 21 Mar 2001 15:35:41 +0900
Links: << >>  << T >>  << A >>
Hi folks.

I'm stuck using 5 clocks in a Spartan-II! <gasp>  Sadly, 
none of these clocks are multiples of another, so I really
do need to use 5.  I'm planning to use the 5th clock as a 
clock for some input pins, and then a little bit of logic 
that moves the data to another clock domain (through a FIFO 
or something.)

I plan to put all of the 5th clock domain logic in the very 
upper left corner of the FPGA (from the FPGA Editor Point 
of view).  The input data will come in from the left side, 
and the pin for the 5th clock will come in the top, near the 
middle of the little cluster of logic.  this way, I can take 
advantage of those long low skew lines.  

I've thrown together a quick test of just the 5th clock part, 
instantiating 4 IBUFS & 4 BUFGs (so that my test doesn't 
end up using the clock buffers when it gets optimized.), 
and putting it through it's paces.  When it's all said and done, 
I get the warning (as I should) that I'm using non-dedicated 
clock resources, and the timing analyzer tells me my Tsetup and
Thold w.r.t. Clock 5.

Then, when I run the trace tool with the -skew option, 
"trce -skew design.ngd -o outfile.twr", the timing report
doesn't have any skew information.  The 5th clock is driving a 
counter as well as some flip-flops, so it can't have been simply 
optimized out.  Any suggestions?

Also, when I select the "Race Conditions" box in the Timing 
analyzer GUI, it doesn't seem to affect the resulting report 
any.  Does that mean that there are no race-related problems?

Thanks in advance,
-Kent

Article: 30027
Subject: Re: TBUFs in Virtex and later chips, going out of fashion, what instead
From: "Jan Gray" <jsgray@acm.org>
Date: Tue, 20 Mar 2001 22:40:20 -0800
Links: << >>  << T >>  << A >>
"Ray Andraka" <ray@andraka.com> wrote in message
news:3AB811ED.3883949B@andraka.com...
> The problem with the CLB muxes is that they don't match the pitch of the
carry
> chain, so If I have a set of counters for instance that I want to address
to
> read onto a common bus, it is a royal pain in the patoot without the
Tbufs.
> It's a good thing there is more routing in these chips!

Right. The various MUXFx's are of little or no use in my adder-heavy
datapaths (e.g. a <96-slice, >80 TBUF, 16-bit RISC CPU for Virtex).

For such designs, which extensively use TBUFs for wide/bus-oriented muxes,
it is hard for me to believe that the area, delay, and power of a
*dedicated* *full-custom* TBUF are inferior to the area, delay, and power of
the same topology using inter-CLB interconnect, plus CLB-local interconnect,
plus 4-LUTs.

Instead I like to believe that the *weighted proportion* of CLBs that use
TBUFs in the mix of test designs (that I assume Xilinx uses to validate and
optimize its next generations of tools and silicon) is low, so that across
the spectrum of designs, TBUF resources are almost always wasted silicon.
This is especially plausible if most such test designs use HDL synthesis,
which do not infer many TBUFs.  If so, then a good architecture design
system might indeed determine that the optimal number of TBUFs per CLB is
... epsilon (arbitrarily close to zero).


Anyway, V-II is here, so how shall we make the most of it?  As I wrote last
time, one important family of circuits (particularly add followed by mux)
can be done properly in just one LUT per bit (in Virtex and Virtex-II), if
Xilinx enhances TRCE (and timing-driven PAR) to address the stated false
path situation.

THIS IS IMPORTANT, because if TRCE is NOT so enhanced, this important
circuit trick is almost unusable, because TRCE (and presumably timing-driven
PAR) think each such mux delay is a whole adder delay.

Austin or Peter, what do you think?  [By the way, thanks: it is great to
hear the Xilinx perspective.  Imagine the deafening silence otherwise.  See
also the cluetrain manifesto (cluetrain.com) thesis #84 :-)]

Jan Gray, Gray Research LLC




Article: 30028
Subject: Re: TBUFs in Virtex and later chips, going out of fashion, what instead
From: Rick Collins <spamgoeshere4@yahoo.com>
Date: Wed, 21 Mar 2001 03:10:29 -0500
Links: << >>  << T >>  << A >>
Kolja Sulimma wrote:
> But wait: Everybody feels happier if he has a reason to complain so they discounted
> the equivalent gate count metric, and now we have a reason to complain again.

You may be on to something! I know that I hate having to back calculate
the gate counts to figure out how to compare today's chips to
yesterday's chip (that I am designing in tomorrow!). 


-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 30029
Subject: Re: Do I need to tie unused CPLD pins to GND?
From: kfalser@REMOVETHISdurst.it (Klaus Falser)
Date: Wed, 21 Mar 2001 08:10:51 GMT
Links: << >>  << T >>  << A >>
On Tue, 20 Mar 2001 08:45:38 -0800, Arthur <> wrote:

>Hello -
>
>  There is a fitter option labelled "User Programmable Grounds" that will help you. When selected, it ties all unused IO pins to ground internally so you don't need to terminate them externally.
>
>  Regards,
>  Arthur

In my understanding this option is tought for having additional 
GND pins and therefore improve ground bounce and other awful 
effects.

As for EVERY chip, EVERY unused should be tied to a defined 
and valid level, usually ground. This is for not damaging 
the pins (and probabely the chip) if someone is touching 
them accidentially (ESD).
Another reason, but I don't know if it applies to Xilinx chips, 
is that a invalid level on a input (and remember, this pins are
inputs and outputs simultaneously), may create a large shunt 
current, since the upper and the lower transistor in the 
input structure are on simultaneously.

I would suggest to connect all unused pins to ground and use 
the above mentioned option too.
If you need to preserve some pins for future use, the 
PROHIBIT option should work now.

Hope this helps
	Klaus  

Falser Klaus
R&D Electronics Department
Company	: Durst Phototechnik AG
	Vittorio Veneto Str. 59
	I-39042 Brixen
Voice	: +0472/810235
	: +0472/810111
FAX	: +0472/830980
Email	: kfalser@IHATESPAMdurst.it 

Article: 30030
Subject: Re: IRDY/TRDY (was Re: More detailed Spartan II CLB drawings?)
From: Kolja Sulimma <kolja@bnl.gov>
Date: Wed, 21 Mar 2001 09:15:52 +0100
Links: << >>  << T >>  << A >>
> O.k now this one's sorted on to the next magic PCI question. In the bitgen args
> list there is a set of  global clock parameters called Gclkdel0-3. I've been
> assuming/wondering for some time if this is to do with meeting PCI66MHz setup
> timing. The give-away is the comment line:
>
> ``You should not use this option unless instructed by Xilinx''
>
> Any ideas ?

Sure. This one is simple.
All we have to do is get instructions from Xilinx.
At least, that's what the tools say :-)

Kolja


Article: 30031
Subject: Re: IRDY/TRDY (was Re: More detailed Spartan II CLB drawings?)
From: Kolja Sulimma <kolja@bnl.gov>
Date: Wed, 21 Mar 2001 09:17:56 +0100
Links: << >>  << T >>  << A >>

Thats the same function, but your formulation ist better optimized and
easier to read ;-)

Eric Crabill wrote:

> Hi,
>
> You may want to double check that, I think it should be:
>
> PCI_CE <= I2 or (not TRDY# and not I3) or (not IRDY# and not I1);

> > In other words:
> > PCI_CE <= I2 or (not TRDY and not I3) or (not IRDY and not I1 and
not I2);


Article: 30032
Subject: Re: TOA measurement
From: "Michal Kvasnicka" <m.kvasnicka@era.cz>
Date: Wed, 21 Mar 2001 09:21:07 +0100
Links: << >>  << T >>  << A >>
Because my main interest is in passive location (TDOA, TOA) of the emitters.
That's all...

Michal
"Jerry Avins" <jya@ieee.org> pÝse v diskusnÝm prÝspevku
news:3AB79CB2.D0EB0A82@ieee.org...
> Michal Kvasnicka wrote:
> >
>   ...
> >
> > Radar pulse can be approximated by trapezoidal (symmetric or asymmetric)
> > pulse wit the following parameters:
> > pulse width = 0.5 - 500us (50% amplitude level)
> > rise time = 20-100ns
> > fall time = 20-200ns
> > sample interval = 1 - 10ns
> > Pulse repetition interval = 1 - 5000us
> >
>   ...
>
> Why is the width (and shape) unknown? Where is the transmitter? Can you
> sample the outgoing pulses and match them up with the returns?
>
> Jerry
> --
> Engineering is the art of making what you want from things you can get.
> -----------------------------------------------------------------------



Article: 30033
Subject: Re: Looking for Skew information
From: Magnus Homann <d0asta@mis.dtek.chalmers.se>
Date: 21 Mar 2001 11:08:27 +0100
Links: << >>  << T >>  << A >>
Kent Orthner <korthner@hotmail.nospam.com> writes:

> Then, when I run the trace tool with the -skew option, 
> "trce -skew design.ngd -o outfile.twr", the timing report
> doesn't have any skew information.  The 5th clock is driving a 
> counter as well as some flip-flops, so it can't have been simply 
> optimized out.  Any suggestions?

Are you sure? If you get a detailed report, it should have a line in
the slack calculation that says "clock skew".

> Also, when I select the "Race Conditions" box in the Timing 
> analyzer GUI, it doesn't seem to affect the resulting report 
> any.  Does that mean that there are no race-related problems?

That check box is sufficient to do skew calculations also. Race conditions
seems hard to get, I had to hand-route a design to provoke a race
condition. 

I guess you are fine, if your timing constraints are OK.

Homann
-- 
Magnus Homann, M.Sc. CS & E
d0asta@dtek.chalmers.se

Article: 30034
Subject: Re: Jobs....?
From: hmurray-nospam@megapathdsl.net (Hal Murray)
Date: Wed, 21 Mar 2001 10:20:50 -0000
Links: << >>  << T >>  << A >>
In article <ueEt6.82688$tP3.1305003@news1.rdc1.bc.home.com>,
 "Raintech Consulting Limited" <resumes@raintech.bc.ca> writes:
>Can one post jobs for design engineers here?

You can, but I would be a lot happier if you didn't.
[I'll also complain to your ISP if you harvest my
email address and spam me directly.  I get one every
month or two.]

The (proposed) charter that I found didn't say "no jobs",
but it didn't encourage them either.  (That was probably
written long before jobs postings became a problem worth
mentioning.)

Think about it for a minute.  If you can post your jobs here
then so can every other headhunter.  Pretty soon we'll get
flooded.

If you want to contribute the the group it would be fine if
your posts included a short signature with "we need design
engineers" and your URL and phone number.



In case you aren't aware, recruiters have a very bad
reputation on usenet.  See
  http://www.eyrie.org/~eagle/writing/rant.html

-- 
These are my opinions, not necessarily my employeers.  I hate spam.


Article: 30035
Subject: Re: Jobs....?
From: "Simon Bacon" <simonb@tile.demon.co.cut_this.uk>
Date: Wed, 21 Mar 2001 12:12:32 -0000
Links: << >>  << T >>  << A >>
The usually accepted formulation is to post a pointer to
a web site.

Something like "For FPGA desgn work look at www.fobar.com/jobs_here"
After all, some of could be looking...

>  "Raintech Consulting Limited" <resumes@raintech.bc.ca> writes:
> >Can one post jobs for design engineers here?





Article: 30036
Subject: Re: TOA measurement
From: "Michal Kvasnicka" <mkvasnicka@volny.cz>
Date: Wed, 21 Mar 2001 15:34:26 +0100
Links: << >>  << T >>  << A >>
Dear Juri,

everything what did you write down is OK, but my problem is "passive"
location (TDOA multilateration without sending whole pulse train to the
central station) not standard radar measurement. So, the transmitted signal
is, in general, unknown for me. I know only some apriori information
(regarding transmitted signal) which mostly play role of some boundaries
regarding received signal shape.

I am looking for algorithm which is able to define some unique reference
point for each pulse and this reference point will be used for precise TOA
measurement.

If you could help me with this problem I will be really very happy.

Best regards, Michal

----- Original Message -----
From: "Juri Kanevski" <kanevski@comsys.ntu-kpi.kiev.ua>
To: "Michal Kvasnicka" <m.kvasnicka@era.cz>
Sent: Tuesday, March 20, 2001 4:05 PM
Subject: Re: TOA measurement


Dear Michal,

The correlation is the general method to increase the signal-noise ratio
for any periodical signals.
It is no matter what kind of shape they have.
If you want to find a signal you must know what you have to find.
Usually one finds the signal which
repeates some original stencil.
The radar sends a signal and receives it but noised and with exchanged
shape.
The correlation is found between sent and received signals.
When the sent signal is trapezoid then the correlation is triangle.
Consider the target is stationar one (unmoved).
when we send 1000 impulses with 1 ms period,
then if we weight the received signal by the trapezoid,
shifted by i sampling cycles, and add it to the i-th accumulator
each 1 ms,
then after 1000 additions in the i-th accumulator the signal will
increase in 1000 times,
but the noise will increase in only 30 times.
Here i represent the delay of the signal.
and in j (j=+-1,2,k)accumulator the resulting signal will be less,
and in l (|l|>j) accumulator the signal will be zeroed,
where 2k is the impulse width.

But when the sent signal is pseudorandom one then the correlation is a
delta function,
and the signal to noise ratio will be dramatically higher then for
trapezoid.

Thats all that I wanted to say.

Regards,
A.Ser.


Michal Kvasnicka wrote:
>
> You are talking about correlation, but in previous messages I said that
the
> model pulse (asymmetric trapezoidal pulse with unknown pulse width and
rise
> or fall time variations) is more or less uknown.
>
> What kind of correlation you have in mind? Please, could you be so kind
and
> describe your idea more detailed?
>
> Thanks in advance,
>
> Michal




Article: 30037
Subject: Re: Do I need to tie unused CPLD pins to GND?
From: Ray Andraka <ray@andraka.com>
Date: Wed, 21 Mar 2001 15:12:17 GMT
Links: << >>  << T >>  << A >>
The xilinx unused pins do not have to be tied off.  The internal pullups or
pulldowns get turned on on unused pins to tie them safely to a voltage plane.

Klaus Falser wrote:
> 
> On Tue, 20 Mar 2001 08:45:38 -0800, Arthur <> wrote:
> 
> >Hello -
> >
> >  There is a fitter option labelled "User Programmable Grounds" that will help you. When selected, it ties all unused IO pins to ground internally so you don't need to terminate them externally.
> >
> >  Regards,
> >  Arthur
> 
> In my understanding this option is tought for having additional
> GND pins and therefore improve ground bounce and other awful
> effects.
> 
> As for EVERY chip, EVERY unused should be tied to a defined
> and valid level, usually ground. This is for not damaging
> the pins (and probabely the chip) if someone is touching
> them accidentially (ESD).
> Another reason, but I don't know if it applies to Xilinx chips,
> is that a invalid level on a input (and remember, this pins are
> inputs and outputs simultaneously), may create a large shunt
> current, since the upper and the lower transistor in the
> input structure are on simultaneously.
> 
> I would suggest to connect all unused pins to ground and use
> the above mentioned option too.
> If you need to preserve some pins for future use, the
> PROHIBIT option should work now.
> 
> Hope this helps
>         Klaus
> 
> Falser Klaus
> R&D Electronics Department
> Company : Durst Phototechnik AG
>         Vittorio Veneto Str. 59
>         I-39042 Brixen
> Voice   : +0472/810235
>         : +0472/810111
> FAX     : +0472/830980
> Email   : kfalser@IHATESPAMdurst.it

-- 
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com

Article: 30038
Subject: Trouble with assigning output pins on Xilinx (foundation)
From: Benjamin Hoffman <hoffman@uwplatt.edu>
Date: Wed, 21 Mar 2001 10:16:34 -0600
Links: << >>  << T >>  << A >>
Hello,
I am working on an assignment for school. We need to design a simple
computer using a Xilinx FPGA.  I am using the student version of
Foundation 2.1.  I am starting small by simply trying to program a
simple AND circuit. It will have 2 inputs and 1 output. I am using the
schematic layout. I captured the circuit and it simulated just fine, but

whenever I try to do the next "Implimentation" step it hangs up. Even if

I let it run over night it never finishes, but it does not lock up as I
can stop it at anytime.  This does not happen if I don't type LOC=p60 in

the properties of the OBUF, but then it does me no good if I can not
specify the pin assignments. I did notice that assigning LOC=p19 and
LOC=p20 to the IBUFs does not cause it to hang up during implimentation,

only when I assign outputs. Does anyone have any idea what is happening
with this?
Thank you,
Ben Hoffman




Article: 30039
Subject: backup FLEX10K
From: "luigi funes" <fuzzy8888@hotmail.com>
Date: Wed, 21 Mar 2001 16:58:47 GMT
Links: << >>  << T >>  << A >>
Hi!
I'm looking for keeping the whole internal state (ff and ram)
during power off in Altera Flex10K devices, or, at least,
to preserve the configuration without reload it at every
power up.
I know is possible to keep the configuration in Xilinx fpga devices
with a low voltage battery, but I don't found these informations
for Altera ram-based pld.
Someone tried this possibility?

Luigi




Article: 30040
Subject: Re: Trouble with assigning output pins on Xilinx (foundation)
From: PeteD <pdowell@mil-x-dig.com>
Date: Wed, 21 Mar 2001 17:20:06 GMT
Links: << >>  << T >>  << A >>
Try assigning LOC to the pads (both IPAD and OPAD), not the buffers.
-- 
Remove "-x-" from address to e-mail

Article: 30041
Subject: Re: Trouble with assigning output pins on Xilinx (foundation)
From: Philip Freidin <philip@fliptronics.com>
Date: Wed, 21 Mar 2001 10:07:41 -0800
Links: << >>  << T >>  << A >>
There was a problem like this with Xilinx's F1.5 student edition.
Maybe this is similar?

The solution was to go to their web site and download the
updates. In your case, the F2.1 updates.

Philip

On Wed, 21 Mar 2001 10:16:34 -0600, Benjamin Hoffman <hoffman@uwplatt.edu>
wrote:
>Hello,
>I am working on an assignment for school. We need to design a simple
>computer using a Xilinx FPGA.  I am using the student version of
>Foundation 2.1.  I am starting small by simply trying to program a
>simple AND circuit. It will have 2 inputs and 1 output. I am using the
>schematic layout. I captured the circuit and it simulated just fine, but
>
>whenever I try to do the next "Implimentation" step it hangs up. Even if
>
>I let it run over night it never finishes, but it does not lock up as I
>can stop it at anytime.  This does not happen if I don't type LOC=p60 in
>
>the properties of the OBUF, but then it does me no good if I can not
>specify the pin assignments. I did notice that assigning LOC=p19 and
>LOC=p20 to the IBUFs does not cause it to hang up during implimentation,
>
>only when I assign outputs. Does anyone have any idea what is happening
>with this?
>Thank you,
>Ben Hoffman
>
>

Philip Freidin
Fliptronics

Article: 30042
Subject: Re: Do I need to tie unused CPLD pins to GND?
From: Peter Alfke <peter.alfke@xilinx.com>
Date: Wed, 21 Mar 2001 10:41:03 -0800
Links: << >>  << T >>  << A >>
Some corrections, see below:

Klaus Falser wrote:

> As for EVERY chip, EVERY unused should be tied to a defined
> and valid level, usually ground. This is for not damaging
> the pins (and probabely the chip) if someone is touching
> them accidentially (ESD).

That's not the reason commonly given, but it helps, of course. Note that all
(our) inputs and outputs are protected with two diodes, one to ground, the other
one to Vcc or as a Zener diode,
protecting against positive spikes.

>
> Another reason, but I don't know if it applies to Xilinx chips,
> is that a invalid level on a input (and remember, this pins are
> inputs and outputs simultaneously), may create a large shunt
> current, since the upper and the lower transistor in the
> input structure are on simultaneously.

If the pin floats into the middle between ground and Vcc, then there is a
certain current, at most a few milliamps per pin. Should be avoided, but is not cathastrophic.
Xilinx pins have a default weak-pull-up resistor for that purpose (only).

Gru▀ nach SŘdtirol!

Peter Alfke, Xilinx Applications


>
>
> I would suggest to connect all unused pins to ground and use
> the above mentioned option too.
> If you need to preserve some pins for future use, the
> PROHIBIT option should work now.
>
> Hope this helps
>         Klaus
>
> Falser Klaus
> R&D Electronics Department
> Company : Durst Phototechnik AG
>         Vittorio Veneto Str. 59
>         I-39042 Brixen
> Voice   : +0472/810235
>         : +0472/810111
> FAX     : +0472/830980
> Email   : kfalser@IHATESPAMdurst.it

Article: 30043
Subject: Re: TBUFs in Virtex and later chips, going out of fashion, what instead
From: Neil Franklin <neil@franklin.ch.remove>
Date: 21 Mar 2001 19:43:36 +0100
Links: << >>  << T >>  << A >>
Austin Lesea <austin.lesea@xilinx.com> writes:

> Juri Kanevski wrote:
>
> > Neil Franklin wrote:
> > >
> > > In Virtex and Spartan-II it is down to 2 TBUFS for the 4 LUT+FF of an
> > > CLB, so only one slice can be routed to them, and even only 1 line for
> > > reading back from TBUF lines.
> > >
> > > In Virtex-II there is even only 2 TBUFs for 8 LUT+FF per CLB. Which
> > >
> > > So I have a question: What is the Xilinx-suggested replacement for TBUFs?
> > > Is one supposed to use MUXes implemented in the CLBs? Is there an other
> > > trick I have not yet stumbled over?
> >
> > And therefore the only solution is
> > to try to do without large multiplexors and shared busses.

Unless I have got many outputs (different logic units) that need
to be selected to go into one input (register file). Then I need an
Mux. Can't avoid it.


> > The way to do without large shared busses in the chip
> > is the stable tendency now and in the future

That is sensible anyway, simply from contention/parallelism
viewpoint. But that can be had by partitioning the TBUF lines (on
Virtex and later chips, not on 3000/4000/5200).


[rearanged to here]

> As the chips scale, driving a 1" long wire became slower and slower (relative
to
> the whole picture).

Assuming an chip-wide bus. With an bus just 5 to 10 CLBs wide (in
XC2S200) they would be quite a bit less than 1" (1/8 to 1/4").


>  Recently we removed TBUF's and replaced them with mux's in
> a few thousands of designs, and without replacing and rerouting, the designs
> were all faster.

This surprises me, given more "wire" (to Mux and away). OTOH if the
Mux is inbetween the target and its nearest source then length may not
be much more. And TBUF section PIPs may be not much faster then GRM PIPs.

Were these comparisons on Virtex-II or also on plain Virtex and
Spartan-II (which is what I am using)?


> TBUF: RIP 200?

That was what I was suspecting. Thanks to get it from the horses mouth.


--
Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/
Hacker, Unix Guru, El Eng HTL/FH/BSc, Sysadmin, Roleplayer, LARPer

Article: 30044
Subject: Re: TOA measurement
From: Jerry Avins <jya@ieee.org>
Date: Wed, 21 Mar 2001 13:48:22 -0500
Links: << >>  << T >>  << A >>
Please satisfy my curiosity about what goes on here. If you know nothing
about the transmitter, what instant do you measure the delay from?

Jerry
-- 
Engineering is the art of making what you want from things you can get.
-----------------------------------------------------------------------
Michal Kvasnicka wrote:
> 
> Dear Juri,
> 
> everything what did you write down is OK, but my problem is "passive"
> location (TDOA multilateration without sending whole pulse train to the
> central station) not standard radar measurement. So, the transmitted signal
> is, in general, unknown for me. I know only some apriori information
> (regarding transmitted signal) which mostly play role of some boundaries
> regarding received signal shape.
> 
> I am looking for algorithm which is able to define some unique reference
> point for each pulse and this reference point will be used for precise TOA
> measurement.
> 
> If you could help me with this problem I will be really very happy.
> 
> Best regards, Michal
> 
  ...

Article: 30045
Subject: Re: backup FLEX10K
From: "Erik Widding" <widding@birger.com>
Date: Wed, 21 Mar 2001 13:56:03 -0500
Links: << >>  << T >>  << A >>
"luigi funes" <fuzzy8888@hotmail.com> wrote in message
news:b55u6.4973$bw6.273124@news.infostrada.it...
> I'm looking for keeping the whole internal state (ff and ram)
> during power off in Altera Flex10K devices, or, at least,
> to preserve the configuration without reload it at every
> power up.
> I know is possible to keep the configuration in Xilinx fpga devices
> with a low voltage battery, but I don't found these informations
> for Altera ram-based pld.

The current draw of an FPGA can typically be modeled as:
    Itotal = Idc + Iac

Where Iac is approximately some constant K * frequency * transitions.  Iac
is zero when the frequency is zero.  Idc is the standby current stated in
the data sheet.  If memory serves, the standby current for 10K parts is less
than 0.5mA.

If you turn off your clocks, then you would only have this standby current
to contend with.  If you can live with 0.5mA (or more specifically what the
data sheet states) then the answer to the question is yes.

The advantage to the Xilinx powerdown mode is that the standby current is
many orders of magnitude lower than 0.5mA.


Regards,
Erik Widding.


--
Birger Engineering, Inc.  --------------------------------  781.481.9233
38 Montvale Ave #260; Stoneham, MA 02180  -------  http://www.birger.com




Article: 30046
Subject: Re: TOA measurement
From: "Michal Kvasnicka" <mkvasnicka@volny.cz>
Date: Wed, 21 Mar 2001 20:31:40 +0100
Links: << >>  << T >>  << A >>
Did you read my previous posts?

+>Time sampling is realized by Rubidium normal (short term stability about
+>10^-12 ) connected with GPS time receiver for long term stability about
+>10^-13 - 10^-15.

TOA is measured as absolute time distributed in the network of the receivers
with accuracy about 1ns. This time is not necessarily synchronized with UTC,
because I need only time difference (TDOA multilateration method for 3-D
target location) TOA_1st station -TOA_2ns station = TDOA_1st2nd, etc.

What now? Any suggestion from your side?

Regards, Michal

"Jerry Avins" <jya@ieee.org> pÝse v diskusnÝm prÝspevku
news:3AB8F776.B4D79B0A@ieee.org...
> Please satisfy my curiosity about what goes on here. If you know nothing
> about the transmitter, what instant do you measure the delay from?
>
> Jerry
> --
> Engineering is the art of making what you want from things you can get.
> -----------------------------------------------------------------------
> Michal Kvasnicka wrote:
> >
> > Dear Juri,
> >
> > everything what did you write down is OK, but my problem is "passive"
> > location (TDOA multilateration without sending whole pulse train to the
> > central station) not standard radar measurement. So, the transmitted
signal
> > is, in general, unknown for me. I know only some apriori information
> > (regarding transmitted signal) which mostly play role of some boundaries
> > regarding received signal shape.
> >
> > I am looking for algorithm which is able to define some unique reference
> > point for each pulse and this reference point will be used for precise
TOA
> > measurement.
> >
> > If you could help me with this problem I will be really very happy.
> >
> > Best regards, Michal
> >
>   ...



Article: 30047
Subject: Re: Senior I/O Designer - Canada
From: "Lee Iovino" <li@wadc.questsyst.com>
Date: Wed, 21 Mar 2001 15:02:23 -0500
Links: << >>  << T >>  << A >>
"Aggressive Meat" sounds like the name of a punk band from New Jersey.

"Tom Burgess" <tom.burgess@home.com> wrote in message
news:3AB46401.CAE847AB@home.com...
> Rick Filipkiewicz wrote:
> >
> > "The PeopleWeb Inc." wrote:
> >
> > > Title:  Senior I/O Designer
> > > Position Type: Permanent
> > > Location: Canada ( Markham, Ontario)
> > > Contact Name: Victoria Lee
> > > Contact E-mail: vickil@thepeoplewebinc.com
> > > ** All Moving expenses are fully covered**
> > >
> >
> > O.k. I'm commuting from Barbados
> >
> > >
> > > We are looking for an aggressive individual that will work within an
> > > integrated design team to craft leading edge I/O design for the next
> > > generation of Rage 3D graphics and multimedia products. A thorough
> > > understanding of the IC design process and tools.
> > >
> >
> > I suppose you need agressive people for Rage graphics
> >
>
> The local Super-Valu had an outdoor sign up for many months:
> "visit our Aggressive Meat Department". I don't know
> what cracked me up most - the images that came to mind
> of rude, pushy butchers harassing customers or the
> aggressive meat itself assaulting them. Or maybe I was
> just amazed that an induhvidual could come up with
> such a dumb slogan.
>
> regards, tom



Article: 30048
Subject: implementing complex datacom protocols
From: "Lee Iovino" <li@wadc.questsyst.com>
Date: Wed, 21 Mar 2001 15:09:02 -0500
Links: << >>  << T >>  << A >>
Does anyone know how to do this?  If so, I represent an Optical Networking
company in Virginia that is building the largest router known to man.  Same
thing Iron Bridge tried to do, but these guys have the funding to get the
job done.  If interested, please contact me at li@wadc.questsyst.com or
800-369-2900.

Experienced FPGA designers will implement complex datacom protocols and take
a design from specification through implementation and debug. Requires a 4
year degree and 4+ years of design experience in the following areas:

HDL coding/synthesis/simulation
High speed memory interfaces
Telecom/datacom buses (PCI, PL4, CSIX)

They need ASIC designers as well, even more urgently.

Thanks for taking time to read this!



Article: 30049
Subject: Re: FFT in FPGAs
From: Tom Dillon <tdillon@dilloneng.com>
Date: Wed, 21 Mar 2001 20:26:00 GMT
Links: << >>  << T >>  << A >>
Rick,

We are doing the preliminary design work for a 2K point FFT taking just =

under 4uS. It will operate on a continuous data stream.

Virtex II is the most obvious choice for this because of the built in=20=

multipliers and block ram.

Feel free to contact me if you need more details.

Regards,

Tom Dillon
Dillon Engineering, Inc.
http://www.dilloneng.com


>>>>>>>>>>>>>>>>>> Original Message <<<<<<<<<<<<<<<<<<

On 3/18/2001, 3:41:40 AM, Rick Collins <spamgoeshere4@yahoo.com> wrote=20=

regarding FFT in FPGAs:


> I am looking at performing real data, fixed point FFTs in an FPGA and =
I
> would like to get some info on the processing time and logic size
> required. The input data is 14 bit, 2048 points. A standard optimizati=
on
> for processing real data is to fold the data into the complex input
> array, so that you only process a 1024 point FFT and then unfold the
> real data in an extra step. We have a DSP available which can do the
> final unfolding step.

> I checked the Altera web site and found info on their megacore functio=
n.
> For a 1K FFT, they use about 3000 LE's and 10 block rams (EABs). They=

> claim the max speed is 90 MHz for 57 uS per block. This is only 3x wha=
t
> I can get from the DSP chip!

> Is the Altera megacore not highly optimized for speed? Are there other=

> cores available that can process the data at a higher clock rate? The=

> data is clocked in at 100 MHz burst rate, if it is fully pipelined and=

> can start another butterfly each 4 clock cycles it should be able to
> process the data in 20 uS. Perhaps that is too much to expect since
> there are log2(N)/2 passes. I would like to process the block in 20 uS=
.
> At that point the processing time becomes insignificant in the overall=

> process. Is that too much to expect from a hardware solution without
> using a thousand dollar chip?


> --

> Rick "rickman" Collins

> rick.collins@XYarius.com
> Ignore the reply address. To email me use the above address with the X=
Y
> removed.

> Arius - A Signal Processing Solutions Company
> Specializing in DSP and FPGA design      URL http://www.arius.com
> 4 King Ave                               301-682-7772 Voice
> Frederick, MD 21701-3110                 301-682-7666 FAX



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