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Messages from 30250

Article: 30250
Subject: VHDL Test bench
From: iPierre <p_crahes@yahoo.com>
Date: Thu, 29 Mar 2001 11:35:32 -0800
Links: << >>  << T >>  << A >>
Could you drop me some links or examples for VHDL test bench background reading and implementation.

Thanx to everybody !

Article: 30251
Subject: Re: VHDL question
From: Mark Korsloot <M.Korsloot@computer.org>
Date: Thu, 29 Mar 2001 21:36:58 +0200
Links: << >>  << T >>  << A >>
Jean-Marie,

Did you include the signal "autosync" in your port declaration.  If not
(but only declared it as a signal), that would explain why the
synthesizer doesn't generate an input pad for it.

Mark

Kent Orthner wrote:
> 
> Hi, Jean-Marie.
> 
> I tried the following on Fuoundateioin Express v.1 (The synthesizer
> is FPGA Express v3.4), so the setup is a little different than what
> you have.  But there were no problems.  And looking at your code, I
> can't see why you would get that warning.  Maybe it's something in the
> part of your code that you didn't include in your message?  Maybe post
> the entire entity/architecture.
> 
> Hope this helps,
> -Kent
> 
> entity test is
>     port (
>         rxready, autosync : in  bit;
>         syncerr, datamode : out bit
>         );
> end entity test;
> 
> architecture test_a of test is
> begin
> 
> 
>     process(rxready, autosync)
>     begin
>         if rxready = '0' then
>             syncerr <= '1';
>             if autosync = '1' then
>                 datamode <= '0';
>             else
>                 datamode <= '1';
>             end if;
>         else
>             syncerr  <= '0';
>             datamode <= '1';
>         end if;
>     end process;
> 
> end architecture test_a;
> 
> Jean-Marie Bussat <JMBussat@lbl.gov> writes:
> > I have a piece of code but the synthetizer doesn't react as I would
> > expect at first glance. I have to following simple code (rxready and
> > autosync are two input ports and datamode and syncerr are output
> > ports):
> >
> > process(rxready, autosync)
> > begin
> >       if rxready='0' then
> >               syncerr <= '1';
> >               if autosync='1' then
> >                       datamode <= '0';
> >               else
> >                       datamode <= '1';
> >               end if;
> >       else
> >               syncerr <= '0';
> >               datamode <= '1';
> >       end if;
> > end process;
> >
> > When I synthetize it with Fpga Express I got a warning saying
> > that no net is attached to port autosync. I dont understand
> > why and if I modify the code the following way ( I believe that
> > the functionnality is the same ):


Article: 30252
Subject: CLK / STARTUP PB
From: iPierre <p_crahes@yahoo.com>
Date: Thu, 29 Mar 2001 12:16:48 -0800
Links: << >>  << T >>  << A >>
CLK/STARTUP PB with XC4K

##CONFIGURATION :

Iíve got a XC4005XL set on Master Serial Mode (M0=0,M1=0,M2=0)
I program the EEPROM (XC18V256) using the JTAG function of the XChecker cable.
The connection between EEPROM and FPGA are as follow :

FPGA  <->  EEPROM

DIN   <->  D0

CCLK  <->  CLK

/INIT <->  OE(/RST)

DONE  <->  /CE

I pulled up to VCC /INIT and DONE

##PROBLEM and RESULTS

The configuration seams not to be OK or the STARTUP not to complete.(I know that there is an help from Xilix for that but I think the problem comes from other stupid mistakes, see below.)

After loading the config stream in the eeprom and set power off->on all the pins of the fpga are pulled-up, DONE is low and off-course nothing working :o(

If I left /init unconnected all pins of the fpga are set to ground but DONE seams to be at vcc (!)

I use the most simple default data stream configuration, the startup is suppose to be done using the CCLK of the fpga. I didnít specify any user clock (and even any other clock neither RST signal) in my design (!) Do I need one to get the design running ? If yes, how to do it (canít find any info in the XC4k doc) ?

I would appreciate any kind of help.

Thanx,

Pierre.

Article: 30253
Subject: Re: Xilinx Core generator with WebPack ISE
From: "Kirk Saban" <kirk_saban@ins.nospam.memec.com>
Date: Thu, 29 Mar 2001 20:38:41 GMT
Links: << >>  << T >>  << A >>
Matthias,

CoreGen is not included in the free webpack ISE tools, you need to purchase
the ISE software to get access to Core Generator.

Kirk

"Matthias Fuchs" <matthias.fuchs@esd-electronics.com> wrote in message
news:3AC05A2F.459F03DA@esd-electronics.com...
> Hi,
>
> I am currently using Xilinx Foundation software for our FPGAs. Now I
> want to start a Spartan II design using the WebPack ISE software
> package. I want to use the Cores generated with the foundation's core
> generator. How can I do that ? It seems that I have to add the Xilinx
> Coregenerator library. How can I do that ?
>
> Can anybody give me a short advice ?
>
> Matthias
> --
> -------------------------------------------------
> \ Matthias Fuchs                                 \
>  \ esd electronic system design Gmbh              \
>   \ Vahrenwalder StraŖe 205                        \
>    \ D-30165 Hannover                               \
>     \ email: matthias.fuchs@esd-electronics.com      \
>      \ phone: +49-511-37298-0                         \
>       \ fax:   +49-511-37298-68                        \
>        --------------------------------------------------



Article: 30254
Subject: Re: VHDL question
From: Jean-Marie Bussat <JMBussat@lbl.gov>
Date: Thu, 29 Mar 2001 12:47:58 -0800
Links: << >>  << T >>  << A >>
Kent Orthner wrote:
> can't see why you would get that warning.  Maybe it's something in the
> part of your code that you didn't include in your message?  Maybe post
> the entire entity/architecture.

Thanks to all who replied 

I finally found what was the problem.

In fact, I've made a mistake and put a statement that was setting
"datamode" to '1' inconditionnaly in another process.

Since "autosync" was only used to select the state of "datamode", the 
optimizer was right when it decided that "autosync" was useless and
removed it.

This is a design error but it's an authorized vhdl construction that
doesn't lead to an error message like "signal xxx has more than one
driver" because the affectation are made inside two differents 
processes.

So, has a conclusion, it's sometimes better to switch to anoter
subject than staying in front of a screen with the strong feeling
that you are right and that the computer is wrong ;-)

Jean-Marie
 
-- 
  _______________________________________
 |                                       | 
 | Jean-Marie Bussat                     |
 | Lawrence Berkeley National Laboratory |
 | 1 Cyclotron Road - MS 50A-6134        |
 | BERKELEY, CA 94720 - USA              |
 | Email: JMBussat@lbl.gov               |
 | Phone: (510)-486-5687                 |
 | Fax:   (510)-486-5977                 |
 |_______________________________________|

Article: 30255
Subject: FPGA V CPLD
From: "Speedy Zero Two" <dlatter@manorsNOSPAMway.freeserve.co.uk>
Date: Thu, 29 Mar 2001 21:56:24 +0100
Links: << >>  << T >>  << A >>
All,

I've been told that logic designs implemented within FPGA's are more
temperamental than CPLD's.

Any insight ?

Cheers
Dave



Article: 30256
Subject: 8279 keyboard controller in Verilog or VHDL ?
From: "Ivar" <did@vip.[nozpam]cybercity.dk>
Date: Thu, 29 Mar 2001 23:09:14 +0200
Links: << >>  << T >>  << A >>
Where can I find the code to the old 8279 keyboard
controller in Verilog or VHDL ?

Ivar



Article: 30257
Subject: Re: Programmble Logic Sequencer
From: "Austin Franklin" <austin@darkro98om.com>
Date: Thu, 29 Mar 2001 16:12:25 -0500
Links: << >>  << T >>  << A >>

"Michael Boehnel" <boehnel@iti.tu-graz.ac.at> wrote in message
news:3AC364BF.CD97C711@iti.tu-graz.ac.at...
> Not all newsgroup users are experts. I didn't check the details but I like
the
> passionate design of the site.

Design of web site is really good, I agree.  Content appears to be pretty
misinforming though....  In it it states that a "Harvard architecture means
that it doesn't have external address/data/control buses"...which is wrong,
a Harvard architecture is basically separate data and program memory.  That
is one, of quite a few, 'confusing' statements in this write-up.




Article: 30258
Subject: Re: PCI-X core
From: "Jamie Sanderson" <jamie@nortelnetworks.com>
Date: Thu, 29 Mar 2001 16:23:37 -0500
Links: << >>  << T >>  << A >>
"Mark Korsloot" <M.Korsloot@computer.org> wrote in message
news:3AC38D19.471F9D3A@computer.org...
> More importantly: PCI-X has no reads (which are sloooowww), but only
> writes: therefore all PCI-X devices must be able to become bus master.
>
> To get information, you "write" to the "slave" give me some data and the
> slave then "writes" to the "master" "here is your data"
>
> No retries anymore....

I'm not 100% sure here, but I believe you're thinking of I2O, not PCI-X. I'm
looking at the latter's spec right now, and there are definitely reads. I2O
is (I believe) a protocol which can run on top of PCI (among other things).

As to the original question, PCI-X for the Virtex 2 is targeted to run at 66
MHz. See the following page for more info:
http://www.xilinx.com/pci/pci-x.htm.

Cheers,
Jamie



Article: 30259
Subject: Re: FPGA V CPLD
From: "Simon Bacon" <simonb@tile.demon.co.cut_this.uk>
Date: Thu, 29 Mar 2001 22:48:13 +0100
Links: << >>  << T >>  << A >>

"Speedy Zero Two" <dlatter@manorsNOSPAMway.freeserve.co.uk> wrote

> I've been told that logic designs implemented within FPGA's are more
> temperamental than CPLD's.

Nope.  But they are anything from 'bigger' to 'hugely bigger'
so the designs have to be done with more care.  Sort of like
the difference between writing the 'Hello, world' program and
writing a real application.

By 'tempermental', your friend probably meant 'you have to
make sure that the timing checks out', which is undoubtedly
true.  Timing still has to check out for a CPLD, but the CPLD
timing model is simpler than is the case for most FPGAs.

OTOH, you may be claiming that the band of brothers who work on
FPGA designs are a tempermental bunch...






Article: 30260
Subject: Re: Please help a poor student with virtexe
From: iPierre <p_crahes@yahoo.com>
Date: Thu, 29 Mar 2001 14:34:15 -0800
Links: << >>  << T >>  << A >>
It happens that this message appears even if all is correclty configurated. Usually you just have to restart the "programer".

Otherwise, in your case, first of all, as recommended previously, check the pins numbers of the connections with the cable.

Pierre

Article: 30261
Subject: Re: Programmble Logic Sequencer
From: Peter Alfke <peter.alfke@xilinx.com>
Date: Thu, 29 Mar 2001 14:47:37 -0800
Links: << >>  << T >>  << A >>
Passion is good, a lively design is nice ( until the typeface and excessive color
gets irritating ), but the accuracy of the content is much more important.
Let's leave it to Hollywood to create great-looking empty ( or bad ) content.

Peter Alfke, Xilinx Applications
===================================
Michael Boehnel wrote:

> Not all newsgroup users are experts. I didn't check the details but I like the
> passionate design of the site.
>
> Michael


Article: 30262
Subject: Re: Problems with NIC and FlexLM / W2K
From: "C.Schlehaus" <carlhermann.schlehaus@t-online.de>
Date: Fri, 30 Mar 2001 04:45:44 +0200
Links: << >>  << T >>  << A >>
Hi,

thanx for Your's posting, but
I do not have the problem to get the right NIC ID, but Quartus has to.
Meanwhile I tried to find the reason for these threee numbers and I
found a hint in the FAQ at www.globetrotter.com:

* Problem: On Windows NT and 2000, I get the wrong hostid such as 0,
* 0xffffffff, or 3 virtual MAC addresses
* Answer: You need upgrade to a v7.1d+ lmutil or lmtools.

But how to upgrade? You can download the latest version of the files,
but that doesn't changes anything for the FlexLM tool invoked by
Start -> Control -> FlexLM License Manager :-(.

Could You advise me, how to perform this update?

TIA, Carlhermann





Article: 30263
Subject: Re: VHDL Test bench
From: Srinivasan Venkataramanan <srini@realchip.co.in>
Date: Fri, 30 Mar 2001 09:55:28 +0530
Links: << >>  << T >>  << A >>
Hi,
  Visit: http://www.i2.i-2000.com/~stefan/vcourse/html/index.html

Also take a look at VHDL FAQ at http://www.vhdl.org/comp.lang.vhdl

(There is also a book by Janick, see: http://janick.bergeron.com/)

HTH,
Srini

iPierre wrote:
> 
> Could you drop me some links or examples for VHDL test bench background reading and implementation.
> 
> Thanx to everybody !

-- 
Srinivasan Venkataramanan (Srini)
ASIC Design Engineer,
Chennai (Madras), India

Article: 30264
Subject: Re: 8279 keyboard controller in Verilog or VHDL ?
From: "news.hinet.net" <cmlin4@winbond.com.tw>
Date: Fri, 30 Mar 2001 14:58:30 +0800
Links: << >>  << T >>  << A >>
Aldec  active-HDL have

8255 8251  8051 8279 8253 ...

VHDL code

goto there ]


"Ivar" <did@vip.[nozpam]cybercity.dk> wrote in message
news:9a08ab$2va7$1@news.cybercity.dk...
> Where can I find the code to the old 8279 keyboard
> controller in Verilog or VHDL ?
>
> Ivar
>
>



Article: 30265
Subject: Re: Programmble Logic Sequencer
From: Michael Boehnel <boehnel@iti.tu-graz.ac.at>
Date: Fri, 30 Mar 2001 09:37:11 +0200
Links: << >>  << T >>  << A >>
I think there isn't any difference to the way companies are working. They announce a
software, sell it and the user will have to keep track with the updated service
packs. I'm sure Mr. Twyman (like the companies) to his knowledge did his best and
will correct misinformations if he gets the right feedbacks.


Article: 30266
Subject: Re: FPGA V CPLD
From: "Victor Schutte" <victors@mweb.co.za>
Date: Fri, 30 Mar 2001 11:14:36 +0200
Links: << >>  << T >>  << A >>
This reply deviates slightly from your question but these are some of the
answers I give when people ask FPGA vs CPLD questions.

You use the same tools and languages but the end products differ quite a
lot. CPLDs tend to be  faster than FPGAs because of the internal structure.
The signals in an FPGA usually have to travel through various gates, thus
adding delays.

If a CPLD is specified as a 10ns device it indicates the total (minimum)
time from an input to output pin. Example: If you want to build a high freq.
oscillator a CPLD would be the choice(if you are looking at PLDs). Using a
10ns device you can theoretically clock up to 100MHz (one of my friends did
this a few weeks ago)

The delays in an FPGA is specified from gate to gate. If you use a 3ns FPGA
you might think whatever you design  will clock 300MHz but looking
internally at all the different gates the signal has to travel the maximum
frequency drops considerally.  My one CPU design runs on -3 FPGA device but
the final max clock frequency is only 20MHz.

Complexity is another matter. I still think that combinational and state
machine logic needs to be implemented in CPLDs. I did a design for a client
with two concurrent state machines running in an Altera 7064 (+- 1800
gates).  The same design just  will not fit on a 10 000 gate Flex FPGA. The
more combinational logic you have the better a CPLD performs.

When you get to busses, sub components like counters, many concurrent
processes etc... a FPGA is better suited. Example: Implementing a basic
serial UART with prescaler and interrupt output uses about  10% of a
Flex10k10 (+- 1000 gates). The same design barely fits on a MAX7160 (more
than 3500 gates)


Conclusion: If you design FPGA designs for FPGAs and CPLD designs for CPLDs
everything will work without major hickups. If you start to mix designs of
trying to save money by putting everything in one chip  (e.g. DSP function
interfacing to a very high speed bus using a single FPGA) you might find
FPGAs very temperamental.

Some of the newer FPGAs contains CPLD macrocell 'ish  structures (APEX I
think?) that allows CPLD performance in a FPGA device.


My 2 cents worth opinion...

Victor

"Speedy Zero Two" <dlatter@manorsNOSPAMway.freeserve.co.uk> wrote in message
news:9a07ep$el1$1@news6.svr.pol.co.uk...
> All,
>
> I've been told that logic designs implemented within FPGA's are more
> temperamental than CPLD's.
>
> Any insight ?
>
> Cheers
> Dave
>
>



Article: 30267
Subject: HAL-15
From: Rissa Tero <rissa@cs.tut.fi>
Date: Fri, 30 Mar 2001 13:38:23 +0300
Links: << >>  << T >>  << A >>

Hi,

In recent NASA press release FPGA-based hypercomputer
is suggested to be used in NASA's projects.
http://acmb.larc.nasa.gov/olaf/nasapressrel.doc

Is all they promise really possible?

http://dailypress.com/business/stories/06809sy0.htm
http://acmb.larc.nasa.gov/olaf/RNHal.html
http://www.starbridgesystems.com/


--
T.Rissa


Article: 30268
Subject: Re: HAL-15
From: Kolja Sulimma <kolja@prowokulta.org>
Date: Fri, 30 Mar 2001 13:12:58 +0200
Links: << >>  << T >>  << A >>
Years ago there was an article about a planned PC system with the
starbridge technology.

The headline was:

"We put the Hype into Hypercomputing"

The programming model seems to be somewhat similar to the SCORE project
of Berkeleys BRASS project, but this is only a guess as I can not find
any spec of their IADL language or other details of Starbridges
technology on their webpage. Only biz talk.

Having spent some time with BRASS I am sure that reconfigurable
computing has the potential to play a major role in computing in the
future. But I find it hard to believe that Starbridge has software ready
that makes this technology accessible to non FPGA experts.

A more acknowledge company that uses reconfigurable computing in their
supercomputers is SRC

http://www.srccomp.com/products_map.htm

But SRC targets FPGA experts.

CU,
        Kolja

Rissa Tero wrote:

> Hi,
>
> In recent NASA press release FPGA-based hypercomputer
> is suggested to be used in NASA's projects.
> http://acmb.larc.nasa.gov/olaf/nasapressrel.doc
>
> Is all they promise really possible?
>
> http://dailypress.com/business/stories/06809sy0.htm
> http://acmb.larc.nasa.gov/olaf/RNHal.html
> http://www.starbridgesystems.com/
>
> --
> T.Rissa


Article: 30269
Subject: Re: HAL-15
From: "Simon Bacon" <simonb@tile.demon.co.cut_this.uk>
Date: Fri, 30 Mar 2001 12:27:03 +0100
Links: << >>  << T >>  << A >>

"Kolja Sulimma" <kolja@prowokulta.org> wrote
>
> A more acknowledge company that uses reconfigurable computing in their
> supercomputers is SRC
>
> http://www.srccomp.com/products_map.htm

And SRC is Seymour Roger Cray.  This is the company Seymour was
starting up when he rolled his Jeep.






Article: 30270
Subject: Re: HAL-15
From: Rissa Tero <rissa@cs.tut.fi>
Date: Fri, 30 Mar 2001 15:08:30 +0300
Links: << >>  << T >>  << A >>

The SCORE requires a dedicated reconfigurable architecture
(correct me if I'm wrong). SB claims that all this is done
with Virtex FPGAs.

April fool's day being so close, I would have considered
HAL as a joke (appropriate name and all), but I would assume
that NASA would not be involved in a scam(?).

On Fri, 30 Mar 2001, Kolja Sulimma wrote:

> Years ago there was an article about a planned PC system with the
> starbridge technology.
>
> The headline was:
>
> "We put the Hype into Hypercomputing"
>
> The programming model seems to be somewhat similar to the SCORE project
> of Berkeleys BRASS project, but this is only a guess as I can not find
> any spec of their IADL language or other details of Starbridges
> technology on their webpage. Only biz talk.
>
> Having spent some time with BRASS I am sure that reconfigurable
> computing has the potential to play a major role in computing in the
> future. But I find it hard to believe that Starbridge has software ready
> that makes this technology accessible to non FPGA experts.
>
> A more acknowledge company that uses reconfigurable computing in their
> supercomputers is SRC
>
> http://www.srccomp.com/products_map.htm
>
> But SRC targets FPGA experts.
>
> CU,
>         Kolja
>
> Rissa Tero wrote:
>
> > Hi,
> >
> > In recent NASA press release FPGA-based hypercomputer
> > is suggested to be used in NASA's projects.
> > http://acmb.larc.nasa.gov/olaf/nasapressrel.doc
> >
> > Is all they promise really possible?
> >
> > http://dailypress.com/business/stories/06809sy0.htm
> > http://acmb.larc.nasa.gov/olaf/RNHal.html
> > http://www.starbridgesystems.com/
> >
> > --
> > T.Rissa
>
>

--
T.Rissa


Article: 30271
Subject: Reed/Solomon ENcoder
From: Steven Sanders <sanders@imec.be>
Date: Fri, 30 Mar 2001 14:09:36 +0200
Links: << >>  << T >>  << A >>
Hello,

What I`m looking for is a R/S ENcoder with following fixed 
specifications (VHDL, no IP cores or netlists):

n=255
k=239
GF(256)
p(x)=1 + x^2 + x^3 + x^4 + x^8 (DVB standard)
g(x)=(x+alpha^0)...(x+alpha^15)

Does someone have any VHDL, architecture descriptions, references
for this coder?

Thanx in advance!

Steven

Article: 30272
Subject: VIRTEX BLOCK RAM
From: Manjunathan <mnathan@logiceastern.com>
Date: Fri, 30 Mar 2001 06:54:57 -0800
Links: << >>  << T >>  << A >>
Hello Everybody !

    what is the clock to output delay for block ram in virtex-E while performing READ and WRITE operation.

 thanks in advance.

regards,
Manjunathan.

Article: 30273
Subject: Re: Programmble Logic Sequencer
From: "Austin Franklin" <austin@darkro98om.com>
Date: Fri, 30 Mar 2001 11:13:35 -0500
Links: << >>  << T >>  << A >>
> I think there isn't any difference to the way companies are working. They
announce a
> software, sell it and the user will have to keep track with the updated
service
> packs. I'm sure Mr. Twyman (like the companies) to his knowledge did his
best and
> will correct misinformations if he gets the right feedbacks.

I think asking the author to correct it, would entail also getting the
author to understand why it needs correction.  I'm trying to say this as
nicely as I can...




Article: 30274
Subject: Re: VIRTEX BLOCK RAM
From: Peter Alfke <peter.alfke@xilinx.com>
Date: Fri, 30 Mar 2001 09:01:56 -0800
Links: << >>  << T >>  << A >>
2.6 ns for speed grade -7,  2.9 ns for speed grade -6

see Xilinx data book ( 2000 ) page 3-36 , label: Tbcko

when performing a write operation, the output reflects the data being written ( write-before-read )
Virtex-II additionally offers read-before-write as a configuration option.

Peter Alfke, Xilinx Applications
===================================
Manjunathan wrote:

> Hello Everybody !
>
>     what is the clock to output delay for block ram in virtex-E while performing READ and WRITE operation.
>
>  thanks in advance.
>
> regards,
> Manjunathan.




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2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarApr2017

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

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