Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarApr2017

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search

Messages from 30825

Article: 30825
Subject: High resolution time measurement?
From: Jonas Thor <thor.NO@SPAM.sm.luth.se>
Date: Mon, 30 Apr 2001 21:04:49 +0200
Links: << >>  << T >>  << A >>
Hello!

This is a not well defined question, but I'll ask anyway... I want to
measure, with high precision, the time between two rising edges of two
pulses. I have a reference clock, frequency F, of about 5-10 MHz, but
I need measurements much more accurate than 1/F. (The rising edges are
of course asynchronous to the reference clock.)

What can I do in a FPGA get the best precison? What's the best I can
do without a DLL and with a DLL?

Thanks for any advice!

/ Jonas Thor 

Article: 30826
Subject: Re: Need info : Training on ASIC/FPGA
From: Tom <tomcip@concentric.net>
Date: 30 Apr 2001 19:14:49 GMT
Links: << >>  << T >>  << A >>
The only training courses that I am aware of are the ones that are run by
the companies which manufacture programable devices. For example, Xilinx and
Altera have courses which are constantly being held in their bay Area
headquarters. These courses usually run from 2 to 4 days and can cost
several hundred dollars at a minimum.

I, myself, learned programmable logic the old fashioned way, through trial,
error and pain.

Hope this helps.

Tom Cipollone

"A. I. Khan" wrote:

> Hi all !
>
> It would be highly appreciated if anyone can let me know if there is any
> good training course related to " ASIC/FPGA flow" (I know its huge;
> still if there is any that covers important aspects) arranged by any
> Institute around North America.
>
> Thankx,
>
> ______Khan


Article: 30827
Subject: Re: C++ To Gates
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Mon, 30 Apr 2001 20:27:44 +0100
Links: << >>  << T >>  << A >>


Kevin Neilson wrote:
> 
> 
> Converting sequential C to chips:  This is what I don't think is possible
> right now.  I think the people that are designing the C-like syntaxes know
> that they are really just RTL languages, but are intentionally trying to
> create confusion by pretending that code written for a processor can be
> converted to an FPGA.  There is a huge difference between writing code
> specifically for a chip in a C-like syntax and writing "normal" C and then
> converting it to a chip.  But the confusion is created to make managers (who
> aren't all technically the brightest) believe that they can leverage their
> software people for chip design.
> 
> -Kevin
> 
>

Excuse my cynisism but I think what we have here is the natural
extension to ``marketing gates''    called ``marketing languages''. The
next sign of progess along these lines will be the appearance as
examples in these languages of our old favourites the traffic light
controller & the vending machine.

What annoys me most about this is that it distracts attention & academic
resources from the task  of getting the existing HDLs, VHDL/Verilog, to
the next level of abstraction that Magnus has mentioned - behavioural
synthesis.

Article: 30828
Subject: Re: High resolution time measurement?
From: Austin Lesea <austin.lesea@xilinx.com>
Date: Mon, 30 Apr 2001 13:05:37 -0700
Links: << >>  << T >>  << A >>
Jonas,

There is a techique where you phase lock an oscillator to the input
frequency offset by a fixed amount.  You then multiply the offset
frequency with a standard frequency reference that is at the orginal input
frequency (rate).  The lower sideband contains the information.  This can
be implemented in DSP in FPGA's.

The technique is a basic one (30+ years old) developed by NIST in Boulder
Colorado for analog precision phase measurement of the atomic clocks, and
then implemented by clever digital/DSP engineers.

Austin

Jonas Thor wrote:

> Hello!
>
> This is a not well defined question, but I'll ask anyway... I want to
> measure, with high precision, the time between two rising edges of two
> pulses. I have a reference clock, frequency F, of about 5-10 MHz, but
> I need measurements much more accurate than 1/F. (The rising edges are
> of course asynchronous to the reference clock.)
>
> What can I do in a FPGA get the best precison? What's the best I can
> do without a DLL and with a DLL?
>
> Thanks for any advice!
>
> / Jonas Thor


Article: 30829
Subject: Re: High resolution time measurement?
From: "Kevin Neilson" <kevin_neilson@yahoo.com>
Date: Mon, 30 Apr 2001 20:38:03 GMT
Links: << >>  << T >>  << A >>
"Austin Lesea" <austin.lesea@xilinx.com> wrote in message
news:3AEDC591.31379447@xilinx.com...


>
> The technique is a basic one (30+ years old) developed by NIST in Boulder
> Colorado for analog precision phase measurement of the atomic clocks, and
> then implemented by clever digital/DSP engineers.
>
> Austin
>

Boulder rocks.




Article: 30830
Subject: MORE Problems Setting Pins High!
From: vikram m n rao <vmrao@students.uiuc.edu>
Date: Mon, 30 Apr 2001 17:06:33 -0500
Links: << >>  << T >>  << A >>

Hello there Alan,

        I've included an message you posted last week in response to my
post asking how to set certain pins high on my FPGA in order to disable a
microcontroller and RAM.
        I followed your advice on how to do this in Verilog (using the
assignment statement, and BTW I named the outputs 'ramdisable' and
'ucdisable'), and I then setup my UCF file with the following ADDITIONAL
lines:
NET ucdisable LOC=36;
NET ramdisable LOC=65;

but XILINX Foundation is giving me the  following error during
the implementation phase:

"ERROR:OldMap:40 - Bad format for LOC constraint 36 on symbol
"ucdisable.PAD"
   (pad signal=ucdisable).  No such site for this device.  This may also
   indicate that a non-constrainable site (such as a VCC, GND, mode,
   configuration, or other special-purpose pin) has been used as a site
name.
ERROR:OldMap:40 - Bad format for LOC constraint 65 on symbol
"ramdisable.PAD"
   (pad signal=ramdisable).  No such site for this device.  This may also
   indicate that a non-constrainable site (such as a VCC, GND, mode,
   configuration, or other special-purpose pin) has been used as a site
name."


Please let me know if you have a solution for this problem, because the
problem is not Verilog-specific, rather it seems to be related to my UCF.
Thank you for your time.

Sincerely,
Vikram Rao

On Fri, 27 Apr 2001, Alan Nishioka wrote:

> Date: Fri, 27 Apr 2001 12:12:42 -0700
> From: Alan Nishioka <alann@accom.com>
> Newsgroups: comp.arch.fpga, comp.lang.verilog
> Subject: Re: Setting Pins High
>
> vikram m n rao wrote:
>
> > I have an XESS XS40 board, and I need to disable the microcontroller and
> > RAM for my design. According to the XESS FAQ, "All you need to do is
> > program the FPGA such that the RST pin of the microcontroller and the /CS
> > pin of the RAM are pulled high. Since pins 36 and 65 on the FPGA are
> > connected to the RST and /CS pins of the RAM/microcontroller, you just
> > need to program the FPGA to set them hi. This will keep all their pins in
> > the high impedance state."
> >
> > Someone at XESS explained to me how to go about this in VHDL:
> > "In VHDL, you just output a logic 1 on these pins:
> > uc_reset <= '1';
> > ce_n <= '1';
> > Then place the following pin assignments in your UCF file (I assume you
> > are using an XS40 Board):
> > NET uc_reset LOC=P36;
> > NET ce_n  LOC=P65;  "
> >
> > So how do I go about doing this in Verilog? I need to have these 2 pins
> > always high to disable the microcontroller and RAM. I tried
> > defining 2 OUTPUTS in my top-level module, uc_reset and ce_n, and
> > defined them as registers. I then inserted the following code to set them
> > high:
> >
> > always @(posedge clkin) begin
> > uc_reset <= 1;
> > ce_n <= 1;
> > end
> >
> > and I then set the registers to correspond to the appropriate pins in my
> > UCF. But this doesn't seem to work, because I get the following error
> > during the implementation phase:
> > "ERROR:OldMap:40 - Bad format for LOC constraint 36 on symbol
> > "ucdisable.PAD"
> >    (pad signal=ucdisable).  No such site for this device.  This may also
> >    indicate that a non-constrainable site (such as a VCC, GND, mode,
> >    configuration, or other special-purpose pin) has been used as a site
> > name.
> > ERROR:OldMap:40 - Bad format for LOC constraint 65 on symbol
> > "ramdisable.PAD"
> >    (pad signal=ramdisable).  No such site for this device.  This may also
> >    indicate that a non-constrainable site (such as a VCC, GND, mode,
> >    configuration, or other special-purpose pin) has been used as a site
> > name."
> >
> > Am I correct in my approach (defining these as hi @posedge of my main
> > clock)? And it looks as if it will not let me set constraints on these
> > pins, but I have verified (through pinouts and tech people at XESS) that
> > those are the pins to set hi. Any ideas on how to go about this?
> >
> > Vik
>
> In verilog try:
>
> assign uc_reset = 1;
> assign ce_n = 1;
>
> Don't define them as registers, just as outputs.
> Since they are constant, they don't need to be registered on a clock.
>
> The error seems to be some sort of name conflict problem.  Or it may be that
> the synthesizer is optimizing the register out and then having problems with
> the result.
>
> Alan Nishioka
> alan@nishioka.com
>
>
>


Article: 30831
Subject: Re: Multiple state machines in altera AHDL
From: Russell Shaw <rjshaw@iprimus.com.au>
Date: Tue, 01 May 2001 10:15:49 +1000
Links: << >>  << T >>  << A >>


Nial Stewart wrote:
> 
> Russell Shaw wrote:
> >
> > Greg Deuerling wrote:
> > >
> > > In article <3AECBB59.2C68BF6D@iprimus.com.au>, rjshaw@iprimus.com.au says...
> > > > AHDL is *much* better than VHDL.
>       ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
> 
> > > > Max-plus-ii is FREE:)
> > >
> > > Yeh brother, I second that.  VHDL is way to wordy and hard to follow.
> >
> > plus i only put the max-plus CD in my PC on saturday, learnt the lingo,
> > and had the not-trivial design worked out and simulated by sunday
> > night:) Now to make a byte-blaster cable...
> 
> But what happens if you decide to target a Xilinx device?
> (SpartanII devices are cheap, provide a lot of resource
> and the web pack software's free too).

I started off with a $200 xilinx foundation pack (couple of years ago)
and got completely stuffed around when it came to trying to get licence
numbers (whithout having to pay a few more hundred $). Whats more, a
year later, a letter came saying to pay maintenance. I don't mind
paying for sw, but why should i fork out hundreds just to learn
and experiment with it?

I don't think i'll ever use xilinx again. Web-packs are no go, they
can pull the plug at any time. Cypress and altera have the right
idea;) When i get my thing going and sell a few thousand, i think
altera will have got their money back for giving away a few copies
of maxplus...

--
   ___                                           ___
  /  /\                                         /  /\
 /  /__\                                       /  /\/\
/__/   / Russell Shaw, B.Eng, M.Eng(Research) /__/\/\/
\  \  /  Victoria, Australia, Down-Under      \  \/\/
 \__\/                                         \__\/

Article: 30832
Subject: Re: MORE Problems Setting Pins High!
From: Dave Vanden Bout <devb@xess.com>
Date: Mon, 30 Apr 2001 20:39:25 -0400
Links: << >>  << T >>  << A >>
vikram m n rao wrote:

> Hello there Alan,
>
>         I've included an message you posted last week in response to my
> post asking how to set certain pins high on my FPGA in order to disable a
> microcontroller and RAM.
>         I followed your advice on how to do this in Verilog (using the
> assignment statement, and BTW I named the outputs 'ramdisable' and
> 'ucdisable'), and I then setup my UCF file with the following ADDITIONAL
> lines:
> NET ucdisable LOC=36;
> NET ramdisable LOC=65;

I believe you forgot to add the 'P' before the pin numbers.  Try this:

NET ucdisable LOC=P36;
NET ramdisable LOC=P65;



>
>
> but XILINX Foundation is giving me the  following error during
> the implementation phase:
>
> "ERROR:OldMap:40 - Bad format for LOC constraint 36 on symbol
> "ucdisable.PAD"
>    (pad signal=ucdisable).  No such site for this device.  This may also
>    indicate that a non-constrainable site (such as a VCC, GND, mode,
>    configuration, or other special-purpose pin) has been used as a site
> name.
> ERROR:OldMap:40 - Bad format for LOC constraint 65 on symbol
> "ramdisable.PAD"
>    (pad signal=ramdisable).  No such site for this device.  This may also
>    indicate that a non-constrainable site (such as a VCC, GND, mode,
>    configuration, or other special-purpose pin) has been used as a site
> name."
>
> Please let me know if you have a solution for this problem, because the
> problem is not Verilog-specific, rather it seems to be related to my UCF.
> Thank you for your time.
>
> Sincerely,
> Vikram Rao
>
> On Fri, 27 Apr 2001, Alan Nishioka wrote:
>
> > Date: Fri, 27 Apr 2001 12:12:42 -0700
> > From: Alan Nishioka <alann@accom.com>
> > Newsgroups: comp.arch.fpga, comp.lang.verilog
> > Subject: Re: Setting Pins High
> >
> > vikram m n rao wrote:
> >
> > > I have an XESS XS40 board, and I need to disable the microcontroller and
> > > RAM for my design. According to the XESS FAQ, "All you need to do is
> > > program the FPGA such that the RST pin of the microcontroller and the /CS
> > > pin of the RAM are pulled high. Since pins 36 and 65 on the FPGA are
> > > connected to the RST and /CS pins of the RAM/microcontroller, you just
> > > need to program the FPGA to set them hi. This will keep all their pins in
> > > the high impedance state."
> > >
> > > Someone at XESS explained to me how to go about this in VHDL:
> > > "In VHDL, you just output a logic 1 on these pins:
> > > uc_reset <= '1';
> > > ce_n <= '1';
> > > Then place the following pin assignments in your UCF file (I assume you
> > > are using an XS40 Board):
> > > NET uc_reset LOC=P36;
> > > NET ce_n  LOC=P65;  "
> > >
> > > So how do I go about doing this in Verilog? I need to have these 2 pins
> > > always high to disable the microcontroller and RAM. I tried
> > > defining 2 OUTPUTS in my top-level module, uc_reset and ce_n, and
> > > defined them as registers. I then inserted the following code to set them
> > > high:
> > >
> > > always @(posedge clkin) begin
> > > uc_reset <= 1;
> > > ce_n <= 1;
> > > end
> > >
> > > and I then set the registers to correspond to the appropriate pins in my
> > > UCF. But this doesn't seem to work, because I get the following error
> > > during the implementation phase:
> > > "ERROR:OldMap:40 - Bad format for LOC constraint 36 on symbol
> > > "ucdisable.PAD"
> > >    (pad signal=ucdisable).  No such site for this device.  This may also
> > >    indicate that a non-constrainable site (such as a VCC, GND, mode,
> > >    configuration, or other special-purpose pin) has been used as a site
> > > name.
> > > ERROR:OldMap:40 - Bad format for LOC constraint 65 on symbol
> > > "ramdisable.PAD"
> > >    (pad signal=ramdisable).  No such site for this device.  This may also
> > >    indicate that a non-constrainable site (such as a VCC, GND, mode,
> > >    configuration, or other special-purpose pin) has been used as a site
> > > name."
> > >
> > > Am I correct in my approach (defining these as hi @posedge of my main
> > > clock)? And it looks as if it will not let me set constraints on these
> > > pins, but I have verified (through pinouts and tech people at XESS) that
> > > those are the pins to set hi. Any ideas on how to go about this?
> > >
> > > Vik
> >
> > In verilog try:
> >
> > assign uc_reset = 1;
> > assign ce_n = 1;
> >
> > Don't define them as registers, just as outputs.
> > Since they are constant, they don't need to be registered on a clock.
> >
> > The error seems to be some sort of name conflict problem.  Or it may be that
> > the synthesizer is optimizing the register out and then having problems with
> > the result.
> >
> > Alan Nishioka
> > alan@nishioka.com
> >
> >
> >




--
|| Dr. Dave Van den Bout   XESS Corp.               (919) 387-0076 ||
|| devb@xess.com           2608 Sweetgum Dr.        (800) 549-9377 ||
|| http://www.xess.com     Apex, NC 27502 USA   FAX:(919) 387-1302 ||



Article: 30833
Subject: Re: Multiple state machines in altera AHDL
From: Luke Roth <roth@narn.cse.psu.edu>
Date: Mon, 30 Apr 2001 21:23:23 -0400
Links: << >>  << T >>  << A >>
> I don't think i'll ever use xilinx again. Web-packs are no go, they
> can pull the plug at any time. Cypress and altera have the right
> idea;) When i get my thing going and sell a few thousand, i think
> altera will have got their money back for giving away a few copies
> of maxplus...

	Actually, the WebPack and Max-PlusII+ software use the exact same
licensing setup.  They run the same program, I even combined both license
files into one on my PC.  They both expire every so often (I had to
download a new license file for my Max-Plus tools just last week).  I tend
to use both tools - Altera for simpler CPLD designs, Xilinx for more
complicated designs in FPGAs.  No sense ruling either out, especially
since they're both free (mostly).
	Luke


Article: 30834
Subject: Re: C++ To Gates
From: Richard Meester <rme@quest-innovations.com>
Date: Tue, 01 May 2001 08:31:29 +0200
Links: << >>  << T >>  << A >>
Magnus,

Magnus Homann wrote:

> Richard, I cut most of your posting, because I think it all comes down to your
> part below.
>
> Richard Meester <rme@quest-innovations.com> writes:
>
> > I agree that you can pick up VHDL in a couple of weeks, I am a software
> > engineer with C/C++ experience, and i learned VHDL in a couple of weeks.
> > The only difference in design is that you describe the architecture that
> > solves your problem, and not the algorithm. I.e. you create an
> > infrastructure where the designer desides how to do it. In software you
> > code the algorithm, and you let the tool deside how the architecture
> > should be.
>
> Judging by what you write above, I'm not sure you grasp VHDL. Did you
> know that VHDL has filesystem? Abstract data types? VHDL is Ada with
> some extensions (not quite, but close enough). Anyone familiar with
> Ada could write software in VHDL in a week, no problem.

I know about the file system, know about abstract data types etc. But the main
problem/issue (at least for me) is that you must layout the registers etc in
VHDL(you design the infrastructure).

>
>
> I said write software and I mean it. This software could then be
> compiled and run, just like your Ada/Java/C++ program
>
> Now, _with the tools we have today_ that program would probably not by
> possible to synth to an FPGA (at least not the file system).

Indeed. And you can in Java. Perhas you are right from your standpoint that for
most of you VHDL is the language to use and the synthesizers are not good enough.
But with why is there C/C++/Ada/Smalltalk/Java. Because different people have
different ideas, and have different skills. Therefore why use only VHDL if i.e.
Java makes work easier for some people. I am not stating that it works easier for
you (probably not).

>
>
> You seem to think that the only VHDL you can write is low RTL-level
> VHDL, probably because that's what almost everybody uses it for. This
> is not due to any limitation in language, it's just that ther are no
> tools to convert any VHDL-program to HW. However, writing such a tol
> would be _much easier_ than to write an equally good tool for Java or
> any other programming language that doesn't support parallelism.
>

Maybe it may not be an limitation of the language, but the fact is that it is not
possible at current. The large companies are holding the synthesizer market.
In our case we developed a library to support parallelism, Not only when
synthesized to an FPGA, but also when run on a PC or a network of PC's. If we
create a software program to run on a PC, it takes 2 minutes to reconfigure it to
run on a network of computers.

>
> So why is a lot of people looking into Java or C to HW, and not VHDL to HW?
>
> * The VHDL crowd want control over what they do. Most of them (us) are
>   used to specifing each and every register.
>
> * It is easier to "sell" C-to-HW (_everyone_ knows C, right?) than
>   VHDL-to-HW("VHDL is low-level, C is high-level"

This was one of my starting statements. More people are able to write software to
be converted into FPGA without learning another language, and then i am not
meaning you, but am targeting embedded software engineers and others who know how
to program in Java.

>
>
> > For me this is much simpler and faster, resulting in less time
> > spent per design, which in our case improves productivity. And as said,
> > for now it is only applicible for designs that are not that time critical,
> > second our designs use more gates than when designed with VHDL. But this
> > is not allways a problem. If it is a problem don't use it, if it is not a
> > problem, and you can cut down on development time and cost why shouldn't
> > you use it?
>
> You are obviously trying to sell a tool that converts Java to HW. Now
> tell me, hadn't it been better if that tool converted the same
> expressions taken in VHDL and convert it to HW? If so, I could write
> software for the "slow" part, and embed RTL for the fast part. Doing
> it ioe languagfe instead of two, would make it _so_ much easier. Both
> for me, that knows VHDL, and any programmer that could pick up VHDL
> programming in a week.
>
> My answer? Java is Internet. Java is sexy. Java is money. All valid
> reasons for you, _but don't blame the language_.

Perhaps Java is internet to you, but the start of Java was to build an embedded
microcontroller chip/language. It took of by the internet, and with the fact that
there is now hardware available that directly executes java byte codes it is round
circle again. But it was designed for embedded industries, not for internet.

Secondly i am not blaming the language, if the language does for you what it is
supposed to do dan keep using it. If you find that there is an easier way of
getting where you want with Java then use this. In our case we use it with Java
cores in FPGA or Java Chips. So for us we can write a complete sollution in
Java(both the user application as well as the extra on chip logic), and not use
Java and VHDL. So for us it is better.

Richard

>
>
> Thanks,
> Homann
> --
> Magnus Homann, M.Sc. CS & E
> d0asta@dtek.chalmers.se

--
Quest Innovations
tel: +31 (0) 227 604046
http://www.quest-innovations.com



Article: 30835
Subject: Re: Multiple state machines in altera AHDL
From: Nial Stewart <nials@sqf.hp.com>
Date: Tue, 01 May 2001 08:59:13 +0100
Links: << >>  << T >>  << A >>
Russell Shaw wrote:
> 
> I don't think i'll ever use xilinx again. Web-packs are no go, they
> can pull the plug at any time. Cypress and altera have the right
> idea;) When i get my thing going and sell a few thousand, i think
> altera will have got their money back for giving away a few copies
> of maxplus...


As Luke says the webpack software is downloadable and from there the
license probably expires every XXX months.

Are you sure you're not thinking of the web fitter (or something like
that) tools?


Anyway, the point that I was trying to make is that VHDL might have a 
bit of a steeper learning curve, but it's probably worth the effort in
the long run.

Verilog might be easier to pick up working on your own.


Nial.

Article: 30836
Subject: Re: C++ To Gates
From: Magnus Homann <d0asta@mis.dtek.chalmers.se>
Date: 01 May 2001 10:04:46 +0200
Links: << >>  << T >>  << A >>
Richard Meester <rme@quest-innovations.com> writes:

> Magnus,
> 
> Magnus Homann wrote:
> 
> > Richard, I cut most of your posting, because I think it all comes down to your
> > part below.
> >
> > Richard Meester <rme@quest-innovations.com> writes:
> >
> > > I agree that you can pick up VHDL in a couple of weeks, I am a software
> > > engineer with C/C++ experience, and i learned VHDL in a couple of weeks.
> > > The only difference in design is that you describe the architecture that
> > > solves your problem, and not the algorithm. I.e. you create an
> > > infrastructure where the designer desides how to do it. In software you
> > > code the algorithm, and you let the tool deside how the architecture
> > > should be.
> >
> > Judging by what you write above, I'm not sure you grasp VHDL. Did you
> > know that VHDL has filesystem? Abstract data types? VHDL is Ada with
> > some extensions (not quite, but close enough). Anyone familiar with
> > Ada could write software in VHDL in a week, no problem.
> 
> I know about the file system, know about abstract data types etc. But the main
> problem/issue (at least for me) is that you must layout the registers etc in
> VHDL(you design the infrastructure).

Then you don't know what VHDL is. You think it is RTL only. It isn't.

> > I said write software and I mean it. This software could then be
> > compiled and run, just like your Ada/Java/C++ program
> >
> > Now, _with the tools we have today_ that program would probably not by
> > possible to synth to an FPGA (at least not the file system).
> 

> Indeed. And you can in Java. Perhas you are right from your
> standpoint that for most of you VHDL is the language to use and the
> synthesizers are not good enough.  But with why is there
> C/C++/Ada/Smalltalk/Java. Because different people have different
> ideas, and have different skills. Therefore why use only VHDL if
> i.e.  Java makes work easier for some people. I am not stating that
> it works easier for you (probably not).

Why use only one language in a project, when everybody can use their
own? That should be fairly obvious. Which is easier to maintain, a
piece of HW developed in VHDL or a mix of VHDl and Java?

> > You seem to think that the only VHDL you can write is low RTL-level
> > VHDL, probably because that's what almost everybody uses it for. This
> > is not due to any limitation in language, it's just that ther are no
> > tools to convert any VHDL-program to HW. However, writing such a tol
> > would be _much easier_ than to write an equally good tool for Java or
> > any other programming language that doesn't support parallelism.
> 
> Maybe it may not be an limitation of the language, but the fact is that it is not
> possible at current.

Then why are you contnuing about this crusaed against VHDL?

> The large companies are holding the synthesizer market.
> In our case we developed a library to support parallelism, Not only when
> synthesized to an FPGA, but also when run on a PC or a network of PC's. If we
> create a software program to run on a PC, it takes 2 minutes to reconfigure it to
> run on a network of computers.

So you extended Java so it would be parallel. VHDL already supports
that. So what have you achieved?

> > So why is a lot of people looking into Java or C to HW, and not VHDL to HW?
> >
> > * The VHDL crowd want control over what they do. Most of them (us) are
> >   used to specifing each and every register.
> >
> > * It is easier to "sell" C-to-HW (_everyone_ knows C, right?) than
> >   VHDL-to-HW("VHDL is low-level, C is high-level"
> 
> This was one of my starting statements. More people are able to write software to
> be converted into FPGA without learning another language, and then i am not
> meaning you, but am targeting embedded software engineers and others who know how
> to program in Java.

Those guys could learn VHDL in the same time it takes them to figure
out the limitations in your Java-version. In either caes, it's a new
language.


> > > For me this is much simpler and faster, resulting in less time
> > > spent per design, which in our case improves productivity. And as said,
> > > for now it is only applicible for designs that are not that time critical,
> > > second our designs use more gates than when designed with VHDL. But this
> > > is not allways a problem. If it is a problem don't use it, if it is not a
> > > problem, and you can cut down on development time and cost why shouldn't
> > > you use it?
> >
> > You are obviously trying to sell a tool that converts Java to HW. Now
> > tell me, hadn't it been better if that tool converted the same
> > expressions taken in VHDL and convert it to HW? If so, I could write
> > software for the "slow" part, and embed RTL for the fast part. Doing
> > it ioe languagfe instead of two, would make it _so_ much easier. Both
> > for me, that knows VHDL, and any programmer that could pick up VHDL
> > programming in a week.
> >
> > My answer? Java is Internet. Java is sexy. Java is money. All valid
> > reasons for you, _but don't blame the language_.

> Perhaps Java is internet to you, but the start of Java was to build
> an embedded microcontroller chip/language. It took of by the
> internet, and with the fact that there is now hardware available
> that directly executes java byte codes it is round circle again. But
> it was designed for embedded industries, not for internet.

Java for me is one of the better progrfamming languages out there. But
you are not tryingg tos ell your extension to peolpe like me, but to
people who ahve a vague ieda about Java, and no idea about HW.
 
> Secondly i am not blaming the language, if the language does for you
> what it is supposed to do dan keep using it. If you find that there
> is an easier way of getting where you want with Java then use
> this. In our case we use it with Java cores in FPGA or Java
> Chips. So for us we can write a complete sollution in Java(both the
> user application as well as the extra on chip logic), and not use
> Java and VHDL. So for us it is better.

But you _are_ blaming the language! "In VHDL you must layout the
register". This is so untrue. There is even no such thing as a
register in VHDL. The fact that you don't get this, invalidates your
comparisons VHDL vs. Java.

But I'm only re-iterating what I told you before.

Homann
-- 
Magnus Homann, M.Sc. CS & E
d0asta@dtek.chalmers.se

Article: 30837
Subject: Re: C++ To Gates
From: Richard Meester <rme@quest-innovations.com>
Date: Tue, 01 May 2001 11:07:56 +0200
Links: << >>  << T >>  << A >>


Magnus Homann wrote:

> Richard Meester <rme@quest-innovations.com> writes:
>
> > Magnus,
> >
> > Magnus Homann wrote:
> >
> > > Richard, I cut most of your posting, because I think it all comes down to your
> > > part below.
> > >
> > > Richard Meester <rme@quest-innovations.com> writes:
> > >
> > > > I agree that you can pick up VHDL in a couple of weeks, I am a software
> > > > engineer with C/C++ experience, and i learned VHDL in a couple of weeks.
> > > > The only difference in design is that you describe the architecture that
> > > > solves your problem, and not the algorithm. I.e. you create an
> > > > infrastructure where the designer desides how to do it. In software you
> > > > code the algorithm, and you let the tool deside how the architecture
> > > > should be.
> > >
> > > Judging by what you write above, I'm not sure you grasp VHDL. Did you
> > > know that VHDL has filesystem? Abstract data types? VHDL is Ada with
> > > some extensions (not quite, but close enough). Anyone familiar with
> > > Ada could write software in VHDL in a week, no problem.
> >
> > I know about the file system, know about abstract data types etc. But the main
> > problem/issue (at least for me) is that you must layout the registers etc in
> > VHDL(you design the infrastructure).
>
> Then you don't know what VHDL is. You think it is RTL only. It isn't.
>
> > > I said write software and I mean it. This software could then be
> > > compiled and run, just like your Ada/Java/C++ program
> > >
> > > Now, _with the tools we have today_ that program would probably not by
> > > possible to synth to an FPGA (at least not the file system).
> >
>
> > Indeed. And you can in Java. Perhas you are right from your
> > standpoint that for most of you VHDL is the language to use and the
> > synthesizers are not good enough.  But with why is there
> > C/C++/Ada/Smalltalk/Java. Because different people have different
> > ideas, and have different skills. Therefore why use only VHDL if
> > i.e.  Java makes work easier for some people. I am not stating that
> > it works easier for you (probably not).
>
> Why use only one language in a project, when everybody can use their
> own? That should be fairly obvious. Which is easier to maintain, a
> piece of HW developed in VHDL or a mix of VHDl and Java?

This is exactly what i mean. Don't use different languages in the same project (sorry
if i didn't put it correctly). What i meant was that if there are people in a company
programming Java, why don't let them create a sollution based on Java.
As stated below for us this means using only Java. We can both create the program as
well as the hardware in Java. In future perhaps we can switch at run-time between
running a process in hardware or executing it on a Java based cpu. So for us with Java
we have a 1 language solution, not a VHDL java mix.

>
>
> > > You seem to think that the only VHDL you can write is low RTL-level
> > > VHDL, probably because that's what almost everybody uses it for. This
> > > is not due to any limitation in language, it's just that ther are no
> > > tools to convert any VHDL-program to HW. However, writing such a tol
> > > would be _much easier_ than to write an equally good tool for Java or
> > > any other programming language that doesn't support parallelism.
> >
> > Maybe it may not be an limitation of the language, but the fact is that it is not
> > possible at current.
>
> Then why are you contnuing about this crusaed against VHDL?

I am not on a cruisage against VHDL. The thread started out with the question how other
languages (c++ to Gates) work. I am simply stating that for those who are not used to
programming in VHDL that there are alternatives like C and Java. how nasty would the
world be without alternatives.

>
>
> > The large companies are holding the synthesizer market.
> > In our case we developed a library to support parallelism, Not only when
> > synthesized to an FPGA, but also when run on a PC or a network of PC's. If we
> > create a software program to run on a PC, it takes 2 minutes to reconfigure it to
> > run on a network of computers.
>
> So you extended Java so it would be parallel. VHDL already supports
> that. So what have you achieved?

Occam also has it build in the language, but who knows about programming in occam. It
is mostly used at academic level, not in business (there are some companies doing it,
but there is no company supporting the tools etc). It also was a longe time around. So
why was VHDL developed if we already had a language that supported parallel constructs
in the language? probably for the same reason as why we developed the Java compiler.
People have their own skills and programming languages they go by. With this people can
choose which programming language they would like to use for  a project.

What is achieved is that HDL is not the only language to program an FPGA in. Secondly
what is achieved with the extensions is to easier create distributed architectures of a
software program when build with these extensions. This was the main goal. That we used
it for our compiler is fine, but was not the goal. As said most programming languages
for CPU's are sequential. With these extensions they are not. That is what is achieved



>

>
>
> > > So why is a lot of people looking into Java or C to HW, and not VHDL to HW?
> > >
> > > * The VHDL crowd want control over what they do. Most of them (us) are
> > >   used to specifing each and every register.
> > >
> > > * It is easier to "sell" C-to-HW (_everyone_ knows C, right?) than
> > >   VHDL-to-HW("VHDL is low-level, C is high-level"
> >
> > This was one of my starting statements. More people are able to write software to
> > be converted into FPGA without learning another language, and then i am not
> > meaning you, but am targeting embedded software engineers and others who know how
> > to program in Java.
>
> Those guys could learn VHDL in the same time it takes them to figure
> out the limitations in your Java-version. In either caes, it's a new
> language.
>
> > > > For me this is much simpler and faster, resulting in less time
> > > > spent per design, which in our case improves productivity. And as said,
> > > > for now it is only applicible for designs that are not that time critical,
> > > > second our designs use more gates than when designed with VHDL. But this
> > > > is not allways a problem. If it is a problem don't use it, if it is not a
> > > > problem, and you can cut down on development time and cost why shouldn't
> > > > you use it?
> > >
> > > You are obviously trying to sell a tool that converts Java to HW. Now
> > > tell me, hadn't it been better if that tool converted the same
> > > expressions taken in VHDL and convert it to HW? If so, I could write
> > > software for the "slow" part, and embed RTL for the fast part. Doing
> > > it ioe languagfe instead of two, would make it _so_ much easier. Both
> > > for me, that knows VHDL, and any programmer that could pick up VHDL
> > > programming in a week.
> > >
> > > My answer? Java is Internet. Java is sexy. Java is money. All valid
> > > reasons for you, _but don't blame the language_.
>
> > Perhaps Java is internet to you, but the start of Java was to build
> > an embedded microcontroller chip/language. It took of by the
> > internet, and with the fact that there is now hardware available
> > that directly executes java byte codes it is round circle again. But
> > it was designed for embedded industries, not for internet.
>
> Java for me is one of the better progrfamming languages out there. But
> you are not tryingg tos ell your extension to peolpe like me, but to
> people who ahve a vague ieda about Java, and no idea about HW.
>
> > Secondly i am not blaming the language, if the language does for you
> > what it is supposed to do dan keep using it. If you find that there
> > is an easier way of getting where you want with Java then use
> > this. In our case we use it with Java cores in FPGA or Java
> > Chips. So for us we can write a complete sollution in Java(both the
> > user application as well as the extra on chip logic), and not use
> > Java and VHDL. So for us it is better.
>
> But you _are_ blaming the language! "In VHDL you must layout the
> register". This is so untrue. There is even no such thing as a
> register in VHDL. The fact that you don't get this, invalidates your
> comparisons VHDL vs. Java

>
>
> But I'm only re-iterating what I told you before.
>
> Homann
> --
> Magnus Homann, M.Sc. CS & E
> d0asta@dtek.chalmers.se

--
Quest Innovations
tel: +31 (0) 227 604046
http://www.quest-innovations.com



Article: 30838
Subject: Re: Multiple state machines in altera AHDL
From: Russell Shaw <rjshaw@iprimus.com.au>
Date: Tue, 01 May 2001 19:29:21 +1000
Links: << >>  << T >>  << A >>
Haven't looked at the webpack stuff for a while. I assume you mean the
flexlm thing. The thing i don't really like is having the pc connected
to the web when doing design work. I suppose its useful if you need a
super-computer...

Luke Roth wrote:
> 
> > I don't think i'll ever use xilinx again. Web-packs are no go, they
> > can pull the plug at any time. Cypress and altera have the right
> > idea;) When i get my thing going and sell a few thousand, i think
> > altera will have got their money back for giving away a few copies
> > of maxplus...
> 
>         Actually, the WebPack and Max-PlusII+ software use the exact same
> licensing setup.  They run the same program, I even combined both license
> files into one on my PC.  They both expire every so often (I had to
> download a new license file for my Max-Plus tools just last week).  I tend
> to use both tools - Altera for simpler CPLD designs, Xilinx for more
> complicated designs in FPGAs.  No sense ruling either out, especially
> since they're both free (mostly).
>         Luke

--
   ___                                           ___
  /  /\                                         /  /\
 /  /__\                                       /  /\/\
/__/   / Russell Shaw, B.Eng, M.Eng(Research) /__/\/\/
\  \  /  Victoria, Australia, Down-Under      \  \/\/
 \__\/                                         \__\/

Article: 30839
Subject: Re: Multiple state machines in altera AHDL
From: Magnus Homann <d0asta@mis.dtek.chalmers.se>
Date: 01 May 2001 12:12:56 +0200
Links: << >>  << T >>  << A >>
Russell Shaw <rjshaw@iprimus.com.au> writes:

> Haven't looked at the webpack stuff for a while. I assume you mean the
> flexlm thing. The thing i don't really like is having the pc connected
> to the web when doing design work. I suppose its useful if you need a
> super-computer...

You download the WebPack and run it on your computer. You might be
thinking about WebFitter, which runs on Xilinx computer?

Homann
-- 
Magnus Homann, M.Sc. CS & E
d0asta@dtek.chalmers.se

Article: 30840
Subject: Renoir -> HDL designer?
From: "Anthony Ellis" <xxxa.ellis@logicworks.co.za>
Date: Tue, 1 May 2001 13:28:42 +0200
Links: << >>  << T >>  << A >>
Does anyone know the status of the coversion from Renoir to HDL Designer?




Article: 30841
Subject: Re: C++ To Gates
From: Kolja Sulimma <kolja@prowokulta.org>
Date: Tue, 01 May 2001 13:30:40 +0200
Links: << >>  << T >>  << A >>
> This is exactly what i mean. Don't use different languages in the same project (sorry
> if i didn't put it correctly). What i meant was that if there are people in a company
> programming Java, why don't let them create a sollution based on Java.

_Do_ use different languages for the same Project!!!

The point is that different languages provide different built in infrastructures that need
to be modeles explicitly
in other languages. You can do almost everything in almost any language. But would it be
easy? Fast? Easy to debug?

Let's say you have a vectorprocessor backend software: You really would like a language
that can be vectorized well.

A transputer farm for your numerics: Use occam instead of building your own set of
transputer communication classes.

Need a user interface for this? Well, if there is no GUI Editor for your language, you
better use another language.

My point is, that I at least find it easier to learn the basics of a new language than to
code 10 times the code using a bad API.

> > Then why are you contnuing about this crusaed against VHDL?

For explicit hardware design VHDL is great. The problem with VHDL if you want more
automation in the design process is the very fact that was stated over and over again in
this thread: You can do everything with VHDL.

This means, if you have your VHDL behavioural compiler that does architecture optimization,
instruction scheduling, task scheduling, partioning in time, and so on, then this compiler
must be able to communicate with all the fancy asynchronous circuit stuff that you designed
in your next line of VHDL as well as with your RTL.
In general this will be really hard to implement.

If you specialize a language for a certain model of computation, not only will it be easier
and more concise to code for this model, but you can expect much more sophisticated
optimizations by your compiler.

> Occam also has it build in the language, but who knows about programming in occam.

I hate this language, but It is a good example for what I said before. Occam really made
sense for transputers but without hardware support for virtual processor links, it looses a
lot.

I allready brought the example of SCORE where the use of buffered streams as the only way
of communication between processes allows to virtualize the hardware and do partitioning in
time.

I agree with you in the fact  that the success of Java in the internet market, and the
relativ (albeit small) success of Java or C to Hardware compilers is not due to the fact
that these languages are a good choice for hardware compilation.  It is just because there
lots of C programmers.

Bottom line: It is not always better to be more general.
(Did you ever wonder, why most simulation models for weather, etc. do not involve quantum
mechanics?)

Kolja Sulimma


Article: 30842
Subject: Re: Multiple state machines in altera AHDL
From: Greg Deuerling <egads@fnal.gov>
Date: Tue, 1 May 2001 07:40:56 -0500
Links: << >>  << T >>  << A >>
In article <3AED9371.6995F471@sqf.hp.com>, nials@sqf.hp.com says...
> Russell Shaw wrote:
> > 
> > Greg Deuerling wrote:
> > >
> > > In article <3AECBB59.2C68BF6D@iprimus.com.au>, rjshaw@iprimus.com.au says...
> > > > AHDL is *much* better than VHDL.
>       ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
> 
> 
> > > > Max-plus-ii is FREE:)
> > >
> > > Yeh brother, I second that.  VHDL is way to wordy and hard to follow.
> > 
> > plus i only put the max-plus CD in my PC on saturday, learnt the lingo,
> > and had the not-trivial design worked out and simulated by sunday
> > night:) Now to make a byte-blaster cable...
> 
> 
> But what happens if you decide to target a Xilinx device?
> (SpartanII devices are cheap, provide a lot of resource
> and the web pack software's free too).

I plan to use Foundation and a SpartanII comming up.  Altera really
lost me as a high end FPGA customer when they put out that load of
crap called Quartus.  They should have left MaxPlusII alone, it was
simple, fast, and easy to use.  I'll get used to using VHDL, but I'll
NEVER like it, and wish I was using AHDL.


-- 
                                                                     gad
=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=
=          Greg Deuerling, Fermi National Accelerator Laboratory          =
= P.O.Box 500 MS368  Batavia, IL 60510  (630)840-4629, FAX  (630)840-5406 =
=                  Electronic Systems Engineering Group                   =
=            Work: egads@fnal.gov       Personal: gad@elnet.com           =
=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=

Article: 30843
Subject: Exemplar: If-elsif synthesises to Muxcy in virtexE
From: "Nisreen Taiyeby" <nisreen@blr.paxonet.com>
Date: Tue, 1 May 2001 04:47:13 -0800
Links: << >>  << T >>  << A >>
There is a web seminar by Micheal A. Bohm of Exemplar logic(www.techonline.com) which says that a If-elsif structure is faster than case statements as it synthesises to using Muxcy in VirtexE. 

The code given by him in the seminar is as follows: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_arith.ALL; 

entity priority_encoder is Port (c: in Std_logic; d: in Std_logic; e: in Std_logic; f: in Std_logic; s:in Std_logic_vector(1 downto 0); pout: out std_logic); end entity priority_encoder; 

architecture priority_encoder_a of priority_encoder is 

begin pout_p: process (c,d,e,f,s) begin if s = "00" then pout <= c; elsif s = "01" then pout <= d; elsif s = "10" then pout <= e; else pout <= f; end if; end process pout_p; 

end architecture priority_encoder_a; 

I have leonardo 2001.1a_rc. I have synthesised the code with "set map_muxcy true" but there is no such use of Muxcy in the edn netlist. 

Further if I put the "set map_muxf5 TRUE" then I get one level of lut(2 luts in a level) followed by a muxf5 which gives 1.53 ns as logic delay for the 4:1 mux. 

If I put the "set map_muxf5 FALSE" then I get 2 levels of lut(2 luts in first level followed by another lut) which gives 1.79 ns as logic delay for the 4:1 mux. 

Is it that the claim of an if-elsif generating a muxcy is not correct. 

Does anyone have knowledge on this thing.

Article: 30844
Subject: Xilinx Virtex-II multiplier reuse examples
From: nospam@nospam.net (David Nyarko)
Date: Tue, 01 May 2001 12:58:44 GMT
Links: << >>  << T >>  << A >>
Hi,
Anyone with VHDL code examples for using 1 hardware multiplier
for 4 multiplications and multiplexing the inputs and outputs
appropriately?

Article: 30845
Subject: Gates to Hardware...
From: "Austin Franklin" <austin@darkroom87.com>
Date: Tue, 1 May 2001 09:31:15 -0400
Links: << >>  << T >>  << A >>
> This is was an
> agrument used in the previous thread to justify the  idea of using s/w
> engineers to design h/w

BTW, this is how we ended up with the awful architecture (which calling it
that is a very far stretch) of the PC in the first place.





Article: 30846
Subject: ccd imaging with fpga
From: martinb@magma.ca (M.B.)
Date: Tue, 01 May 2001 13:33:08 GMT
Links: << >>  << T >>  << A >>
Hi I have a telescope and some basic experiance with VHDL, FPGAs.
I would like to get a CCD (something common and cheap) and use a FPGA
perhaps a xilinx or atmel with VHDL. and interface to my computer (win
98.

Has anyone done somthing like this?
Is there a project in any books or wed sites that you have seen that
could get me started?

Or is there a development kit from one of the CCD Manufacturers that I
could look into?



Article: 30847
Subject: Re: C++ To Gates
From: Richard Meester <rme@quest-innovations.com>
Date: Tue, 01 May 2001 15:51:49 +0200
Links: << >>  << T >>  << A >>


Kolja Sulimma wrote:

> > This is exactly what i mean. Don't use different languages in the same project (sorry
> > if i didn't put it correctly). What i meant was that if there are people in a company
> > programming Java, why don't let them create a sollution based on Java.
>
> _Do_ use different languages for the same Project!!!

This is a difficult subject, i agree with Magnus that it is easier to maintain if written in 1
language. I also agree with you that it can have advantages to use different languages in the
same project and use the advantages of each language. Perhaps you should look at it with
different views from project to project.

>

>
>
> The point is that different languages provide different built in infrastructures that need
> to be modeles explicitly
> in other languages. You can do almost everything in almost any language. But would it be
> easy? Fast? Easy to debug?
>
> Let's say you have a vectorprocessor backend software: You really would like a language
> that can be vectorized well.
>
> A transputer farm for your numerics: Use occam instead of building your own set of
> transputer communication classes.
>
> Need a user interface for this? Well, if there is no GUI Editor for your language, you
> better use another language.
>
> My point is, that I at least find it easier to learn the basics of a new language than to
> code 10 times the code using a bad API.
>
> > > Then why are you contnuing about this crusaed against VHDL?
>
> For explicit hardware design VHDL is great. The problem with VHDL if you want more
> automation in the design process is the very fact that was stated over and over again in
> this thread: You can do everything with VHDL.
>
> This means, if you have your VHDL behavioural compiler that does architecture optimization,
> instruction scheduling, task scheduling, partioning in time, and so on, then this compiler
> must be able to communicate with all the fancy asynchronous circuit stuff that you designed
> in your next line of VHDL as well as with your RTL.
> In general this will be really hard to implement.
>
> If you specialize a language for a certain model of computation, not only will it be easier
> and more concise to code for this model, but you can expect much more sophisticated
> optimizations by your compiler.
>
> > Occam also has it build in the language, but who knows about programming in occam.
>
> I hate this language, but It is a good example for what I said before. Occam really made
> sense for transputers but without hardware support for virtual processor links, it looses a
> lot.

I don't hate the language, and it has quite good things. Thats why we used the channel
structure in our compiler. But indeed i prefer Java with the occam like library over
programming in occam.

>
>
> I allready brought the example of SCORE where the use of buffered streams as the only way
> of communication between processes allows to virtualize the hardware and do partitioning in
> time.
>
> I agree with you in the fact  that the success of Java in the internet market, and the
> relativ (albeit small) success of Java or C to Hardware compilers is not due to the fact
> that these languages are a good choice for hardware compilation.  It is just because there
> lots of C programmers.
>
> Bottom line: It is not always better to be more general.
> (Did you ever wonder, why most simulation models for weather, etc. do not involve quantum
> mechanics?)
>
> Kolja Sulimma

--
Quest Innovations
tel: +31 (0) 227 604046
http://www.quest-innovations.com



Article: 30848
Subject: Re: FPGA Prototyping Kits (Platforms)
From: "Dave Feustel" <dfeustel@mindspring.com>
Date: Tue, 1 May 2001 09:27:41 -0500
Links: << >>  << T >>  << A >>
I just got an Atmel FPSLIC starter kit containing a
microprocessor and a dynamically programmable
FPGA. I've looking for other  companies that make
similar kits, but so far the other kits have little documentation,
cost too much or are simply not yet available.

"Shawki Areibi" <sareibi@uoguelph.ca> wrote in message news:3AE442E8.7FCEAF58@uoguelph.ca...
> hi, I was wondering if someone knew about companies that sell FPGA
> prototyping kits for dynamically reconfigurable FPGAs (preferably XILINX
>
> since our students are using the XESS XS40).
> Also are there companies that develops kits for Atmel FPSLIC that
> combines
> FPGA with a microcontroller.
> I would really appreciate your comments and experience in this field
> PS: We would like to use the platforms to map Neural Net Algorithms
>        on the FPGAs
> You can email me directly at sareibi@uoguelph.ca
> Shawki
> --
> Shawki Areibi
> Assistant Professor
> School of Engineering
> University of Guelph
> Guelph, Ont, Canada N1G 2W1
> Tel: (519) 824-4120
> Fax: (519) 836-0227
>
>



Article: 30849
Subject: Using synospys power compiler for Xilinx Virtex design ..
From: Steven Derrien <sderrien@irisa.fr>
Date: Tue, 01 May 2001 16:55:15 +0200
Links: << >>  << T >>  << A >>
Hi, 

Has anybody ever used the power compiler tool suit from synopsys to 
perform RTL and 'gate' level power estimation for Xilinx FPGAs ? 

I'v looked to the synopsys documentation, but it doesn't get much into 
the practical details. Particulary, it seems that power compiler expects
some technlogical specific library to be able to run, but too few 
information are given.

Has anybody a clue or experience on this ?


thanks,

Steven



Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarApr2017

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search