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Messages from 31125

Article: 31125
Subject: Re: Virtex-2 - experiences ?
From: "Erik Widding" <widding@birger.com>
Date: Sat, 12 May 2001 15:11:24 GMT
Links: << >>  << T >>  << A >>
"Meelis Kuris" <matiku@hot.ee> wrote in message
news:3afbcfb5@news.estpak.ee...
>
> "Erik Widding" <widding@birger.com> wrote in message
> news:%PaK6.12945$t12.971754@bgtnsc05-news.ops.worldnet.att.net...
> ...
> > revision.  But overall, none of the errata is particularly bad, just
don't
> > expect the DCM to do all the really cool stuff listed in the data sheet.
>
> What do you mean by that? What doesn't it do then?
> Actually, the thing I'm concerned about is, does fine phase shift
> work ok (at 270MHz)?
> Can't test it right now myself but my whole project relies on that phase
> shift, so I'm a bit worried.

There are a number of limitations listed in the errata.  But it has been
reported to me by an FAE that some of the features with problems, i.e.
variable phase shift, are usable for testing purposes.  In this particular
die revision many items listed in the errata are merely not 100% reliable,
or not 100% characterized.  You should call your FAE to get a complete copy
of the errata.  If a feature that you need is listed in the errata, call him
back to find out "just how broken" the feature is.  Just because something
is listed on the errata as not working, doesn't necessarily mean that it is
completely broken.


Regards,
Erik Widding.


--
Birger Engineering, Inc.  --------------------------------  781.481.9233
38 Montvale Ave #260; Stoneham, MA 02180  -------  http://www.birger.com




Article: 31126
Subject: Re: Implementation Of LUT in Vertex-E
From: Kolja Sulimma <kolja@prowokulta.org>
Date: Sat, 12 May 2001 17:20:00 +0200
Links: << >>  << T >>  << A >>


Erik Widding wrote:

> "Falk Brunner" <Falk.Brunner@gmx.de> wrote in message
> news:3AFD127D.9460AAFC@gmx.de...
> > A. I. Khan schrieb:
> > >
> > > Hi all !
> > >
> > > I'll appreciate if anyone could facilitate me with some idea  to
> > > implement LUT (4096  words depth with 10 bits width) in Vertex-E (Part:
> > > V1000EBG 560) for FPGA.
> > You can also use 10 4096x1bit ROMS (no chip select decoder
> > required),this depends a little bit on the required speed.
>
> This is the right way.  It is faster, smaller, and... we certainly shouldn't
> overlook... simpler to implement.

What do you want to store in your ROM?
You should at least try to synthesize the ROM from VHDL, especially when you
have values in your ROM that you can set to "-" (Don't care)
Depending on the ROM content you can get very good or very bad results.


Kolja Sulimma


Article: 31127
Subject: Re: Shannon Capacity, a quote from the paper
From: Rick Collins <spamgoeshere4@yahoo.com>
Date: Sat, 12 May 2001 11:51:17 -0400
Links: << >>  << T >>  << A >>
Brian Drummond wrote:
> In other words, you can increase the binary digit rate (raw channel
> capacity) of the channel ad infinitum. But because of the redundancy you
> need for reliability in the presence of noise, you cannot increase the
> _information_ rate beyond a certain limit - the useful channel capacity.
> 
> Having separated these two concepts, it seems obvious to me, that
> Shannon's "channel capacity" refers to the "useful channel capacity"
> since he refers to it as the ability to carry information. In other
> words the redundancy is NOT counted as part of the channel capacity.
> 
> - Brian.

I don't know that we need to consider what Shannon "meant". This is a
physical/mathematical relationship that Shannon discovered. The truth is
in the relationship, not the words of Shannon. 

I think it is very clear that the value C described in the formula given
(whichever one you pick of the several offered) is the data rate after
all processing has been done to recover "error free" bits. Nowhere in
the formula does it consider any characteristics of the method of
transmission. So this formula does not consider the "raw" channel
capacity. It only considers the "information" capacity of unerrorred
data. If this formula describes the "raw" channel capacity, it would
have no value since I can transmit any data rate on a channel if I am
willing to live with the resultant errors. 

A formula that defines the "raw" data rate on a channel would have to do
so in terms of the error rate as you can increase the "raw" data rate at
the expense of a higher error rate. Since error rate does not show in
this formula, C = W log2 (P+N)/N, this formula can not be describing the
"raw" channel capacity. 


-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 31128
Subject: Re: Shannon Capacity
From: Rick Collins <spamgoeshere4@yahoo.com>
Date: Sat, 12 May 2001 12:03:23 -0400
Links: << >>  << T >>  << A >>
I guess I am jumping in late in the game, but maybe I can help clarify
things a bit. 

The check and correct bits ARE information. But they are not added
information. Since they are calculated from the message itself and are
uniquely identified by the message, they provide no extra information.
In fact that is the point. They contain a subset of the information in
the message so that they can be used to detect errors in the message. If
the message were transmitted with no errors, the check and correct bits
would provide no extra information. 

Is that more clear?



Austin Lesea wrote:
> 
> See what I mean?
> 
> Still confused after all these years.
> 
> If the CRC is not information, then you don't need it.
> 
> If the CRC is information, then you need to send it.
> 
> I rest my case.
> 
> Austin
> 
> Berni Joss wrote:
> 
> > "Austin Lesea" <austin.lesea@xilinx.com> wrote in message
> > news:3AEDB258.DE79F5F7@xilinx.com...
> > > Kevin,
> >
> > <<snip>>
> >
> > > All bits must be included in the channel.  How else do you get them at
> > the other
> > > end?  They too, may be in error.  A rate 1/2 code means that twice as
> > many bits
> > > are in the channel, so that is a horrendously inefficient code (it cuts
> > in half
> > > your through put).
> > >
> >
> > I do not agree.
> >
> > I'm not sure I understand Austin correctly, but assuming you are sending
> > packets of 10 bytes each followed by 2 bytes of CRC then, it is my
> > understanding that, you should NOT count the CRC bytes into the channel
> > capacity C.
> > The reason being that the CRC bits do not contribute information, they are
> > fully predictable.
> >
> > The channel capacity, as far as I remember from school many years ago :)),
> > measures the "information" flow per unit time. If all transmitted bits are
> > completely random, then the capacity equals the bit rate.
> > Adding fully predictable bits [FEC, CRC, constants! or otherwise
> > predictable] does not increase the information content of your message, and
> > therefore does not require additional channel capacity.
> >
> > Note that you can send 10Mbit/s of zeros through a completely "blocked"
> > channel (S/N = 0) and recover all zeros without error, if you know that you
> > should expect zeros!
> > A less "trivial" or stupid example is the coding used over bad audio links,
> > e.g. radio, where entire words are used instead of letters [alpha = a,
> > bravo = b, charlie = c, ... zulu = z]. In this case, each word has the
> > information content of just a single letter.
> >
> > Most text books about communication systems have a section about the
> > Shannon limit. The one I have hany explains it quite well. "Digital and
> > Analog Communication Systems", by Leon W. Couch II, published by Macmillan
> > Publishing Company.
> >
> > Hope this helps,
> > Berni.
> >
> > >
> > > Kevin Neilson wrote:
> > >
> > > > There's something I've never quite understood about Shannon's Law.  It
> > > > states something like this:
> > > >
> > > > C = W*logbase2(1 + S/N)
> > > >
> > > > where C is channel capacity, bits/s
> > > >     W = bandwidth, Hz
> > > >     S/N = signal-to-noise ratio
> > > >
> > > > Theoretically, if using enough error-correction, you can transmit C
> > bits/s
> > > > on a channel error-free.
> > > >
> > > > Say you determine that the channel capacity for a particular channel is
> > > > 1Mbit/s.  Does that include the error correction bits or not?  What if
> > you
> >
> > No, don't include the error correction bits.
> >
> > > > have a 1/2 rate code, where half of the bits are parity bits.  Does
> > that
> > > > mean you transmit 2Mbit on that channel (with 1Mbit capacity) for a net
> > data
> > > > throughput of 1Mbit error-free?  Or does the 1Mbit include the partiy
> > bits?
> >
> > 2Mbit/s of which 1Mbit/s is error correction is compatible with a 1Mbit/s
> > channel. But Shannon won't tell you how to code it! He just says it is not
> > impossible.
> >
> > > >
> > > > -Kevin
> > >


-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 31129
Subject: Re: Finally, an FPGA tool chain for Linux (Altera Quartus II)
From: Duane Clark <dclark@akamail.com>
Date: Sat, 12 May 2001 09:17:35 -0700
Links: << >>  << T >>  << A >>
Eric Smith wrote:
> 
> Rick Filipkiewicz <rick@algor.co.uk> writes:
> > Given that VMWare provides a way of using the command line tools under
> > Linux then
> > (3) => Xilinx doesn't have to do a Linux port.
> 
> I use VMware.  But running Windows software under VMware is really
> annoying compared to running native Linux software.
> 
> VMware supports more than just the command line tools.  Since it runs
> real Windows, it runs the GUI stuff too.
> 
> However, I'd much prefer to completely remove Windows from my system.
> Right now the Xilinx software is the ONLY reason I have Windows installed.
> I haven't looked at Altera's FPGAs in a few years, but if their parts will
> do what I want, having native tools for Linux may well make me switch.
> 
> The Xilinx Windows GUI wrapper is nice in some ways, but I'd trade it
> for command-line-only tools under Linux without any hesitation whatsoever.

So (the obligatory question) just out of curiosity, why aren't you
running them under wine? All of the Xilinx command line tools work
perfectly this way, and have been doing so for more than a year. The one
wine bug I am aware of that cropped up, about a half year ago, was fixed
within days by the wine developers. Now that is service that you likely
won't get from any CAE vendor. 

I have VMware, but I never run the Xilinx tools under it, because they
are so much easier and faster under wine. I can type "ngdbuild -p
xcv300e-6-bg432 -sd ../ngofiles top.ngo", and it behaves exactly as if I
were under Solaris. I generally use scripts, but my scripts execute the
commands exactly as specified in the Xilinx docs. Makefiles work too,
and I would assume that TCL would work, though I have not tried it.

Yes, getting Xilinx setup under wine is a little more effort than just
inserting a CD and clicking setup. But having gone through that a year
ago, it was well worth the effort to me.

Duane

Article: 31130
Subject: Re: Finally, an FPGA tool chain for Linux (Altera Quartus II)
From: Phil Hays <spampostmaster@home.com>
Date: Sat, 12 May 2001 16:19:26 GMT
Links: << >>  << T >>  << A >>
Kolja Sulimma wrote:

> We are currently running Foundation in a windows NT multi user enviroment. Everybody
> here is anoyed because the
> preferences are shared among all users.

Is the the part of Foundation that does simulation, aka Aldec aka SusieCAD?  I
used Aldec stuff under a WindowsNT 3.51 multi-user system about 5 years ago. 
There is (err.. or was..) a global registry entry set by the Aldec install that
told the Aldec tools where to load the preferences from.  If you set this as a
user registry entry to your personal copy of the (directory or file?  I can't
recall.) that it was originally pointed to, then your preferences became your
own.  Had to do both for it to work, otherwise the Aldec stuff wouldn't start.

Please note:  this was two versions of NT and several versions of Aldec ago, and
was before Aldec was OEM'd by Xilinx.  Registry edits must be done with great
care.  Attempt this at your own risk.


> Read the XC4K datasheet. It says that you can put three arbitrary independant
> functions (no shared inputs) of 4, 4 and 3 inputs respectively into a single CLB if
> one or two of these functions are fed to registers.
> Ever tried this?
> Well, you can't, unless you use the FPGA-Editor.

I got a list as well.  The map bug is just the current head of the list.


-- 
Phil Hays

Article: 31131
Subject: Re: Shannon Capacity
From: Rick Collins <spamgoeshere4@yahoo.com>
Date: Sat, 12 May 2001 12:42:46 -0400
Links: << >>  << T >>  << A >>
This interpretation is clearly wrong. Consider the formula C = W log2
(P+N)/N. If your noise goes to ZERO, then the fraction (P+N)/N goes to
infinity. This results in C going to infinity. 

C is the upper bound for unerrord data rate for a given bandwidth and a
given noise level. This is not in any way related to the actual bit rate
of the transmission. This is the rate of useful information. So by
definition it would not include redundant check and correct bits. 


Austin Lesea wrote:
> 
> .....
> 
> It says that for a rate of C bits per second in the presence of No
> noise power bandwidth in W hertz, you can have error free operation.
> 
> It tells you nothing about how to code it to achieve that rate.
> 
> That's the million dollar question: how do you even get close to the
> Shannon limit without knowing how?
> 
> Austin
> 
> Steve Rencontre wrote:
> 
> > In article <3af20db4.2149921@news.dtgnet.com>, nemo@dtgnet.com
> > (Nemo)
> > wrote:
> >
> > > C refers the the capacity of a physical band-limited
> > > channel.  By definition, C includes *all* the data carried by the
> > > channel. This includes the payload data and any overhead (parity
> > bytes,
> > > etc) needed for the FEC layer if used.
> >
> > Sorry, but that doesn't add up. Shannon's Theorem says that you can
> > carry
> > C bps /without/ error. In that case, why have you included error
> > detection
> > and correction bits with the payload data?!
> >
> > --
> > Steve Rencontre         http://www.rsn-tech.co.uk
> > //#include <disclaimer.h>


-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 31132
Subject: Re: Finally, an FPGA tool chain for Linux (Altera Quartus II)
From: Phil Hays <spampostmaster@home.com>
Date: Sat, 12 May 2001 17:27:08 GMT
Links: << >>  << T >>  << A >>
Rick Collins wrote:

> I am currently using FPGA design tools under NT and I find that I need
> to boot the machine once every two or three days just to keep things
> running correctly. Many people claim that the real problems are in the
> various apps, which may be true. But I have never seen a Unix system
> that was taken down on a regular basis just to clean up problems. Just
> as the proof of the pudding is in the eating, the measure of an OS is in
> the running (or rebooting).

As I mentioned, my experience with NT 4 and Windows 2000 is rather better.  I
don't know why, different applications perhaps?  Or different hardware perhaps
(Dell or Micron vs ?)?  I've seen frequent crashes out of a "Joes Clone Shop"
machine, and a similar Dell machine had many fewer crashes.  Windows 3.1 and
follow-ups (Win95, Win98 and WinME) is a different story.

A decade ago, I was using Viewlogic Xilinx under Unix, and Viewmumble would
coredump about once a day.  Between once a week and once a month the OS would
follow, or about as often, would create a zombie process that "kill -9", the
sure kill, couldn't kill.  Attempting to keep using the system with this zombie
would cause a system coredump, so we just rebooted.  Oh, and the coredumps from
Viewmumble would be in a different place every time, so we needed to grep for
and delete these to maintain non-zero disk space.  Oh, and the license manager
would crash, and either we had to hunt down someone with the root password to
restart it, or just tell everyone to save and log off so we could reboot.  Time
between forced reboots was about a week.

I'd rather have been using VMS or Tops20.  But maybe it was the applications
fault?  Or the hardware's fault?


> Then again some of the tools are nothing to brag about. I find that
> Modelsim crashes once every 4 or 5 reloads of a design.

Do you reload or restart the simulation?


-- 
Phil Hays

Article: 31133
Subject: Xilinx and Actel
From: Chris Eilbeck <chris@yordas.demon.co.uk>
Date: 12 May 2001 18:27:56 +0100
Links: << >>  << T >>  << A >>
Has anyone used both?  I'm used to the Xilinx toolchain and devices
but a client wants a project done using Actel antifuse.  Are there any
objective comparisons anywhere on the web or does anyone have any
opinions as to how hard it would be to make the change?

Ta

Chris
-- 
Chris Eilbeck                             mailto:chris@yordas.demon.co.uk
MARS Flight Crew                                  http://www.mars.org.uk/
UKRA #1108 Level 1                                                   BSMR


Article: 31134
Subject: Re: SRAM fpga cell
From: Falk Brunner <Falk.Brunner@gmx.de>
Date: Sat, 12 May 2001 19:32:25 +0200
Links: << >>  << T >>  << A >>
Rick Filipkiewicz schrieb:
> 
> > Just forget about the system gate number, its practical useless. Have a
>   ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
> 
> Falk should have added that they are usually known in the trade as
> ``marketing gates'' whose meaning is generally only understood by

;-)))))

-- 
MFG
Falk


Article: 31135
Subject: Fine phase shift in Virtex2
From: "Meelis Kuris" <matiku@hot.ee>
Date: Sat, 12 May 2001 21:15:23 +0300
Links: << >>  << T >>  << A >>
Hi!

I need to shift phase of 270MHz clock signal 90 degrees.
As I can't use CLK90 output of DCM in high frequency mode,
I'm using fine phase shift of clk0 output.
For some reason it doesn't work in simulation, output clock is
still exactly phase-aligned to the input clock.
I'm using Modelsim XE, with new libraries from xilinx site.

Am I doing something wrong or is it just the simulation software?

Thanks in advance,

Meelis


Here's the source:
----------------------------------------------------------
entity tb is
end tb;

architecture tb_a of tb is

component DCM

    port ( CLKIN     : in  std_logic;
           CLKFB     : in  std_logic;
           DSSEN     : in  std_logic;
           PSINCDEC  : in  std_logic;
           PSEN      : in  std_logic;
           PSCLK     : in  std_logic;
           RST       : in  std_logic;
           CLK0      : out std_logic;
           CLK90     : out std_logic;
           CLK180    : out std_logic;
           CLK270    : out std_logic;
           CLK2X     : out std_logic;
           CLK2X180  : out std_logic;
           CLKDV     : out std_logic;
           CLKFX     : out std_logic;
           CLKFX180  : out std_logic;
           LOCKED    : out std_logic;
           PSDONE    : out std_logic;
           STATUS    : out std_logic_vector(7 downto 0)
          );
end component;

attribute DLL_FREQUENCY_MODE : string;
attribute CLKOUT_PHASE_SHIFT : string;
attribute PHASE_SHIFT  : integer;

attribute DLL_FREQUENCY_MODE of dcm1: label is "HIGH";
attribute CLKOUT_PHASE_SHIFT of dcm1: label is "FIXED";
attribute PHASE_SHIFT  of dcm1: label is 64; -- actual phase shift is period
* PHASE_SHIFT / 256

component bufg port (
 I  : in std_logic;
 O  : out std_logic);
end component;

signal clk, clk90, gnd, Reset, clk90DCM1o : std_logic:='0';

begin
gnd <= '0';
Reset <='0';
clk<= not clk after 10 ns;

dcm1 : DCM

 port map (
 CLKIN => clk,
 CLKFB => clk90,
 DSSEN => gnd,
 PSINCDEC => gnd,
 PSEN => gnd,
 PSCLK => gnd,
 RST => Reset,
 CLK0 => clk90DCM1o
 );

bufg5 : bufg port map(
 I => clk90DCM1o,
 O => clk90 );

end tb_a;




Article: 31136
Subject: Re: Finally, an FPGA tool chain for Linux (Altera Quartus II)
From: Neil Franklin <neil@franklin.ch.remove>
Date: 12 May 2001 22:37:58 +0200
Links: << >>  << T >>  << A >>
Kolja Sulimma <kolja@prowokulta.org> writes:

> > At least JBits will work on Linux, since it's written in Java, although
> > the damn Linux installer that Xilinx used for the latest version won't
> > run properly on my system with Red Hat Linux 7.0 and Sun's latest JDK.

Will also not run on Slackware 7.0 and JDK 1.2.2.006. This seems to be
universal.


> > AFAIK, all the JBits installer does is extract files from an archive,

Apart from one thing: assuring you have the password. So it seems to
be one of these braindead distribution control things. Fits into the
same mould as having to order an URL by mail instead of simply downloading
it from an public known web site.


> > so it seems like it should be even easier for them to simply supply a
> > .tar.gz file.

I have an theory: some "GUIs'R'Us" designer felt that an .tar.gz is
not in line with offering "quality", so it had to have an GUI. At
lowest possible cost, so they used this installer.


> Or a JAR file....

Actually after the crash I tried to debug it, and looked at the left
overs. It seems to unpack an JAR and a few other files  out of the
executable, then that JAR is unpacked to a load of files with dumb
names (numbers, IIRC, this was a month ago), it then renames them,
most likely with data from an totally unreadable binary file. Most
likely the password is a decryption key for that file.


--
Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/
Hacker, Unix Guru, El Eng HTL/BSc, Sysadmin, Archer, Roleplayer
- Intellectual Property is Intellectual Robbery

Article: 31137
Subject: Re: Finally, an FPGA tool chain for Linux (Altera Quartus II)
From: Neil Franklin <neil@franklin.ch.remove>
Date: 12 May 2001 23:01:28 +0200
Links: << >>  << T >>  << A >>
Phil Hays <spampostmaster@home.com> writes:

> rather see Tops20. (-;)  (OK, hardware availability is a problem.)

<off-topic>
Hardware availability is a problem?

Methinks, you do not know, that you can still get TOPS-20 v7.xx
together with fitting hardware TOAD-1 [1] (an KL-10 clone with 30bit
extended addressing) from XKL (http://www.xkl.com/).

It even uses FPGAs for its processor [2].

[1] http://www.xkl.com/xkl/toad-1.gif
[2] http://www.io.com/~guccione/HW_list.html

>From [2]:

FPGA Devices:
     2 Xilinx XC4010E-3
Contact:
     Product Information
     XKL Systems Corp.
     8420 154th Avenue NE
     Redmond, WA 98052
     np-info@nospam.xkl.com
Notes:
     This is the CPU for the TOAD-1, a 36-bit computer instruction-set
     compatible with the Digital Equipment Corporation PDP-10 family
     of computers (best known as the DECsystem-10 and DECSYSTEM-20,
     defined by the respective operating systems Tops-10 and Tops-20).
     The FPGAs are used for all arithmetic, including floating-point
     and byte-selection operations. (Note: The PDP-10 architecture is
     word-oriented, with byte size and position within the 36-bit word
     defined by a pointer word which also contains the word address.)
</off-topic>


Also FYI, my hobby FPGA project (target XC2S200, tool JBits on Linux,
hey!, back on topic!) is an freeware (public domain, not GPL) PDP-10
clone. Initially aimed at KI-10 compatible with TOPS-10, but extension
to KL-10 and TOPS-20 possible.


--
Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/
Hacker, Unix Guru, El Eng HTL/BSc, Sysadmin, Archer, Roleplayer
- Intellectual Property is Intellectual Robbery

Article: 31138
Subject: Meet others in you area tonight!! Free AD placement!
From: pxwwxp@you.com
Date: Sat, 12 May 2001 21:05:10 GMT
Links: << >>  << T >>  << A >>
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Article: 31139
Subject: Re: Finally, an FPGA tool chain for Linux (Altera Quartus II)
From: Neil Franklin <neil@franklin.ch.remove>
Date: 12 May 2001 23:06:14 +0200
Links: << >>  << T >>  << A >>
martin capitanio <martin@capitanio.org> writes:

> Eric Smith wrote:
>
> > It would, but I harbor no fantasies of Xilinx releasing any tools as
> > open source.  Even JBits is not open source.
> Look at JDrive.

What is that? Where is there info on it?


> It's possibly unusable, but OS

One can allways investigate it.


> (with the power of GPL have they yet some problems).

Quite a few people have a problem with PGL. I am a Linux user since
over 5 years, founding member of a Linux user group. And I dislike the
GPL and do not put my own software projects under it.

RMS (inventor of the GPL) calls it an "legal hack", I call it law abuse.


--
Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/
Hacker, Unix Guru, El Eng HTL/BSc, Sysadmin, Archer, Roleplayer
- Intellectual Property is Intellectual Robbery

Article: 31140
Subject: Re: Finally, an FPGA tool chain for Linux (Altera Quartus II)
From: Eric Smith <eric-no-spam-for-me@brouhaha.com>
Date: 12 May 2001 16:29:46 -0700
Links: << >>  << T >>  << A >>
Neil Franklin <neil@franklin.ch.remove> writes:
> Methinks, you do not know, that you can still get TOPS-20 v7.xx
> together with fitting hardware TOAD-1 [1] (an KL-10 clone with 30bit
> extended addressing) from XKL (http://www.xkl.com/).

Bzzzt!  No longer commercially available.

Article: 31141
Subject: Re: Finally, an FPGA tool chain for Linux (Altera Quartus II)
From: Rick Collins <spamgoeshere4@yahoo.com>
Date: Sat, 12 May 2001 23:01:36 -0400
Links: << >>  << T >>  << A >>
Phil Hays wrote:
> 
> Rick Collins wrote:
> > Then again some of the tools are nothing to brag about. I find that
> > Modelsim crashes once every 4 or 5 reloads of a design.
> 
> Do you reload or restart the simulation?
> 
> --
> Phil Hays

So far it only crashes when I am reloading a simulation. I often work in
a mode where I find several small bugs one at a time. I fix the problem
in my HDL and reload and restart the simulation. This does not require
that I exit the tool. But once in several reloads, it will get to the
end of complilation and instead of prompting me to input a command, it
crashes. Then I have to run Modelsim again and reload the simulation. 


-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 31142
Subject: Re: Finally, an FPGA tool chain for Linux (Altera Quartus II)
From: Phil Hays <spampostmaster@home.com>
Date: Sun, 13 May 2001 03:46:50 GMT
Links: << >>  << T >>  << A >>
Neil Franklin wrote:

Sorry, but XKL is no longer selling the TOAD.


-- 
Phil Hays

Article: 31143
Subject: Re: Finally, an FPGA tool chain for Linux (Altera Quartus II)
From: hamish@cloud.net.au
Date: Sun, 13 May 2001 07:10:15 GMT
Links: << >>  << T >>  << A >>
Kolja Sulimma <kolja@prowokulta.org> wrote:
> On the other hand: Large parts of tools have not even been ported to Windows
> 95 yet:
> No long file names, and the backend tools run in a 16-Bit environment.

Oh? The backend tools work fine with long filenames on NT and 2000.
I don't use the front end tools (design manager, etc); Alliance only.

Hamish
-- 
Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>

Article: 31144
Subject: Re: Implementation Of LUT in Vertex-E
From: Lasse Langwadt Christensen <langwadt@ieee.org>
Date: Sun, 13 May 2001 01:54:43 -0700
Links: << >>  << T >>  << A >>
Falk Brunner wrote:
> 
> A. I. Khan schrieb:
> >
> > Hi all !
> >
> > I'll appreciate if anyone could facilitate me with some idea  to
> > implement LUT (4096  words depth with 10 bits width) in Vertex-E (Part:
> > V1000EBG 560) for FPGA.
> 
> Sounds like you need a 4096x10bit ROM??
> Just use the Core-Generator to get 8 512x8bit ROMS made of BlockRAM
> (gives you 4096x8bits) plus 2 2048x2bit ROMS.
> Add an appropiate chip select decoder and you are done.

why not just generate a 4096x10bit rom in coregen???

> You can also use 10 4096x1bit ROMS (no chip select decoder
> required),this depends a little bit on the required speed.
> Dont use the LUTs for such a BIG ROM.
> 
> --
> MFG
> Falk

I'd think something like this should work, you'll just have to figure
out
how to initialize it; 

RAMB4_S1 
U0(.DO(DO[0]),.ADDR(ADR),.CLK(CLK),.EN(1'b1),.WE(1'b0),.RST(1'b0));
..
RAMB4_S1 
U9(.DO(DO[9]),.ADDR(ADR),.CLK(CLK),.EN(1'b1),.WE(1'b0),.RST(1'b0));



-Lasse

-- Lasse Langwadt Christensen, 
-- PHX,AZ

Article: 31145
Subject: VirtexblockRAM bug
From: "Paul McCanny" <p.mccanny@ee.qub.ac.uk>
Date: Sun, 13 May 2001 11:59:50 +0100
Links: << >>  << T >>  << A >>
Hi,
I was wondering if anybody else was having problems using the Virtex2
blockRAM.  I have a piece of code that uses the two ports provided.  One of
these is set only to read (port A), the other is set to strobe between read
and writes (port B).  When simulating I noticed that the memory doesn't
behave like it should.  For some reason the portB does not seem to
successfully write to the port until the portA clock is activated.  Then
everything works fine.  I hacked a solution to this problem by making portA
clock when reset is held high but I was just wondering if anyone else had
similar problems and if I can expect any more.

Thanks,

Paul



Article: 31146
Subject: Avnet Virtex-E Development Kit
From: "Dave Feustel" <dfeustel@mindspring.com>
Date: Sun, 13 May 2001 06:12:08 -0500
Links: << >>  << T >>  << A >>
Does anyone have any experience with
or opinion of the Avnet Virtex-E Development kit?

Thanks,

Dave Feustel
Fort Wayne, Indiana



Article: 31147
Subject: Re: C++ To Gates
From: "Dave Feustel" <dfeustel@mindspring.com>
Date: Sun, 13 May 2001 07:06:46 -0500
Links: << >>  << T >>  << A >>

"Rick Filipkiewicz" <rick@algor.co.uk> wrote in message news:3AECA74D.36015D44@algor.co.uk...
>
>
> Magnus Homann wrote:
> >
> > Kolja Sulimma <kolja@prowokulta.org> writes:
[snipped]
> o The argument that there are a lot of cheap s/w engineers out there who
> could be turned to doing h/w is also largely a marketing invention. The
> bulk of these C/C++ programmers spend their time writing database query
> apps, complicated GUIs for doing simple tasks, and web programs that use
> all my 128K ISDN bandwidth to flash a red light on & off.
>
> The s/w engineers who *would* take naturally to this are those used to
> writing multi-threaded RTOS code or device drivers or interrupt handlers
> - in short kernel hackers. But these people are (a) at least as rare &
> expensive as h/w engineers and (b) are usually bright enough that they
> could pick up at least the basics of Verilog coding in a few days [VHDL
> might stop them for a little longer but not much]
>

I am a longtime system sw programmer with some hardware experience and
an armchair background in computer architecture suddenly very interested
in FPGAs. I would like to program a couple of  virtual machines (implemented
in C) into FPGAs on a commercially produced FPGA development board and
then play with those VMs  under Windows 2000.  I've pretty much settled on
Xilinx parts  and Verilog as the implementation language but I have no FPGA hw/sw
tools yet. What is the best way to get started along this path?

Thanks,

Dave Feustel



Article: 31148
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From: qnnmoq@you.com
Date: Sun, 13 May 2001 13:36:51 GMT
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Article: 31149
Subject: Getting Started with FPGAs
From: "Dave Feustel" <dfeustel@mindspring.com>
Date: Sun, 13 May 2001 08:41:11 -0500
Links: << >>  << T >>  << A >>
I am a longtime system sw programmer with some hardware experience and
an armchair background in computer architecture suddenly very interested
in FPGAs. I would like to program a couple of  virtual machines (implemented
in C) into FPGAs on a commercially produced FPGA development board and
then play with those VMs  under Windows 2000.  I've pretty much settled on
Xilinx parts  and Verilog as the implementation language but I have no FPGA hw/sw
tools yet. What is the best way to get started along this path?

Thanks,

Dave Feustel







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