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Messages from 31175

Article: 31175
Subject: Re: Bug in Xilinx Hardware Debugger?
From: "Jaan Sirp" <jaan.sirp@mail.ee>
Date: Mon, 14 May 2001 03:22:29 -0700
Links: << >>  << T >>  << A >>
Sorry Xilinx!

The LPT connector of the Insight Memec cable is guilty.

Jaan

Article: 31176
Subject: Re: Huffman decoders
From: Kolja Sulimma <kolja@prowokulta.org>
Date: Mon, 14 May 2001 13:03:39 +0200
Links: << >>  << T >>  << A >>
I am not sure, but as far as I know, JPEG uses pretty small, static Huffman
tables.

In this case you can use a BlockRAM to describe a discrete finite automaton that
decodes Huffman codes at
n+1 cycles for a n-bit code word.

For an internal node:
1 & table row of left child & table row of right child

For a leaf:
0 & output symbol

Than you use a simple state machine to walk this tree.
With a little more effort you can do 1, 2 or 4 input bits per cycle using larger
RAMs.
Clock Frequency should be at least 100 MHz in a Spartan-II. The size without the
RAMs shold be 20 LUTs or so.

The ocean-logic approach of 1 cylce per codeword employs a logarithmic shifter
which get rather large for
larger code words and slow the clock frequency down. Check carefully whether you
need this.

CU,

Kolja Sulimma

Gareth wrote:

> Hi,
>
> I'm interested in using a huffman decoder as part of a jpeg project. So far,
> I've seen a core from Ocean Logic
> (http://www.ocean-logic.com/pub/OL_Huff.pdf), but the datasheet seems a bit
> non descriptive (the same core pops up in a few places under license, I
> think;
> Xentec seem to do the same one). Does anyone know about / can anyone
> recommend
> a core for this task, or have info on price, clock speed, size, etc?
>
> Thanks,
>
> G


Article: 31177
Subject: Re: Leonardo/Modelsim/Xilinx post synthesis simulation (VHDL)
From: Alan Fitch <alan.fitch@doulos.com>
Date: Mon, 14 May 2001 13:56:27 +0100
Links: << >>  << T >>  << A >>
In article <aZyK6.1180$bi2.94543@www.newsranger.com>, Darrell Gibson
<nospam@newsranger.com> writes
>I'm experiencing some problems trying to perform functional post-synthesis
>simulation on a VHDL net-list generated by Leonardo (v1999.1d build 6.60)
>following targeting to a Xilinx xc4000XL device.  The VHDL net-list generated
>from Leonardo contains illegal VHDL characters.  Specifically all references to
>a net are placed in backslash's. (The net is nx2087 and in the VHDL net-list is
>appears as /_nx2087/).  As a result the net-list can not be compiled for
>simulation without removing these extra characters.  I'd like to assume that
>Leonardo has identified a problem with this particular net and has therefore
>inserted the illegal characters to make the designer aware of the problem.  I
>have scoured the transcript log and I can find no reason for any a problem
>occurring on this net.  I've searched the Leonardo documentation but can find no
>reference to this problem.  I have tried changing the target device to other
>Xilinx FPGA's.  Using 3000 series the problem disappears.  Using Virtex I have
>the same problem but it occurs on a lot more nets.
>

The characters are not illegal, they are VHDL 93 extended character set
characters. Therefore

a) either tell Leonardo to write out VHDL '87

b) tell your simulator to compile the file as VHDL '93

kind regards

Alan

-- 
Alan Fitch
DOULOS Ltd.
Church Hatch, 22 Market Place, Ringwood, Hampshire BH24 1AW, United Kingdom
Tel: +44 1425 471223                        Email: alan.fitch@doulos.com
Fax: +44 1425 471573                             Web: http://www.doulos.com

                   **********************************
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are not the views of Doulos Ltd., unless specifically stated.









Article: 31178
Subject: Re: Getting Started with FPGAs
From: NOj.duranNO@bcn.NOservicom.es
Date: Mon, 14 May 2001 14:24:05 GMT
Links: << >>  << T >>  << A >>
On Sun, 13 May 2001 08:41:11 -0500, "Dave Feustel"
<dfeustel@mindspring.com> wrote:

>I am a longtime system sw programmer with some hardware experience and
>an armchair background in computer architecture suddenly very interested
>in FPGAs. I would like to program a couple of  virtual machines (implemented
>in C) into FPGAs on a commercially produced FPGA development board and
>then play with those VMs  under Windows 2000.  I've pretty much settled on
>Xilinx parts  and Verilog as the implementation language but I have no FPGA hw/sw
>tools yet. What is the best way to get started along this path?
>
>Thanks,
>
>Dave Feustel
>
>

I was in a similar position some three months ago. I chose the XESS
XS-4010XL+ board with the XILINX Foundation v2.1 Student Edition, and
after spending ~$200 and ~1 month of my time I am happy with it.

Of  course neither the 4010XL nor the Found. v2.1 are the latest
technology, but now I  will be able to choose my new hw/sw according
to my  real experience.

Josep Duran.


Article: 31179
Subject: test
From: "zinger" <hcliu@newavetech.com>
Date: Mon, 14 May 2001 22:48:42 +0800
Links: << >>  << T >>  << A >>
test




Article: 31180
Subject: Re: Post timing: $setup( negedge RST:1372505 ps, posed
From: Brian Philofsky <brian.philofsky@xilinx.com>
Date: Mon, 14 May 2001 09:51:12 -0600
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.
--------------9CE2A1543358618EBDAF94E6
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Hello Roger,

   At simulation time 1372716 ps the reset of some registers with the instance name /tf/FPGA/\pts_unit0/shifter_low is going low while some 191 ps later at time 1372907
ps your clock for these registers is going high while the registers are clock enabled.  Since the setup time for these registers are reported as 479 ps, a setup
violation is reported.

    Since you can decipher the offending register names, I would go back to the Timing Analyzer and find out what the static timing is for the resets for this path and
see how it matches up with your simulation environment.  How to fix this depends on what the static timing analysis reveals and what the source of the reset signal is.

Some suggested reading can be found on the Xilinx web site at : http://support.xilinx.com/techdocs/10629.htm and http://support.xilinx.com/techdocs/5255.htm

Good luck,


--  Brian


"Roger.chen" wrote:

> We are using VirtexII XC2V1000FG456 in our design.the development software is Foundation iSE3.3i,Simulation tool is ModelSim
> We have passed Place and route,and found no timing errors,the minimum slack is about 0.3ns(clocked at 200MHz). but in doing post timing,We find the following error:
>
>    ** Error: C:/XILINX/verilog/src/simprims/X_FF.v(55): $setup( negedge RST:1372716 ps, posedge CLK &&& (CE == 1):1372907 ps, 479 ps );
> #    Time: 1372907 ps  Iteration: 0  Instance: /tf/FPGA/\pts_unit0/shifter_low[24]\
> # ** Error: C:/XILINX/verilog/src/simprims/X_FF.v(55): $setup( negedge RST:1372716 ps, posedge CLK &&& (CE == 1):1372907 ps, 479 ps );
> #    Time: 1372907 ps  Iteration: 0  Instance: /tf/FPGA/\pts_unit0/shifter_low[9]\
> # ** Error: C:/XILINX/verilog/src/simprims/X_FF.v(55): $setup( negedge RST:1372716 ps, posedge CLK &&& (CE == 1):1372907 ps, 479 ps );
> #    Time: 1372907 ps  Iteration: 0  Instance: /tf/FPGA/\pts_unit0/shifter_low[8]\
> # ** Error: C:/XILINX/verilog/src/simprims/X_FF.v(55): $setup( negedge RST:1372505 ps, posedge CLK &&& (CE == 1):1372908 ps, 479 ps );
> #    Time: 1372908 ps  Iteration: 0  Instance: /tf/FPGA/\pts_unit5/shifter_low[7]\
> # ** Error: C:/XILINX/verilog/src/simprims/X_FF.v(55): $setup( negedge RST:1372505 ps, posedge CLK &&& (CE == 1):1372908 ps, 479 ps );
> #    Time: 1372908 ps  Iteration: 0  Instance: /tf/FPGA/\pts_unit5/shifter_low[6]\
>
> Where the problem lies?
> Thank you.

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email;internet:brian.philofsky@xilinx.com
title:Sr Technical Marketing Engineer
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--------------9CE2A1543358618EBDAF94E6--


Article: 31181
Subject: Re: Nasty "register ordering" in map
From: John_H <johnhandwork@mail.com>
Date: Mon, 14 May 2001 09:00:06 -0700
Links: << >>  << T >>  << A >>
Although it doesn't look like the dsgnmgr user interface allows me to access the feature, I remembered seeing the register ordering issue in the tools.

If you try the command line form of the map utility, "map -h virtexe" will give you the options applicable to the Virtex-E family.  The -r option disables register ordering.

Patrick -
Thanks for the reminder about the BLKNM;  I may try working it into my current design.  The concept is good - I'll see about the execution.

Article: 31182
Subject: Re: Fine phase shift in Virtex2
From: Brian Philofsky <brian.philofsky@xilinx.com>
Date: Mon, 14 May 2001 10:16:02 -0600
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.
--------------FC7F2B10F955BD0A6839CF2C
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit



Hello Meelis,

    The attribute you are setting is for synthesis only.  Unfortuanately, you
must apply one attribute for synthesis and one for simulation to get this to
simulate and implement properly.  The way to pass simulation attributes is by
modifying the generic declaration or generic mapping of the DCM primitive or
instance.  This can be done in the component declaration, generic port mapping
or from a configuration statement.  If you are only using one DCM, it is
probably easiest just to modify the component declaration to:

component DCM
  -- synopsys translate_off
 generic (
    DLL_FREQUENCY_MODE : string := "HIGH";
    CLKOUT_PHASE_SHIFT : string := "FIXED";
    PHASE_SHIFT  : integer := 64 ;
     );
  -- synopsys translate_on
 port ( CLKIN : in std_logic;
        CLKFB : in std_logic;
        DSSEN : in std_logic;
        PSINCDEC : in std_logic;
        PSEN : in std_logic;
        PSCLK : in std_logic;
        RST : in std_logic;
        CLK0 : out std_logic;
        CLK90 : out std_logic;
        CLK180 : out std_logic;
        CLK270 : out std_logic;
        CLK2X : out std_logic;
        CLK2X180 : out std_logic;
        CLKDV : out std_logic;
        CLKFX : out std_logic;
        CLKFX180 : out std_logic;
        LOCKED : out std_logic;
        PSDONE : out std_logic;
        STATUS : out std_logic_vector(7 downto 0)
      );
end component;


Try that out and see if the simulation starts working for you.

Good Luck,


--  Brian



Meelis Kuris wrote:

> Hi!
>
> I need to shift phase of 270MHz clock signal 90 degrees.
> As I can't use CLK90 output of DCM in high frequency mode,
> I'm using fine phase shift of clk0 output.
> For some reason it doesn't work in simulation, output clock is
> still exactly phase-aligned to the input clock.
> I'm using Modelsim XE, with new libraries from xilinx site.
>
> Am I doing something wrong or is it just the simulation software?
>
> Thanks in advance,
>
> Meelis
>
> Here's the source:
> ----------------------------------------------------------
> entity tb is
> end tb;
>
> architecture tb_a of tb is
>
> component DCM
>
>     port ( CLKIN     : in  std_logic;
>            CLKFB     : in  std_logic;
>            DSSEN     : in  std_logic;
>            PSINCDEC  : in  std_logic;
>            PSEN      : in  std_logic;
>            PSCLK     : in  std_logic;
>            RST       : in  std_logic;
>            CLK0      : out std_logic;
>            CLK90     : out std_logic;
>            CLK180    : out std_logic;
>            CLK270    : out std_logic;
>            CLK2X     : out std_logic;
>            CLK2X180  : out std_logic;
>            CLKDV     : out std_logic;
>            CLKFX     : out std_logic;
>            CLKFX180  : out std_logic;
>            LOCKED    : out std_logic;
>            PSDONE    : out std_logic;
>            STATUS    : out std_logic_vector(7 downto 0)
>           );
> end component;
>
> attribute DLL_FREQUENCY_MODE : string;
> attribute CLKOUT_PHASE_SHIFT : string;
> attribute PHASE_SHIFT  : integer;
>
> attribute DLL_FREQUENCY_MODE of dcm1: label is "HIGH";
> attribute CLKOUT_PHASE_SHIFT of dcm1: label is "FIXED";
> attribute PHASE_SHIFT  of dcm1: label is 64; -- actual phase shift is period
> * PHASE_SHIFT / 256
>
> component bufg port (
>  I  : in std_logic;
>  O  : out std_logic);
> end component;
>
> signal clk, clk90, gnd, Reset, clk90DCM1o : std_logic:='0';
>
> begin
> gnd <= '0';
> Reset <='0';
> clk<= not clk after 10 ns;
>
> dcm1 : DCM
>
>  port map (
>  CLKIN => clk,
>  CLKFB => clk90,
>  DSSEN => gnd,
>  PSINCDEC => gnd,
>  PSEN => gnd,
>  PSCLK => gnd,
>  RST => Reset,
>  CLK0 => clk90DCM1o
>  );
>
> bufg5 : bufg port map(
>  I => clk90DCM1o,
>  O => clk90 );
>
> end tb_a;

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--------------FC7F2B10F955BD0A6839CF2C--


Article: 31183
Subject: Re: Implementation Of LUT in Vertex-E
From: Falk Brunner <Falk.Brunner@gmx.de>
Date: Mon, 14 May 2001 18:31:17 +0200
Links: << >>  << T >>  << A >>
Lasse Langwadt Christensen schrieb:
> 
> > Add an appropiate chip select decoder and you are done.
> 
> why not just generate a 4096x10bit rom in coregen???

Too easy ;-))

-- 
MFG
Falk


Article: 31184
Subject: Re: Fine phase shift in Virtex2
From: Austin Lesea <austin.lesea@xilinx.com>
Date: Mon, 14 May 2001 09:32:58 -0700
Links: << >>  << T >>  << A >>

--------------6B32C23081301DFA70310208
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

Meelis,

>From the answers database:

 http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=9949

________________________________________________

Answers Database
Virtex-II - CLKDLL simulation may not be correct if the
multiply, divide, and phase shift outputs are used.
Family:
Product Line:
Part:
Version:
Record Number: 9949
Last Modified: 08/22/00 16:15:07
Status: Active
Problem Description:

Keywords: CLKDLL, Functional, Timing, Backannotate, Unisim, Simprim,
Simulation, multiply, divide,phase

Urgency: Standard

Problem Description:
There is an inconstency in the Virtex-II CLKDLL property value types for
multiply,
divide and phase shift. The unisim, and simprim value type is specified as
hexadecimal, whereas MAP and Ngdanno specify integer value types. This
 inconsistency creates data corruption in either the functional simulation
(pre-
ngdbuild) or backannotated timing simulation.

Solution 1:

Currently there is no workaround. This problem will be fixed in a future 3.1i
release.

______________________________________________

Austin

Meelis Kuris wrote:

> "Austin Lesea" <austin.lesea@xilinx.com> wrote in message
> news:3AFF54B3.50B5DD4B@xilinx.com...
> > Meelis,
> >
> > I know the fixed phase shift works in silicon (my lab people tested it,
> and I
> > have tested it, too).
> >
> > I suggest emailing the hotline for a a quick response.
> >
> >  http://www.support.xilinx.com/support/clearexpress/websupport.htm
>
> Well: "WebCase is NOT available to students."
> And that's exactly what I am. I just can't get to that web page.
>
> Meelis

--------------6B32C23081301DFA70310208
Content-Type: text/html; charset=us-ascii
Content-Transfer-Encoding: 7bit

<!doctype html public "-//w3c//dtd html 4.0 transitional//en">
<html>
Meelis,
<p>From the answers database:
<p>&nbsp;<a href="http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=9949">http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&amp;iCountryID=1&amp;getPagePath=9949</a>
<p>________________________________________________
<p>Answers Database
<br>Virtex-II - CLKDLL simulation may not be correct if the
<br>multiply, divide, and phase shift outputs are used.
<br>Family:
<br>Product Line:
<br>Part:
<br>Version:
<br>Record Number: <b>9949</b>
<br>Last Modified: 08/22/00 16:15:07
<br>Status: Active
<br>Problem Description:
<p>Keywords: CLKDLL, Functional, Timing, Backannotate, Unisim, Simprim,
Simulation, multiply, divide,phase
<p>Urgency: Standard
<p>Problem Description:
<br>There is an inconstency in the Virtex-II CLKDLL property value types
for multiply,
<br>divide and phase shift. The unisim, and simprim value type is specified
as
<br>hexadecimal, whereas MAP and Ngdanno specify integer value types. This
<br>&nbsp;inconsistency creates data corruption in either the functional
simulation (pre-
<br>ngdbuild) or backannotated timing simulation.
<p>Solution 1:
<p>Currently there is no workaround. This problem will be fixed in a future
3.1i release.
<p>______________________________________________
<p>Austin
<p>Meelis Kuris wrote:
<blockquote TYPE=CITE>"Austin Lesea" &lt;austin.lesea@xilinx.com> wrote
in message
<br><a href="news:3AFF54B3.50B5DD4B@xilinx.com">news:3AFF54B3.50B5DD4B@xilinx.com</a>...
<br>> Meelis,
<br>>
<br>> I know the fixed phase shift works in silicon (my lab people tested
it,
<br>and I
<br>> have tested it, too).
<br>>
<br>> I suggest emailing the hotline for a a quick response.
<br>>
<br>>&nbsp; <a href="http://www.support.xilinx.com/support/clearexpress/websupport.htm">http://www.support.xilinx.com/support/clearexpress/websupport.htm</a>
<p>Well: "WebCase is NOT available to students."
<br>And that's exactly what I am. I just can't get to that web page.
<p>Meelis</blockquote>
</html>

--------------6B32C23081301DFA70310208--


Article: 31185
Subject: Re: Fine phase shift in Virtex2
From: Austin Lesea <austin.lesea@xilinx.com>
Date: Mon, 14 May 2001 09:37:13 -0700
Links: << >>  << T >>  << A >>
Meelis,

For University and Student support:

 http://xup.msu.edu/

They have their own hotline,

Austin

Meelis Kuris wrote:

> "Austin Lesea" <austin.lesea@xilinx.com> wrote in message
> news:3AFF54B3.50B5DD4B@xilinx.com...
> > Meelis,
> >
> > I know the fixed phase shift works in silicon (my lab people tested it,
> and I
> > have tested it, too).
> >
> > I suggest emailing the hotline for a a quick response.
> >
> >  http://www.support.xilinx.com/support/clearexpress/websupport.htm
>
> Well: "WebCase is NOT available to students."
> And that's exactly what I am. I just can't get to that web page.
>
> Meelis


Article: 31186
Subject: Re: Fine phase shift in Virtex2
From: Austin Lesea <austin.lesea@xilinx.com>
Date: Mon, 14 May 2001 10:09:28 -0700
Links: << >>  << T >>  << A >>
Should be working now since Service Pack 5,

Austin

Meelis Kuris wrote:

> "Austin Lesea" <austin.lesea@xilinx.com> wrote in message
> news:3AFF54B3.50B5DD4B@xilinx.com...
> > Meelis,
> >
> > I know the fixed phase shift works in silicon (my lab people tested it,
> and I
> > have tested it, too).
> >
> > I suggest emailing the hotline for a a quick response.
> >
> >  http://www.support.xilinx.com/support/clearexpress/websupport.htm
>
> Well: "WebCase is NOT available to students."
> And that's exactly what I am. I just can't get to that web page.
>
> Meelis


Article: 31187
Subject: Quad Decoder
From: "vi" <vi_ismyname@hotmail.com>
Date: Mon, 14 May 2001 10:17:04 -0700
Links: << >>  << T >>  << A >>
Anyone have a quadrature decoder in a schematic format to share?  I have
done it with D F/Fs and it work under simulation, but it did not work very
well under real test.  I used Xilinx and Orcad schematic capture.

cheer



Article: 31188
Subject: Re: Quad Decoder
From: Eric <erv_nospam@sympatico.ca>
Date: Mon, 14 May 2001 18:08:12 GMT
Links: << >>  << T >>  << A >>
You'll find exactly what you're looking for in this Xilinx Application note :

http://www.xilinx.com/xapp/xapp012.pdf

Hope this helps,

Eric.

--------------------------

vi wrote:

> Anyone have a quadrature decoder in a schematic format to share?  I have
> done it with D F/Fs and it work under simulation, but it did not work very
> well under real test.  I used Xilinx and Orcad schematic capture.
>
> cheer


Article: 31189
Subject: Re: Quad Decoder
From: "vi" <vi_ismyname@hotmail.com>
Date: Mon, 14 May 2001 11:27:17 -0700
Links: << >>  << T >>  << A >>
Thanks for the response, but I already have look at his AppNote.
A schematic format of the decoder would be nice(I have not done state
machine for a very long time).  It is for a stepper motor control.

Eric <erv_nospam@sympatico.ca> wrote in message
news:3B001F54.2FB89B97@sympatico.ca...
> You'll find exactly what you're looking for in this Xilinx Application
note :
>
> http://www.xilinx.com/xapp/xapp012.pdf
>
> Hope this helps,
>
> Eric.
>
> --------------------------
>
> vi wrote:
>
> > Anyone have a quadrature decoder in a schematic format to share?  I have
> > done it with D F/Fs and it work under simulation, but it did not work
very
> > well under real test.  I used Xilinx and Orcad schematic capture.
> >
> > cheer
>



Article: 31190
Subject: unix!
From: Sudhir Sakhuja <sudhir@ftghome.com>
Date: Mon, 14 May 2001 14:40:06 -0400
Links: << >>  << T >>  << A >>
Hi unix gurus/learners,

There is an exciting new web site at http://www.unixboulevard.com which

focuses
on  unix.
The site has features like Chat Rooms, News Groups , Mailing List ,

Project
oportunities for free-lancer's. The site has  good downloadable utilites

and expert
tips on unix environment/administration.
Site allows you to post articles and take part in most of the features

present in this
highly focused site you are the owner!
This is your site and you are the one who can take this unix community

site  to  next
level.
So join the community today at http://www.unixbolevard.com to help unix

grow.

Cya!

Sudhir Sakhuja
Fusion Technology Group
http://www.ftghome.com
Lets build a unix community @ http://www.unixbolevard.com


Article: 31191
Subject: Re: Quad Decoder
From: Eric <erv_nospam@sympatico.ca>
Date: Mon, 14 May 2001 19:05:59 GMT
Links: << >>  << T >>  << A >>
Ok, I'm doing your homework for you :

http://www3.sympatico.ca/erv/quadrature.gif

Remember this road goes both ways, and it would be appreciated if you would
post the diagram for your stepper controller once it's finished.

Éric.

---------------------------

vi wrote:

> Thanks for the response, but I already have look at his AppNote.
> A schematic format of the decoder would be nice(I have not done state
> machine for a very long time).  It is for a stepper motor control.
>
> Eric <erv_nospam@sympatico.ca> wrote in message
> news:3B001F54.2FB89B97@sympatico.ca...
> > You'll find exactly what you're looking for in this Xilinx Application
> note :
> >
> > http://www.xilinx.com/xapp/xapp012.pdf
> >
> > Hope this helps,
> >
> > Eric.
> >
> > --------------------------
> >
> > vi wrote:
> >
> > > Anyone have a quadrature decoder in a schematic format to share?  I have
> > > done it with D F/Fs and it work under simulation, but it did not work
> very
> > > well under real test.  I used Xilinx and Orcad schematic capture.
> > >
> > > cheer
> >


Article: 31192
Subject: Unix!!!!!!!!!!
From: Sudhir Sakhuja <sudhir@ftghome.com>
Date: Mon, 14 May 2001 15:15:52 -0400
Links: << >>  << T >>  << A >>
Hi unix gurus/learners,

There is an exciting new web site at http://www.unixboulevard.com which

focuses on  unix.
The site has features like Chat Rooms, News Groups , Mailing List ,

Project oportunities for free-lancer's. The site has  good downloadable

utilites and expert tips on unix environment/administration.
The site is on its way past the beta stage,site allows you to post
articles and interactively take part in most of the features.
This is your site and you are the one who can take this unix community

site  to  next level.
So join the community today at http://www.unixboulevard.com to help unix

grow.

Cya!

Sudhir Sakhuja
Fusion Technology Group
http://www.ftghome.com
Lets build a unix community @ http://www.unixboulevard.com


Article: 31193
Subject: Re: Quad Decoder
From: "vi" <vi_ismyname@hotmail.com>
Date: Mon, 14 May 2001 12:22:34 -0700
Links: << >>  << T >>  << A >>
Whats your email?? erv_@sympatico.ca ?

Eric <erv_nospam@sympatico.ca> wrote in message
news:3B002CDE.ACC2B89F@sympatico.ca...
> Ok, I'm doing your homework for you :
>
> http://www3.sympatico.ca/erv/quadrature.gif
>
> Remember this road goes both ways, and it would be appreciated if you
would
> post the diagram for your stepper controller once it's finished.
>
> Éric.
>
> ---------------------------
>
> vi wrote:
>
> > Thanks for the response, but I already have look at his AppNote.
> > A schematic format of the decoder would be nice(I have not done state
> > machine for a very long time).  It is for a stepper motor control.
> >
> > Eric <erv_nospam@sympatico.ca> wrote in message
> > news:3B001F54.2FB89B97@sympatico.ca...
> > > You'll find exactly what you're looking for in this Xilinx Application
> > note :
> > >
> > > http://www.xilinx.com/xapp/xapp012.pdf
> > >
> > > Hope this helps,
> > >
> > > Eric.
> > >
> > > --------------------------
> > >
> > > vi wrote:
> > >
> > > > Anyone have a quadrature decoder in a schematic format to share?  I
have
> > > > done it with D F/Fs and it work under simulation, but it did not
work
> > very
> > > > well under real test.  I used Xilinx and Orcad schematic capture.
> > > >
> > > > cheer
> > >
>



Article: 31194
Subject: Re: Xilinx and Actel
From: Tom <tomcip@concentric.net>
Date: 14 May 2001 19:23:05 GMT
Links: << >>  << T >>  << A >>
Chris,

I have been programing FPGAs and CPLDs for better then 15 years now and I
have nothing against Actel as a company. However, Actel has been nipping at
the heals of Altera and Xilinx for over 10 years. No matter what they claim,
their market share can be no better then 10%.

What has this got to do with anything? Plenty!

Both Xilinx and Altera have large device product lines. One or the other of
their devices could probably serve your needs without having to change
software, which would be a major headache.

The larger companies also have big tech support infrastructures. No matter
how much you think you might know, the devices are changing so fast that tech
support always remains important.

Ask some questions of your customer. What is so important about using the
Actel Anti-fuse technology? What is so iimportant about using ANY technology.
The objective of design engineering is to design that which the customer
requires within their cost and functionality constraints. What difference
does it make which technology is used if the technology works and is
affordable? Does the customer have a predjudice? Did the customer read some
kind of markting blurb from Actel? Do they own stock in Actel? Never believe
the marketing hype.

My guess is that the customer has some kind of Actel toolset and does not
want to have an outside consultant use devices which he can not program.

I hope that this helps.

Tom


Chris Eilbeck wrote:

> Has anyone used both?  I'm used to the Xilinx toolchain and devices
> but a client wants a project done using Actel antifuse.  Are there any
> objective comparisons anywhere on the web or does anyone have any
> opinions as to how hard it would be to make the change?
>
> Ta
>
> Chris
> --
> Chris Eilbeck                             mailto:chris@yordas.demon.co.uk
> MARS Flight Crew                                  http://www.mars.org.uk/
> UKRA #1108 Level 1                                                   BSMR


Article: 31195
Subject: Re: Quad Decoder
From: Eric <erv_nospam@sympatico.ca>
Date: Mon, 14 May 2001 15:49:08 -0400
Links: << >>  << T >>  << A >>
Should I answer this one ?

If I take time to add a "_nospam" part to my email to prevent spam bots
from finding it as they harvest the newsgroup, I'd appreciate if you could
refrain from trying to post it in the clear ...

Fortunately, you missed it by 1 char (guess which one that is) and please
don't post the result in here ...

Thanks.

Eric.

----------------------------------------------------------

vi wrote:

> Whats your email?? erv_@sympatico.ca ?
>
> Eric <erv_nospam@sympatico.ca> wrote in message
> news:3B002CDE.ACC2B89F@sympatico.ca...
> > Ok, I'm doing your homework for you :
> >
> > http://www3.sympatico.ca/erv/quadrature.gif
> >
> > Remember this road goes both ways, and it would be appreciated if you
> would
> > post the diagram for your stepper controller once it's finished.
> >
> > Éric.
> >
> > ---------------------------
> >
> > vi wrote:
> >
> > > Thanks for the response, but I already have look at his AppNote.
> > > A schematic format of the decoder would be nice(I have not done state
> > > machine for a very long time).  It is for a stepper motor control.
> > >
> > > Eric <erv_nospam@sympatico.ca> wrote in message
> > > news:3B001F54.2FB89B97@sympatico.ca...
> > > > You'll find exactly what you're looking for in this Xilinx Application
> > > note :
> > > >
> > > > http://www.xilinx.com/xapp/xapp012.pdf
> > > >
> > > > Hope this helps,
> > > >
> > > > Eric.
> > > >
> > > > --------------------------
> > > >
> > > > vi wrote:
> > > >
> > > > > Anyone have a quadrature decoder in a schematic format to share?  I
> have
> > > > > done it with D F/Fs and it work under simulation, but it did not
> work
> > > very
> > > > > well under real test.  I used Xilinx and Orcad schematic capture.
> > > > >
> > > > > cheer
> > > >
> >


Article: 31196
Subject: Re: Quad Decoder
From: Eric <erv_nospam@sympatico.ca>
Date: Mon, 14 May 2001 15:55:39 -0400
Links: << >>  << T >>  << A >>
Should I answer this one ?

If I take time to add a "_nospam" part to my email to prevent spam bots
from finding it as they harvest the newsgroup, I'd appreciate if you could
refrain from trying to post it in the clear ...

Fortunately, you missed it by 1 char (guess which one that is) and please
don't post the result in here ...

Thanks.

Eric.

----------------------------------------------------------

vi wrote:

> Whats your email?? erv_@sympatico.ca ?
>
> Eric <erv_nospam@sympatico.ca> wrote in message
> news:3B002CDE.ACC2B89F@sympatico.ca...
> > Ok, I'm doing your homework for you :
> >
> > http://www3.sympatico.ca/erv/quadrature.gif
> >
> > Remember this road goes both ways, and it would be appreciated if you
> would
> > post the diagram for your stepper controller once it's finished.
> >
> > Éric.
> >


Article: 31197
Subject: Re: Implementation Of LUT in Vertex-E
From: Falk Brunner <Falk.Brunner@gmx.de>
Date: Mon, 14 May 2001 22:18:47 +0200
Links: << >>  << T >>  << A >>
Lasse Langwadt Christensen schrieb:
> 
> > Add an appropiate chip select decoder and you are done.
> 
> why not just generate a 4096x10bit rom in coregen???

Too easy ;-))

-- 
MFG
Falk

Article: 31198
Subject: Re: Xilinx and Actel
From: Duane Clark <dclark@akamail.com>
Date: Mon, 14 May 2001 14:59:47 -0700
Links: << >>  << T >>  << A >>
Chris Eilbeck wrote:
> 
> Has anyone used both?  I'm used to the Xilinx toolchain and devices
> but a client wants a project done using Actel antifuse.  Are there any
> objective comparisons anywhere on the web or does anyone have any
> opinions as to how hard it would be to make the change?

Is this for space stuff, using the radhard parts, perhaps? I prefer the
Xilinx parts but have done several designs with the radhard Actel 1020s
and 1280s. I have not tried the newer Actel parts, so I don't know
anything about those. The basic Actel Desktop tools are very easy to
use, and you should have no problem migrating to Actel from Xilinx. They
are very basic "click the go button" style of tools. I do not use the
Veribest design tools that come with it, so cannot comment on that. 

The most annoying difference is that these parts do not have a built in
power on reset. So you often need to put a little extra effort into
reset circuitry, even if it is sometimes solely to make the simulation
work well. The structure of the 1020s and 1280s is basic muxes and
flipflops, with none of the carry chains and RAM cells of the Xilinx
parts. Arithmetic functions are significantly more cumbersome and slower
because of that. Floorplanning probably is not necessary, as I can often
achieve well over 90% utilization at reasonable speeds without it. The
chip viewer/editor is just about useless in my opinion.

> 
> Chris
> --
> Chris Eilbeck                             mailto:chris@yordas.demon.co.uk
> MARS Flight Crew                                  http://www.mars.org.uk/
> UKRA #1108 Level 1                                                   BSMR

Article: 31199
Subject: Important News
From: <sasx888er_666@yahoo.com>
Date: 14 May 2001 22:04:03 GMT
Links: << >>  << T >>  << A >>
Herpes Sufferers,
 new guaranteed treatment!
http://reflect.to/life



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