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Messages from 31375

Article: 31375
Subject: Re: FPGA consultant needed
From: John_H <>
Date: Mon, 21 May 2001 08:18:46 -0700
Links: << >>  << T >>  << A >>
Ummm...  Eric #2:
  "on behalf of Altera."

It doesn't seem in appropriate; this is where some good FPGA folks can be found!  It's a forum for FPGA designers of all types.  Where better to find someone with the technical knowledge required?

Article: 31376
Subject: Maximum clock frequency to expect in Xilinx Virtex FPGA ?
From: jimmie.landerman@axis.com (Jimmie)
Date: 21 May 2001 08:43:36 -0700
Links: << >>  << T >>  << A >>
Hi all!
I am new to FPGA design, but have been doing ASIC design for some time.

Now we are working on a design that is to be implemented in a Virtex Xilinx FPGA.
Nothing fancy, some counters, crc-calculation a couple of mid-sized state
machines etc.

Without doing to much architecture specific stuff (wants to be able to port
parts of the design to an ASIC later on), could anyone give a ball-park figure
of what clock frequency to expect ? 

I have got some simple designs (state machines) through the synthesis tool (using
verilog and FPGA express), and get figures like 40-50 MHz, does this sound like reasonable
figures to expect?

I would like to reach 100 MHz, but that might demand too much tuning and
architecture specific design.

Also, any opinions about using fpga express with Virtex, good, bad !?

Brgds
Jimmie Landerman

Article: 31377
Subject: Re: FPGA consultant needed
From: Eric Crabill <eric.crabill@xilinx.com>
Date: Mon, 21 May 2001 08:48:18 -0700
Links: << >>  << T >>  << A >>

Exactly!  :)

John_H wrote:
> 
> Ummm...  Eric #2:
>   "on behalf of Altera."

Article: 31378
Subject: Re: JTAG and Debugging
From: steve (Steve Rencontre)
Date: Mon, 21 May 2001 17:24 +0100 (BST)
Links: << >>  << T >>  << A >>
In article <9eb15m$pl5$06$1@news.t-online.com>, 
carlhermann.schlehaus@t-online.de (C.Schlehaus) wrote:

> Hi,
> AFAIK the JTAG Interface could be used to read the actual status
> (low or high) of any I/O Pin of the ALTERA FPGA and even to apply
> different signals to these Pins.
> Could this JTAG Interface be used to get somewhat of a PC-software
> scope function of one or more pins?
> I'm afraid this could be a timing problem, but it should be possible
> for 'quasistatic' signals, shouldn't it?
> Unfortunately I never found any software for the PC to do this
> job. I hoped, that perhaps ALTERA itself would offer an option
> to use the Byteblaster for this, but they seem to support only
> programming by JTAG.
> Any information regarding the debug capabilities of JTAG and
> especially software would be appreciated,
> Carlhermann Schlehaus

You could download my Personal JTAG package (www.rsn-tech.co.uk/pjtag). 
It's got its limitations, but I've used it in anger on real projects. I 
was originally planning to develop it into a full-scale commercial 
package, but there's always been something more important to do :-)

(But don't bother unless you're running Windows NT - or maybe 2k, which I 
haven't tested. There is no support for any flavour of 9x.)

--
Steve Rencontre		http://www.rsn-tech.co.uk
//#include <disclaimer.h>


Article: 31379
Subject: Re: Maximum clock frequency to expect in Xilinx Virtex FPGA ?
From: "n#" <n@n.com>
Date: Mon, 21 May 2001 18:16:36 +0100
Links: << >>  << T >>  << A >>
The simple answer is 100MHz should be achievable. The longer answer starts
'it depends' and continues with such phrases as 'what speed grade', 'which
Virtex', 'lots of pipelining', etc. etc. I have got some serial adders
running at 180MHz in VirtexE -6, but generally, I find that with designs
with lots of wide-ish adders (32, 48) then 91MHz can be a b'stard sometimes.

for your 40-50 MHz score, is that the estimate from FPGA express? Remember,
it aint over til the bit file is made! Run the P&R to see the truth.

FPGA express works OK for me.

Cheers,

N.

"Jimmie" <jimmie.landerman@axis.com> wrote in message
news:ebd5ee05.0105210743.668c8790@posting.google.com...
> Hi all!
> I am new to FPGA design, but have been doing ASIC design for some time.
>
> Now we are working on a design that is to be implemented in a Virtex
Xilinx FPGA.
> Nothing fancy, some counters, crc-calculation a couple of mid-sized state
> machines etc.
>
> Without doing to much architecture specific stuff (wants to be able to
port
> parts of the design to an ASIC later on), could anyone give a ball-park
figure
> of what clock frequency to expect ?
>
> I have got some simple designs (state machines) through the synthesis tool
(using
> verilog and FPGA express), and get figures like 40-50 MHz, does this sound
like reasonable
> figures to expect?
>
> I would like to reach 100 MHz, but that might demand too much tuning and
> architecture specific design.
>
> Also, any opinions about using fpga express with Virtex, good, bad !?
>
> Brgds
> Jimmie Landerman



Article: 31380
Subject: Re: <no subject>
From: krw@btv.ibm.com (Keith R. Williams)
Date: Mon, 21 May 2001 17:17:55 GMT
Links: << >>  << T >>  << A >>
On Mon, 21 May 2001 12:03:36 +0000 (UTC), floreq10@hotmail.com
("elvira catherina") wrote:

>hello,
>
>till now i am using a schematic entry.
>whenver i design a state machine with  a non consecutives output values(if 
>we can say this, i mean not a simple counter, say [8,5,3,10,15,2]).

IMO VHDL is far easier than schematic capture for state machines. I
could be convinced either way for dataflow.

>To implement this state machine, i use my digital desigin notes, and it's 
>working fine. but i wonder can a VHDl code performs the same task optimally 
>by just using if else constructors.

The normal way of defining an FSM is with a CASE statement.  One can
define the state values, but I've never seen a need to do it.  The
compiler/synthesizer (SynplifyPro, in my case) does a better job of
optomizing than I could. By defining the state vector as an enumerated
type it's easy to try different encodings or let the synthesizer pick
the one it thinks is best for the problem at hand.

>Moreover, sometimes i want at a certain cycle the state machine to be in a 
>certain state , how could i program automatically this in VHDL

I'm not sure what you mean, but to move to a new state just assign the
state variable to that new state.

For example a clocked process with two inputs (no outputs ;-) and four
states.

I could either code with fixed states, such as:

       signal FSMState: std_logic_vector(3 downto 0);

FSM:   process (Clock)             -- FSM (ignore reset)
       begin
       if       rising_edge(Clock) -- On clock edge
         then
           case FSMState is        -- Case on state variable
             when "0001"  =>       --   When in idle state
               if Input1 = '1'     --     If Input is active
                 then FSMState <= "0010";  --  then go to state1
             when STATE1 =>        --   When in state 1
               if Input2 = '1'     --     If input 2 is active
                 then FSMState <= "0100";  --  then go to second state
             when STATE2 =>        --   WHen in state 2
               if Input2 = '0'     --     if input 2 goes low
                 and Input1 = '0'  --        and Input 1 is low
                 then FSMState <= "1000"; --    then go to done state
             when Done   =>        --   When in done state
               FSMState <= "0001"  --     go immediately to IDLE
           end case;
        end if;
        end process;     	  	
------------------------------------------------------------------

Or I could code using a enumerated type and let the synthesis tools
pick the encoding:

type:  MyState  is  (Idle, State1, State2, Done)

FSM:   process (Clock)             -- FSM (ignore reset)
       variable FSMState: MyState; -- Define state variable as type MyState
       begin
       if       rising_edge(Clock) -- On clock edge
         then
           case FSMState is        -- Case on state variable
             when IDLE  =>         --   When in idle state
               if Input1 = '1'     --     If Input is active
                 then FSMState := State1;  --  then go to state1
             when STATE1 =>        --   When in state 1
               if Input2 = '1'     --     If input 2 is active
                 then FSMState := State2;  --  then go to second state
             when STATE2 =>        --   WHen in state 2
               if Input2 = '0'     --     if input 2 goes low
                 and Input1 = '0'  --        and Input 1 is low
                 then FSMState := Done; --    then go to done state
             when Done   =>        --   When in done state
               FSMState := Idle    --     go immediately to IDLE
           end case;
        end if;
        end process;     	  	

I hope this helps (and I didn't make a real big booboo ;-).

----
  Keith       


Article: 31381
Subject: RLocs on Inferred registers??
From: "n#" <n@n.com>
Date: Mon, 21 May 2001 18:18:47 +0100
Links: << >>  << T >>  << A >>
Anyone know a tool that will do this? I have written scripts, used cores
etc. but I still wish I could do this.

Cheers,

N.



Article: 31382
Subject: Hardware Engineer-RTOS,PLD,VXworks,fibre channel
From: Jennifer Walton <jenniferw@scientific.com>
Date: Mon, 21 May 2001 17:33:46 GMT
Links: << >>  << T >>  << A >>
Boston area storage company is looking for a Hardware engineer.

You would be designing innovative high-speed I/O controllers using FPGA'
s and embedded PowerPC (405GP).

The ideal candidate has the following experience: 
5+ years hardware design/development
experience designing I/O controllers with high speed transmissions
extensive background in digital computing and/or networking environment

PLD 
Xilinx 
Fibre Channel
VxWorks and Linux environment PCI
fiber optic
GigE and ESCON or FICON 

This is a ground floor opportunity.  A chance to be instrumental in the 
direction of a new company and an exciting product.  Interested?  Email 
your resume to learn more!



Please email your resume to jenniferw@scientific.com  in plain ascii text 
format (refer to JO# JO59788KAT in your response) or fax to the number 
listed below.

To help us expedite our response, please include information on your current 
salary status and expectations.  If you'd like to be considered for other 
positions similar to the one described above, please provide input on 
relocation preferences in the U.S.

Scientific Placement staff members are knowledgeable specialists in niche 
technology job markets (Multimedia, E-Commerce, Networking/Telecom, Games, 
Embedded Systems, Hardware, and platforms that include: Macintosh, Windows, 
and Unix).

We can provide advice on resume quality, salary levels, and the demand 
for certain skills.  Scientific Placement enjoys a national reputation 
for professionalism, competence, and ethics.  Our clients are scattered 
nationwide and clustered wherever there is a high technology developer 
community.  Fees are employer paid.  For additional information, please 
visit our web site.




Jennifer Walton
Scientific Placement, Inc.
New England Branch
phone:  603-424-3875 
toll free: 877 700 4774
fax: (603) 424-7634
email: jwalton@scientific.com
 http://www.scientific.com

Article: 31383
Subject: Re: Synplicity newsgroup?
From: Muzaffer Kal <muzaffer@dspia.com>
Date: Mon, 21 May 2001 17:35:54 GMT
Links: << >>  << T >>  << A >>
On Mon, 21 May 2001 16:22:45 +0300, Utku Ozcan <ozcan@netas.com.tr>
wrote:

>
>news:news.synplicity.com is not working by me, any one faced a similar problem?
>It is so for the last 3-4 days.
>
>Utku
>

I even filed a bug and they told me they were working on it.

Muzaffer

FPGA DSP Consulting
http://www.dspia.com

Article: 31384
Subject: Re: Finally, an FPGA tool chain for Linux (Also Synplicity)
From: Duane Clark <dclark@akamail.com>
Date: Mon, 21 May 2001 10:51:51 -0700
Links: << >>  << T >>  << A >>
Eric Smith wrote:
> 
> Altera has announced a port of Quartus II (including MAX+PLUS II)
> to Linux!
> ...
> Do any other programmable logic vendors support Linux?

Don't know, but here is good news from Synplicity:
http://www.synplicity.com/about/pressreleases/SYB-104final.html

It looks like Linux is really starting to get some respect.

Duane

Article: 31385
Subject: Re: free simulator
From: "Dave Feustel" <dfeustel@mindspring.com>
Date: Mon, 21 May 2001 13:16:42 -0500
Links: << >>  << T >>  << A >>
What is the URL for Aldec?

"Ray Andraka" <ray@andraka.com> wrote in message news:3B09098F.73C778D8@andraka.com...
> plus it comes with a fisrt class HDL editor, tutorials and probably the best
> on-line help in the industry.  If you are learning VHDL, Aldec would be THE tool
> to get.
>
> Tom Dillon wrote:
> >
> > It's not free but Aldec's Active HDL is much cheaper than Modeltech and
> > does an excellent job.
> >
> > Regards,
> >
> > Tom Dillon
> > Dillon Engineering, Inc.
> > http://www.dilloneng.com
> >
> > >>>>>>>>>>>>>>>>>> Original Message <<<<<<<<<<<<<<<<<<
> >
> > On 5/14/2001, 4:59:49 AM, "Meelis Kuris" <matiku@hot.ee> wrote regarding
> > free simulator:
> >
> > > Hi!
> >
> > > I've been using Modeltech XE which comes with WebPack
> > > and I'm getting really tired of this design size limitation and
> > > it's generally quite slow and the DCM phase shift problem I wrote about,
> > > etc.
> >
> > > So, what other free/shareware simulator can I use for simulation
> > > where I can also use Virtex2 specific things like DCM?
> >
> > > Can I use Veribest simulator coming with Actel Desktop
> > > software? Is it possible to use unisim library with it?
> > > How? Tried linking the same unisim library which was meant
> > > for Modelsim, no success.
> >
> > > Or any other suggestions?
> >
> > > Thanks,
> >
> > > Meelis
>
> --
> -Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930     Fax 401/884-7950
> email ray@andraka.com
> http://www.andraka.com



Article: 31386
Subject: Re: JTAG and Debugging
From: "C.Schlehaus" <carlhermann.schlehaus@t-online.de>
Date: Mon, 21 May 2001 20:34:22 +0200
Links: << >>  << T >>  << A >>
Hi,
<steve (Steve Rencontre)> schrieb im Newsbeitrag
news:memo.20010521172452.1296a@steve.rsn-tech.co.uk...

> (But don't bother unless you're running Windows NT - or maybe 2k, which I
> haven't tested. There is no support for any flavour of 9x.)
>

unfortunately the program terminates under W2K as soon as I
try to setup my Hardware with an abnormal Program termination.

Sorry, Carlhermann




Article: 31387
Subject: Re: Xilinx Service Pack 8 Now Available
From: Arthur Yang <arthur.yang@xilinx.com>
Date: Mon, 21 May 2001 12:01:40 -0700
Links: << >>  << T >>  << A >>

--------------6675719393CDB8B7A59554FA
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

Hello Kolja -

     I apolgize for the confusion - I meant that those designs will be
fit into Xilinx CPLDs in the next major release of software - not
meaning service packs.

    Send me your code and I can return a report and JED to you for this
issue.

Regards,
Arthur

Kolja Sulimma wrote:

> I was promised that sesigns with 0 inputs and 2 outputs fit into
> Xilinx CPLDs after installing this service pack.
> But this bugifx is not in the list.
>
> ;-(
>
> Kolja Sulimma
>
> Roy White wrote:
>
>> Hello Xilinx Software users,
>>
>> Service Pack 8 is now available for all Platforms.  To keep you
>> software up to date with the latest features I encourage you to
>> visit our service pack download center
>> at support.xilinx.com.
>>
>> Thank you for designing with Xilinx!
>>
>> Roy White
>>
>

--------------6675719393CDB8B7A59554FA
Content-Type: text/html; charset=us-ascii
Content-Transfer-Encoding: 7bit

<!doctype html public "-//w3c//dtd html 4.0 transitional//en">
<html>
Hello Kolja -
<p>&nbsp;&nbsp;&nbsp;&nbsp; I apolgize for the confusion - I meant that
those designs will be fit into Xilinx CPLDs in the next major release of
software - not meaning service packs.
<br>&nbsp;
<br>&nbsp;&nbsp;&nbsp; Send me your code and I can return a report and
JED to you for this issue.
<p>Regards,
<br>Arthur
<p>Kolja Sulimma wrote:
<blockquote TYPE=CITE>I was promised that sesigns with 0 inputs and 2 outputs
fit into Xilinx CPLDs after installing this service pack.
<br>But this bugifx is not in the list.
<p>;-(
<p>Kolja Sulimma
<p>Roy White wrote:
<blockquote TYPE=CITE>Hello Xilinx Software users,
<p>Service Pack 8 is now available for all Platforms.&nbsp; To keep you
software up to date with the latest features I encourage you to visit our
service pack download center
<br>at <a href="http://support.xilinx.com/support/techsup/sw_updates/">support.xilinx.com</a>.
<p>Thank you for designing with Xilinx!
<p>Roy White
<br>&nbsp;</blockquote>
</blockquote>
</html>

--------------6675719393CDB8B7A59554FA--


Article: 31388
Subject: Re: JTAG and Debugging
From: "C.Schlehaus" <carlhermann.schlehaus@t-online.de>
Date: Mon, 21 May 2001 22:36:46 +0200
Links: << >>  << T >>  << A >>
Hi,

"C.Schlehaus" <carlhermann.schlehaus@t-online.de> schrieb im Newsbeitrag
news:9ebn3n$n9d$00$1@news.t-online.com...

> unfortunately the program terminates under W2K as soon as I
> try to setup my Hardware with an abnormal Program termination.

I have to apologize, as I had the Byteblaster driver not
installed. I still have to test the scan function, but
at least the program terminates no longer :-)

Sorry (once more), Carlhermann



Article: 31389
Subject: LFSR Taps for 64 bit registers?
From: "Dave Feustel" <dfeustel@mindspring.com>
Date: Mon, 21 May 2001 17:27:31 -0500
Links: << >>  << T >>  << A >>
I'm looking for taps for 64-bit linear feedback shift registers.
Can someone post either values for such taps or a source
of information for generating the taps?

Thanks,

Dave Feustel
Fort Wayne, Indiana



Article: 31390
Subject: Re: FPGA consultant needed
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Tue, 22 May 2001 00:07:17 +0100
Links: << >>  << T >>  << A >>


Eric wrote:
> 
> Here is the text for this patent :
> 
> http://www.delphion.com/details?pn=US05260610__
> 
> Problem is, Altera own this "catch-all and innovation stifling" patent
> as you call it. What they search in here is someone who will be paid to
> pretend this is a real invention. Maybe that's the reason why Altera
> themselves could not find an "expert" to defend this patent and had
> to go fishing in here.
> 
> May I leave the word "grossly" from my previous post ?
> 
> Eric.
> 
> 

Sorry I got the wrong end of the stick here, had a brain-out, & thought
the expert would be fighting the patent - bad PAR day. Please re-instate
GROSSLY & consider normal lawyer mode resumed.

Article: 31391
Subject: Re: Synplicity newsgroup?
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Tue, 22 May 2001 00:12:27 +0100
Links: << >>  << T >>  << A >>


Muzaffer Kal wrote:
> 
> On Mon, 21 May 2001 16:22:45 +0300, Utku Ozcan <ozcan@netas.com.tr>
> wrote:
> 
> >
> >news:news.synplicity.com is not working by me, any one faced a similar problem?
> >It is so for the last 3-4 days.
> >
> >Utku
> >
> 
> I even filed a bug and they told me they were working on it.
> 
> Muzaffer
> 
> FPGA DSP Consulting
> http://www.dspia.com

I started having a similar problem last week logging on to SOS & also
filed a bug. After what appears to have been quite a struggle its now
working again *and* I can get to the newsgroup for the first time ever.

Article: 31392
Subject: Re: Maximum clock frequency to expect in Xilinx Virtex FPGA ?
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Tue, 22 May 2001 00:19:32 +0100
Links: << >>  << T >>  << A >>


Jimmie wrote:
> 
> Hi all!
> I am new to FPGA design, but have been doing ASIC design for some time.
> 
> Now we are working on a design that is to be implemented in a Virtex Xilinx FPGA.
> Nothing fancy, some counters, crc-calculation a couple of mid-sized state
> machines etc.
> 
> Without doing to much architecture specific stuff (wants to be able to port
> parts of the design to an ASIC later on), could anyone give a ball-park figure
> of what clock frequency to expect ?
> 
> I have got some simple designs (state machines) through the synthesis tool (using
> verilog and FPGA express), and get figures like 40-50 MHz, does this sound like reasonable
> figures to expect?
> 

You should be able to get much better than that after place & route. One
thing you might not be used to, coming from an ASIC background, is that
FPGA synth tools are much poorer at predicting the final PPR STA speed
than ASIC ones.

As a data point I have an 85% used XCV400E design that's signing off
@80MHz without any floorplanning or hard macros, just using the
automatic P&R tools.

> I would like to reach 100 MHz, but that might demand too much tuning and
> architecture specific design.
> 
> Also, any opinions about using fpga express with Virtex, good, bad !?
> 

I would strongly recommend you at least run an eval of Synplify.

Article: 31393
Subject: Re: LFSR Taps for 64 bit registers?
From: Mark Curry <mcurry@ti.com>
Date: Mon, 21 May 2001 16:26:34 -0700
Links: << >>  << T >>  << A >>
Dave,

Xilinx has an excellent app note:

http://www.xilinx.com/xapp/xapp052.pdf

Regards,

Mark


Dave Feustel wrote:
> 
> I'm looking for taps for 64-bit linear feedback shift registers.
> Can someone post either values for such taps or a source
> of information for generating the taps?
> 
> Thanks,
> 
> Dave Feustel
> Fort Wayne, Indiana

Article: 31394
Subject: Re: free simulator
From: Ray Andraka <ray@andraka.com>
Date: Mon, 21 May 2001 23:34:33 GMT
Links: << >>  << T >>  << A >>
http://www.aldec.com

Dave Feustel wrote:
> 
> What is the URL for Aldec?
> 
> "Ray Andraka" <ray@andraka.com> wrote in message news:3B09098F.73C778D8@andraka.com...
> > plus it comes with a fisrt class HDL editor, tutorials and probably the best
> > on-line help in the industry.  If you are learning VHDL, Aldec would be THE tool
> > to get.
> >
> > Tom Dillon wrote:
> > >
> > > It's not free but Aldec's Active HDL is much cheaper than Modeltech and
> > > does an excellent job.
> > >
> > > Regards,
> > >
> > > Tom Dillon
> > > Dillon Engineering, Inc.
> > > http://www.dilloneng.com
> > >
> > > >>>>>>>>>>>>>>>>>> Original Message <<<<<<<<<<<<<<<<<<
> > >
> > > On 5/14/2001, 4:59:49 AM, "Meelis Kuris" <matiku@hot.ee> wrote regarding
> > > free simulator:
> > >
> > > > Hi!
> > >
> > > > I've been using Modeltech XE which comes with WebPack
> > > > and I'm getting really tired of this design size limitation and
> > > > it's generally quite slow and the DCM phase shift problem I wrote about,
> > > > etc.
> > >
> > > > So, what other free/shareware simulator can I use for simulation
> > > > where I can also use Virtex2 specific things like DCM?
> > >
> > > > Can I use Veribest simulator coming with Actel Desktop
> > > > software? Is it possible to use unisim library with it?
> > > > How? Tried linking the same unisim library which was meant
> > > > for Modelsim, no success.
> > >
> > > > Or any other suggestions?
> > >
> > > > Thanks,
> > >
> > > > Meelis
> >
> > --
> > -Ray Andraka, P.E.
> > President, the Andraka Consulting Group, Inc.
> > 401/884-7930     Fax 401/884-7950
> > email ray@andraka.com
> > http://www.andraka.com

-- 
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com

Article: 31395
Subject: Re: LFSR Taps for 64 bit registers?
From: Peter Alfke <palfke@earthlink.net>
Date: Tue, 22 May 2001 04:59:52 GMT
Links: << >>  << T >>  << A >>
I checked several sources, and they agree:
Take a 64-bit shift register.
Number the bits 1 through 64 ( that's the habit of the folks in
LFSR and Crypto-land)
Generate the XNOR of outputs Q60, Q61, Q63, and Q64.
XNOR means "even parity", ( the output of the XNOR is a 1 if 0, 2
or 4 of the inputs are 1.  Maybe that's a dumb use of the word
"exclusive", but that's the way it is.)
You could also have picked XOR = odd parity, but that would have
made the all-zero state persistent ( and thus illegal). Most
circuitry has a reset input, perhaps even a power-on reset, that
makes it more meaningful to make all-zeros legal as the starting
code, and make the all-ones illegal. The normal sequence never gets
you into the illegal state, but if you ever get there, you are
stuck. And a detector costs you some gating and might sacrifice
speed.

Of course, you can put the first 60 bits into a RAM, and the SRL16
in Virtex is especially nice and cheap, since you can stuff up to
16 shift-register bits into a 4-input Look-Up-Table (LUT).

Good luck, and tell us when you reach max count.
It will take more than 5,000 years @ 100 MHz, so don't hold your
breath.  :-)

Peter Alfke, Xilinx Applications
==============================================================
Dave Feustel wrote:

> I'm looking for taps for 64-bit linear feedback shift registers.
> Can someone post either values for such taps or a source
> of information for generating the taps?
>
> Thanks,
>
> Dave Feustel
> Fort Wayne, Indiana


Article: 31396
Subject: Re: Synplicity newsgroup?
From: Utku Ozcan <ozcan@netas.com.tr>
Date: Tue, 22 May 2001 08:28:49 +0300
Links: << >>  << T >>  << A >>

It works! It works! Thanks for the effort!

Utku



Article: 31397
Subject: fast divider
From: "Pjc" <pjc@tomail.com.tw>
Date: Tue, 22 May 2001 14:12:43 +0800
Links: << >>  << T >>  << A >>
please tell  me how to design a fast (unsigned)32bit divider
thanks




Article: 31398
Subject: xilinx webpack problem
From: Gonzalo Arana <gonzaloa@sinectis.com.ar>
Date: Tue, 22 May 2001 03:24:53 -0300
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.
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Hi there,

  I'm a beginner in the FPGA world (also in the VHDL world).
  My first 'project' is just a counter written in vhdl.
  I wrote it as an entity.
  When I 'use' it from another entity (which would represent the FPGA
itself), and try to get the bitstream, I get the following error
message:

ERROR:Route:10 - There are no connections to route.  If this is
incorrect,
   please check the mapper report file (.mrp) to verify why any specific
net or
   component may have been trimmed out of the design. 

   But I can successfully get the bit-stream for the counter entity
(useless).

   My questions are:
1) How do I represent the chip itself in VHDL? (as an entity?)
2) If this is the case, what am I doing wrong?  Here is a fragment of
counter.mrp:

Section 2 - Warnings
--------------------
WARNING:MapLib:62 - All of the external outputs in this design are using
slew
   rate limited output drivers. The delay on speed critical outputs can
be
   dramatically reduced by designating them as fast outputs in the
schematic.
WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net N87 is
sourced by a
   combinatorial pin. This is not good design practice. Use the CE pin
to
   control the loading of data into the flip-flop.

Section 3 - Design Attributes
-----------------------------

Section 4 - Removed Logic Summary
---------------------------------

Section 5 - Removed Logic
-------------------------

Section 6 - Added Logic
-----------------------

Section 7 - Expanded Logic
--------------------------
To enable this section, set the detailed map report option and rerun
map.

......

   Just in case, I do include both source codes.
   Any help would be appreciated,

Gonzalo
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 filename="counter.vhd"

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity counter is
    Port ( incnt : in std_logic_vector(0 to 3);
           incntenable : in std_logic;
           clock : in std_logic;
           borrowout : out std_logic;
           borrowin : in std_logic;
           countenable : in std_logic);
end counter;

architecture behavioral of counter is

  signal cnt : std_logic_vector (0 to 3) := "0000";      -- cuenta actual
  signal nextcnt : std_logic_vector (0 to 3) := "0000";  -- proximo valor de la cuenta

begin

  -- purpose: Calcula el nuevo valor de la cuenta
  -- inputs : cnt
  -- outputs: borrow
  getNextState: process (cnt)
  begin  -- process getNextState
    case cnt is
      when "0000" => nextcnt <= "1111"; borrowout <= '1';
      when "0001" => nextcnt <= "0000";
      when "0010" => nextcnt <= "0001";
      when "0011" => nextcnt <= "0010";
      when "0100" => nextcnt <= "0011";
      when "0101" => nextcnt <= "0100";
      when "0110" => nextcnt <= "0101";
      when "0111" => nextcnt <= "0110";
      when "1000" => nextcnt <= "0111";
      when "1001" => nextcnt <= "1000";
      when "1010" => nextcnt <= "1001";
      when "1011" => nextcnt <= "1010";
      when "1100" => nextcnt <= "1011";
      when "1101" => nextcnt <= "1100";
      when "1110" => nextcnt <= "1101";
      when "1111" => nextcnt <= "1110"; borrowout <= '0';
      when others => null;
    end case;
  end process getNextState;

  -- purpose: Realiza el cambio de estado
  -- type   : combinational
  -- inputs : clock
  -- outputs: cnt
  shiftState: process (clock, incntenable, borrowin, nextcnt)
  begin  -- process shiftState
    -- ESTA ANDA (380 MHz)
--     if clock = '1' and clock'event then
--       cnt <= incnt;
--     end if;

    -- ESTA ANDA (180 MHz)
    if clock'event and clock = '1' then
      if incntenable = '1' then 
        cnt <= incnt;
      elsif borrowin = '1' and countenable = '1' then
        cnt <= nextcnt;
      end if;
    end if;
    
    -- ESTA NO ANDA
--     if clock = '1' and clock'event and incntenable = '1' then
--       cnt <= incnt;
--     elsif clock = '1' and clock'event and borrowin = '1' and countenable = '1' then
--       cnt <= nextcnt;
--     end if;
  end process shiftState;

end behavioral;

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity test1 is
    Port ( led : out std_logic;
			  clock: in std_logic);
end test1;

architecture behavioral of test1 is
	component counter port (
		 incnt : in std_logic_vector(0 to 3);
       incntenable : in std_logic;
       clock : in std_logic;
       borrowout : out std_logic;
       borrowin : in std_logic;
       countenable : in std_logic);
	end component counter;
	signal cero : std_logic;
	signal uno : std_logic;
	signal cuatro_ceros : std_logic_vector (0 to 3);
	signal borrows : std_logic_vector (0 to 5);
	signal clock1 : std_logic;

begin
	cero <= '0';
	uno <= '1';
	cuatro_ceros <= "0000";
	borrows <= "000000";
	clock1 <= clock;
	contador0: counter port map (cuatro_ceros, cero, clock, borrows(0), uno, uno);
	contador1: counter port map (cuatro_ceros, cero, clock, borrows(1), borrows(0), uno);
	contador2: counter port map (cuatro_ceros, cero, clock, borrows(2), borrows(1), uno);
	contador3: counter port map (cuatro_ceros, cero, clock, borrows(3), borrows(2), uno);
	contador4: counter port map (cuatro_ceros, cero, clock, borrows(4), borrows(3), uno);
	contador5: counter port map (cuatro_ceros, cero, clock, led, borrows(4), uno);

-- POR QUE ESTO NO ANDA??????????????????
--	contador: for i in 0 to 5 generate
--		cntr0: if (i = 0) generate
--		    counter_rightest: counter port map (cuatro_ceros, cero, clock, borrows(i), uno, uno);
--		cntr1to4: if (i > 0 and i < 5) generate
--		    counter_middle:   counter port map (cuatro_ceros, cero, clock, borrows(i), borrows(i-1), uno);
--		cntr5: if (i = 5) generate
--		    counter_leftest:  counter port map (cuatro_ceros, cero, clock, led, borrows(i-1), uno);
--		end generate;
--	end generate;
end behavioral;


--------------4D20E38EC412CC4B700347AA--


Article: 31399
Subject: Xilinx PCI JTAG programming
From: Steven Sanders <steven.sanders@imec.be>
Date: Tue, 22 May 2001 11:29:58 +0200
Links: << >>  << T >>  << A >>
Hello,

Currently we`re designing a cPCI board with a VirtexII on it and we 
want to program it via JTAG via the cPCI backplane. We run Linux on 
the embedded PC. The main question is: can you program an 
unconfigured fpga (so no pci core present in the Virtex 
at boot !) via JTAG without detecting the card under Linux?
Or does the pci core has to be ALREADY present (and thus detectable) 
to use the PCI JTAG interface to program it? 

Anyone any experience with this?

Thanx very much!!!

Steven 
www.imec.be



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