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Messages from 31400

Article: 31400
Subject: Re: xilinx webpack problem
From: Kent Orthner <korthner@hotmail.nospam.com>
Date: 22 May 2001 19:14:01 +0900
Links: << >>  << T >>  << A >>
Gonzalo Arana <gonzaloa@sinectis.com.ar> writes:
> Hi there,
> 
>   I'm a beginner in the FPGA world (also in the VHDL world).
>   My first 'project' is just a counter written in vhdl.
>   I wrote it as an entity.

I'll try to help you out a bit.  Please see my comments below.
I hope they help.

-Kent

----------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--** STD_LOGIC_ARITH and STD_LOGIC_UNSIGNED over lap a bit,
--** I would suggest not using either of them, and using 
--** NUMERIC_STD instead.  (Although I'm sure that there 
--** are others here that would disagree)

entity counter is
    Port ( incnt : in std_logic_vector(0 to 3);
           incntenable : in std_logic;
           clock : in std_logic;
           borrowout : out std_logic;
           borrowin : in std_logic;
           countenable : in std_logic);
end counter;

architecture behavioral of counter is

--  signal cnt : std_logic_vector (0 to 3) := "0000";      -- cuenta actual
--  signal nextcnt : std_logic_vector (0 to 3) := "0000";  -- proximo valor de la cuenta

--** It is convention to number your vectors high-to-low, 
--** like you would normally count bits.
--** Also, assigning initial values is not supported for 
--**synthesis.

  signal cnt : std_logic_vector (3 downto 0); --  (:= "0000"; <-- not supported)
  signal nextcnt : std_logic_vector (3 downto 0); --  (:= "0000"; <-- not supported)


begin
 
   -- purpose: Calcula el nuevo valor de la cuenta
   -- inputs : cnt
   -- outputs: borrow
   getNextState: process (cnt)
   begin  -- process getNextState
     case cnt is
       when "0000" => nextcnt <= "1111"; borrowout <= '1';
       when "0001" => nextcnt <= "0000";
       when "0010" => nextcnt <= "0001";
       when "0011" => nextcnt <= "0010";
       when "0100" => nextcnt <= "0011";
       when "0101" => nextcnt <= "0100";
       when "0110" => nextcnt <= "0101";
       when "0111" => nextcnt <= "0110";
       when "1000" => nextcnt <= "0111";
       when "1001" => nextcnt <= "1000";
       when "1010" => nextcnt <= "1001";
       when "1011" => nextcnt <= "1010";
       when "1100" => nextcnt <= "1011";
       when "1101" => nextcnt <= "1100";
       when "1110" => nextcnt <= "1101";
--       when "1111" => nextcnt <= "1110"; borrowout <= '0';

--** Use "1111" as your others case.  (I doubt know if this 
--** makes a difference, but it's better to be sure.)

       when others => nextcnt <= "1110"; borrowout <= '0';
     end case;
   end process getNextState;
 
   -- purpose: Realiza el cambio de estado
   -- type   : combinational

--** This is not a combinational process.  You want the outputs 
--** to change on the rising edge of Clock, so this is sequential 
--**type.

   -- inputs : clock
   -- outputs: cnt
--**   shiftState: process (clock, incntenable, borrowin, nextcnt)

--** The sensitivity list should only include signals that cause the
--** outputs of yout process to change.  In your case, only clock.

   shiftState: process (clock)
   begin  -- process shiftState

     -- ESTA ANDA (180 MHz)
     if clock'event and clock = '1' then
       if incntenable = '1' then 
         cnt <= incnt;
       elsif borrowin = '1' and countenable = '1' then
         cnt <= nextcnt;
       end if;
     end if;
     
  end process shiftState;
 
 end behavioral;


 library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
 use IEEE.STD_LOGIC_ARITH.ALL;
 use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
 entity test1 is
     Port ( led : out std_logic;
 			  clock: in std_logic);
 end test1;
 
 architecture behavioral of test1 is

 	component counter port (
 		 incnt : in std_logic_vector(0 to 3);
                incntenable : in std_logic;
                clock : in std_logic;
                borrowout : out std_logic;
                borrowin : in std_logic;
                countenable : in std_logic);
 	end component counter;

 	signal cero : std_logic;
 	signal uno : std_logic;
 	signal cuatro_ceros : std_logic_vector (0 to 3);
 	signal borrows : std_logic_vector (0 to 5);
 	signal clock1 : std_logic;

 begin
 	cero <= '0';
 	uno <= '1';
 	cuatro_ceros <= "0000";

--** This *ALWAYS* drives zeros to your borrows signal:
 	borrows <= "000000";


--** You don't need clock1:
 	clock1 <= clock;

--** These counters are trying to drive the borrows(4 downto 0) signal.  
--** But a few lines above, you're driving '0's all the time.  To prevent 
--** damage to the chip, the synthesis tool or Place-n-Route tool will
--** remove something.

 	contador0: counter port map (cuatro_ceros, cero, clock, borrows(0), uno, uno);
 	contador1: counter port map (cuatro_ceros, cero, clock, borrows(1), borrows(0), uno);
 	contador2: counter port map (cuatro_ceros, cero, clock, borrows(2), borrows(1), uno);
 	contador3: counter port map (cuatro_ceros, cero, clock, borrows(3), borrows(2), uno);
 	contador4: counter port map (cuatro_ceros, cero, clock, borrows(4), borrows(3), uno);
 	contador5: counter port map (cuatro_ceros, cero, clock, led, borrows(4), uno);


 
 -- POR QUE ESTO NO ANDA??????????????????
 --	contador: for i in 0 to 5 generate
 --		cntr0: if (i = 0) generate
 --		    counter_rightest: counter port map (cuatro_ceros, cero, clock, borrows(i), uno, uno);
 --		cntr1to4: if (i > 0 and i < 5) generate
 --		    counter_middle:   counter port map (cuatro_ceros, cero, clock, borrows(i), borrows(i-1), uno);
 --		cntr5: if (i = 5) generate
 --		    counter_leftest:  counter port map (cuatro_ceros, cero, clock, led, borrows(i-1), uno);
 --		end generate;
 --	end generate;
 end behavioral;

Article: 31401
Subject: inout signals between Viewdraw schematics and VHDL components
From: Marc-Eric Uldry <muldry@studi.epfl.ch>
Date: Tue, 22 May 2001 12:44:14 +0200
Links: << >>  << T >>  << A >>

I have a Viewdraw schematic and I need to insert a component written in
VHDL. So far I'm using Leonardo to create an EDIF file and, in Viewdraw, I
set the FILE property to the name of the edn file. I'm not aware of any
other way to do it.

My problem is that the VHDL exports some pins as inout and I need to
connect them to an iopad in Viewdraw. I've tried with and without the "Add
I/O Pads" property set, but both lead to errors in the Xilinx device
manager. From my little experience with input or output signals it looks
like I need to unset "Add I/O pads" in Leonardo and add manually IBUFT or
OBUFT in Viedraw between the component and the IOPAD. Unfortunately I
cannot do the same with the inout port since only one net is going out the
"VHDL module". Here is the error message I get connecting it directly to
the IOPAD:

WARNING:NgdBuild:465 - bidirect pad net 'P132' has no legal load
ERROR:NgdBuild:466 - bidirect pad net 'P132' has illegal connection

For information, connecting the VHDL compiled with the "I/O Pads" set in
Leonardo directly on the IOPAD lead to:

ERROR:NgdBuild:461 - logical net 'P132' has multiple pad connections

Does anyone know how to get rid of that problem or do differently?

Thanks in advance.


Marc-Eric


Article: 31402
Subject: Re: RLocs on Inferred registers??
From: hamish@cloud.net.au
Date: Tue, 22 May 2001 12:24:38 GMT
Links: << >>  << T >>  << A >>
n# <n@n.com> wrote:
> Anyone know a tool that will do this? I have written scripts, used cores
> etc. but I still wish I could do this.

What's the problem? You can put these RLOCs in your UCF, on INSTances
which are named according to the inferred registers in your design.

You might even be able to use an attribute like xc_rloc on the
signals which the registers output to. Your synthesis tool should
pass these along in the EDF file.

Hamish
-- 
Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>

Article: 31403
Subject: Counter problem
From: Martin <martin.t@yours.com>
Date: Tue, 22 May 2001 07:19:49 -0700
Links: << >>  << T >>  << A >>
Hi,

Does anybody know what can be wrong with that code ?

--- Code starts here ---

entity DownCounter is
generic( PresetValue: integer := 1023 );
port(	Reset:	in std_logic;		Clk:	in std_logic;		Zero:	out std_logic		);
end DownCounter;

architecture Behaviour of DownCounter is
begin
Controller: process( Reset, Clk )
	variable state: integer range 0 to PresetValue;
begin
	if( Reset = '1' ) then
		state := PresetValue;
	elsif( Clk'event and Clk = '0' ) then
		if( state = 0 ) then
		state := PresetValue;
	else
		state := state - 1;
	end if;
	end if;
		
	if( state = 0 ) then
		Zero <= '1';
	else
		Zero <= '0';
	end if;
end process Controller;
end Behaviour;

--- End of code  ----

I use the Synplify 6.1.3 to synthesis and simulation after that operation is OK. The problem is in simulation after the Place&Route for Xilinx Spartan2 150k + Service Pack 7, which gives all 'X' signals. What can be wrong ?

Regards,
Martin

Article: 31404
Subject: Re: Xilinx PCI JTAG programming
From: Muzaffer Kal <muzaffer@dspia.com>
Date: Tue, 22 May 2001 14:44:36 GMT
Links: << >>  << T >>  << A >>
On Tue, 22 May 2001 11:29:58 +0200, Steven Sanders
<steven.sanders@imec.be> wrote:

>Hello,
>
>Currently we`re designing a cPCI board with a VirtexII on it and we 
>want to program it via JTAG via the cPCI backplane. We run Linux on 
>the embedded PC. The main question is: can you program an 
>unconfigured fpga (so no pci core present in the Virtex 
>at boot !) via JTAG without detecting the card under Linux?
>Or does the pci core has to be ALREADY present (and thus detectable) 
>to use the PCI JTAG interface to program it? 

If PCI JTAG is under the control of the OS, you don't need the PCI
core but make sure that FPGA programming happens before PCI detection
& resource assignment. Or you have will have to find a way to tell the
OS a new device has become available as if it was hot plugged.

Muzaffer

FPGA DSP Consulting
http://www.dspia.com

Article: 31405
Subject: FPGA
From: "julia" <julia_802002@yahoo.it>
Date: Tue, 22 May 2001 16:00:22 +0100
Links: << >>  << T >>  << A >>

plz poit me to a tutorial in the net about the basics of FPGA and design.

  Julia



Article: 31406
Subject: Re: JTAG and Debugging
From: steve (Steve Rencontre)
Date: Tue, 22 May 2001 16:50 +0100 (BST)
Links: << >>  << T >>  << A >>
In article <9ebu96$2gp$01$1@news.t-online.com>, 
carlhermann.schlehaus@t-online.de (C.Schlehaus) wrote:

> Hi,
> 
> "C.Schlehaus" <carlhermann.schlehaus@t-online.de> schrieb im Newsbeitrag
> news:9ebn3n$n9d$00$1@news.t-online.com...
> 
> > unfortunately the program terminates under W2K as soon as I
> > try to setup my Hardware with an abnormal Program termination.
> 
> I have to apologize, as I had the Byteblaster driver not
> installed. I still have to test the scan function, but
> at least the program terminates no longer :-)
> 
> Sorry (once more), Carlhermann

Hmm, it shouldn't be affected by the ByteBlaster driver, since it doesn't 
use it. OTOH, I may need to recompile my driver for Win2k - some NT kernel 
drivers will work unchanged with 2k, some won't. Although I'm running 2k 
on my main machine, the one I use for hardware debugging still runs NT4, 
so I haven't needed to address the issue.

One other point - because PJ does use a kernel driver, you need to be 
logged on as an administrator to install it. I can't remember if the 
free-with-the-compiler version of InstallShield I use is clever enough to 
give a sensible message if you don't, or whether the install just fails 
silently.

Drop me an email if you continue to have driver-related problems and I'll 
try a 2k rebuild.

--
Steve Rencontre		http://www.rsn-tech.co.uk
//#include <disclaimer.h>


Article: 31407
Subject: VIRTEX and dynamic reconfiguration
From: Robert Siegmund <rsie@infotech.tu-chemnitz.de>
Date: Tue, 22 May 2001 18:12:17 +0200
Links: << >>  << T >>  << A >>
Hi,

does anybody have experience with dynamic (run time) reconfiguration of

VIRTEX /VIRTEX II FPGA? We are about to do some experiments with

that, however, although the contents of CLB LUT can easily be modified during

run time, the problem remains that in order to exchange complete

modules, also the routing needs to be (partially) modified.

Is there a way to at least restrict PAR from routing through a reserved

block of CLB's which can then serve as a place keeper for a run-time

reconfigurable module?

Or does anybody know about the status of the JBits tool from XILINX?

regards, Robert

--
------------------------------------------------------------------------------
Dipl.-Ing. Robert Siegmund                 email: rsie@infotech.tu-chemnitz.de
Chemnitz University of Technology
Dpt. of Systems and Circuit Design        www: http://www.tu-chemnitz.de/~rsie
Chemnitz,Germany
------------------------------------------------------------------------------




Article: 31408
Subject: Re: Counter problem
From: "Meelis Kuris" <matiku@hot.ee>
Date: Tue, 22 May 2001 19:57:11 +0300
Links: << >>  << T >>  << A >>
When I try to imagine what will be synthesized as a result of such
code, I think there will be no place to store the value of state.
I think you have to have a signal(meaning a register) which basically
stores the value of state until next clock cycle.

Maybe this way:
-----------------------

 entity DownCounter is
 generic( PresetValue: integer := 1023 );
 port( Reset: in std_logic; Clk: in std_logic; Zero: out std_logic );
 end DownCounter;

 architecture Behaviour of DownCounter is
 begin
 signal state : integer range 0 to PresetValue;

 Controller: process( Reset, Clk )
 begin
 if( Reset = '1' ) then
 state <= PresetValue;
 elsif( Clk'event and Clk = '0' ) then
 if( state = 0 ) then
 state <= PresetValue;
 else
 state <= state - 1;
 end if;
 end if;

end process Controller;

Zero<= '1' when (state=0) else '0';
end Behaviour;
-----------------------

Cheers,

Meelis

"Martin" <martin.t@yours.com> wrote in message
news:ee70aed.-1@WebX.sUN8CHnE...
> Hi,
>
> Does anybody know what can be wrong with that code ?
>
> --- Code starts here ---
>
> entity DownCounter is
> generic( PresetValue: integer := 1023 );
> port( Reset: in std_logic; Clk: in std_logic; Zero: out std_logic );
> end DownCounter;
>
> architecture Behaviour of DownCounter is
> begin
> Controller: process( Reset, Clk )
> variable state: integer range 0 to PresetValue;
> begin
> if( Reset = '1' ) then
> state := PresetValue;
> elsif( Clk'event and Clk = '0' ) then
> if( state = 0 ) then
> state := PresetValue;
> else
> state := state - 1;
> end if;
> end if;
>
> if( state = 0 ) then
> Zero <= '1';
> else
> Zero <= '0';
> end if;
> end process Controller;
> end Behaviour;
>
> --- End of code  ----
>
> I use the Synplify 6.1.3 to synthesis and simulation after that operation
is OK. The problem is in simulation after the Place&Route for Xilinx
Spartan2 150k + Service Pack 7, which gives all 'X' signals. What can be
wrong ?
>
> Regards,
> Martin



Article: 31409
Subject: Re: RLocs on Inferred registers??
From: "n#" <n@n.com>
Date: Tue, 22 May 2001 18:47:33 +0100
Links: << >>  << T >>  << A >>
Thanks for the reply,

The problem is that it is much easier (obviously) to infer a register, but a
lot of hard work to add all the RLOCs, either in UCF or by instatiation -
fine for a small design, but it is never the small designs that are the
problem (only small chips!). What I have found tends to happen with the
Xilinx P&R tools, is that bussed registers get bunched up (when not RLoced
or on the output of an adder etc), so, for example, if trying to add a level
of pipeling to an already registered adder output which feeds input of
another adder, we end up with a jiggered placement; instead of getting a
nice adder 'stick' followed by a register 'stick' and then the other adder
'stick', the two adder sticks remain, but the middle register gets bunched
up, (strangely, usually above and to the left) - not sure I have explained
this as clearly as I could...!. Also, adding RLocs to large designs
considerably reduces P&R time in my experience . The bunching situation is
particularly bad when using SRL16 primitive, which I have had to completely
rloc down to get sensible PAR times and scores/repeatbility. I guess I could
make a library of instatiated registers of different widths with the RLOCs
in (would require two sets, one in S0 and one in S1), but all this
instatiation make the code less readable.

The UCF solution is also not good IMHO as I believe that it would need to be
modified after synthisys each time (the names have been changed to persicute
the innocent?)

I guess I am asking for synthis with some ammount of placement, or an
'inteligent' P&R that doesn't start from a random seed, but rather takes a
look at the data flow - I know, I know, take a number and get in line. I
gather that Synplify may be experimenting with placed synthisys, and Xilinx
with their XST stuff, but I wondered if there was somthing I missed. (If  I
could instiate in a for loop for instance)

I feel a parser coming on....

Cheers,

N.
<hamish@cloud.net.au> wrote in message
news:aUsO6.3160$25.11196@news1.eburwd1.vic.optushome.com.au...
> n# <n@n.com> wrote:
> > Anyone know a tool that will do this? I have written scripts, used cores
> > etc. but I still wish I could do this.
>
> What's the problem? You can put these RLOCs in your UCF, on INSTances
> which are named according to the inferred registers in your design.
>
> You might even be able to use an attribute like xc_rloc on the
> signals which the registers output to. Your synthesis tool should
> pass these along in the EDF file.
>
> Hamish
> --
> Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>



Article: 31410
Subject: Re: LFSR Taps for 64 bit registers?
From: Tim Jaynes <tim.jaynes@xilinx.com>
Date: Tue, 22 May 2001 10:55:07 -0700
Links: << >>  << T >>  << A >>
Hi Dave,
Peter Alfke's done this in a Xilinx application note:
http://support.xilinx.com/xapp/xapp210.pdf
On page 4-5 it lists the taps for maximum-length LFSR counters up to 168
bits.
Regards,
Tim Jaynes
CAE


Dave Feustel wrote:

> I'm looking for taps for 64-bit linear feedback shift registers.
> Can someone post either values for such taps or a source
> of information for generating the taps?
>
> Thanks,
>
> Dave Feustel
> Fort Wayne, Indiana


Article: 31411
Subject: Re: Counter problem
From: John_H <johnhandwork@mail.com>
Date: Tue, 22 May 2001 11:06:18 -0700
Links: << >>  << T >>  << A >>
The biggest simulation problems are usually the test bench.  Do you get the Preset value when you reset?

You may need to just "drill down" into your simulation, looking at signals deeper and deeper into your macro until you find out why the unknowns are generated.

The fact that pre-P&R simulation came out okay suggests the code is adequate.

Article: 31412
Subject: Re: fast divider
From: gah@ugcs.caltech.edu (glen herrmannsfeldt)
Date: 22 May 2001 18:13:27 GMT
Links: << >>  << T >>  << A >>
"Pjc" <pjc@tomail.com.tw> writes:

>please tell  me how to design a fast (unsigned)32bit divider
>thanks

How fast, and how much hardware can you supply to it?

There is always a tradeoff.  

Are both dividend and divisor 32 bits?
(Traditionally, the dividend is twice as long as the divisor.)

-- glen




Article: 31413
Subject: Re: Counter problem
From: Ray Andraka <ray@andraka.com>
Date: Tue, 22 May 2001 19:56:40 GMT
Links: << >>  << T >>  << A >>
The last part of the code within the process, beginning with:

if( state = 0 ) then
  Zero <= '1';

should either be inside the clock if-then cosntruct to make it registered, or
taken out of the process as a concurrent statement.  The way it is right now,
that gets updated as a result of an event on clock or reset but not as part of
the clocked logic.  It will most likely come thorugh synthesis with an
incomplete sensitivity list warning or worse.  It may or maynot give you the
right results in simulation, and will probably not match between pre and pst
synthesis. 

Meelis Kuris wrote:
> 
> When I try to imagine what will be synthesized as a result of such
> code, I think there will be no place to store the value of state.
> I think you have to have a signal(meaning a register) which basically
> stores the value of state until next clock cycle.
> 
> Maybe this way:
> -----------------------
> 
>  entity DownCounter is
>  generic( PresetValue: integer := 1023 );
>  port( Reset: in std_logic; Clk: in std_logic; Zero: out std_logic );
>  end DownCounter;
> 
>  architecture Behaviour of DownCounter is
>  begin
>  signal state : integer range 0 to PresetValue;
> 
>  Controller: process( Reset, Clk )
>  begin
>  if( Reset = '1' ) then
>  state <= PresetValue;
>  elsif( Clk'event and Clk = '0' ) then
>  if( state = 0 ) then
>  state <= PresetValue;
>  else
>  state <= state - 1;
>  end if;
>  end if;
> 
> end process Controller;
> 
> Zero<= '1' when (state=0) else '0';
> end Behaviour;
> -----------------------
> 
> Cheers,
> 
> Meelis
> 
> "Martin" <martin.t@yours.com> wrote in message
> news:ee70aed.-1@WebX.sUN8CHnE...
> > Hi,
> >
> > Does anybody know what can be wrong with that code ?
> >
> > --- Code starts here ---
> >
> > entity DownCounter is
> > generic( PresetValue: integer := 1023 );
> > port( Reset: in std_logic; Clk: in std_logic; Zero: out std_logic );
> > end DownCounter;
> >
> > architecture Behaviour of DownCounter is
> > begin
> > Controller: process( Reset, Clk )
> > variable state: integer range 0 to PresetValue;
> > begin
> > if( Reset = '1' ) then
> > state := PresetValue;
> > elsif( Clk'event and Clk = '0' ) then
> > if( state = 0 ) then
> > state := PresetValue;
> > else
> > state := state - 1;
> > end if;
> > end if;
> >
> > if( state = 0 ) then
> > Zero <= '1';
> > else
> > Zero <= '0';
> > end if;
> > end process Controller;
> > end Behaviour;
> >
> > --- End of code  ----
> >
> > I use the Synplify 6.1.3 to synthesis and simulation after that operation
> is OK. The problem is in simulation after the Place&Route for Xilinx
> Spartan2 150k + Service Pack 7, which gives all 'X' signals. What can be
> wrong ?
> >
> > Regards,
> > Martin

-- 
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com

Article: 31414
Subject: Re: Counter problem
From: Martin <martin.t@yours.com>
Date: Tue, 22 May 2001 14:43:12 -0700
Links: << >>  << T >>  << A >>
Hi,

Yes, after reset all signals have the proper values in post-P&R simulation. The problem begins when the reset goes unactive and the counter starts to count.

The Xilinx map report says it merged some signals. Maybe that caused that problem ?

Regards, Martin

Article: 31415
Subject: Re: FPGA
From: Tom <tomcip@concentric.net>
Date: 22 May 2001 23:08:12 GMT
Links: << >>  << T >>  << A >>
Julia,

This may disappoint you but there is no one-size-fits-all tutorial concerning
the theory behind FPGA design that I am aware of, and I have been working
with FPGAs since they were invented. Al lot of good information can be had by
searching the archives of this newsgroup. I used to use deja.com but I don't
know if it became a dot-bomb.

If this is a student inquiry then the best way to get started is to visit the
web site of a company that manufactures FPGAs and CPLDs. I would recommend
the Xilinx site or the Altera site or possibly even the Lattice site.

Then do the following:

1) Download free development software if it exists. I know that the "Webpack"
software from Xilinx is free. It is, of course, a restricted set of tools but
it is plenty for a beginner. I don't know if Altera has a free tool suite.
Several years ago I used the "Lattice"  tool suite, which was free back then.

2) There are something like 16 different manuals on the Xilinx site so
download the "quick Start" guide or the other basic manuals. I would not get
bogged down with the advanced manuals until you get some experience.

3) Download the device catalog, which is full of data sheets for CPLDs and
FPGAs.

4) With the tools that you have you can program and simulate FPGA and CPLD
designs. You don't need any hardware if this is an academic exercise.

5) At some point, if you wish to test out your designs on real hardware
without having to build a special purpose board, there are many development
system boards available into which you can download code from your pc or
laptop via a 232 cable.

I hope this helps.

Tom Cipollone
Antares Audio Technologies




julia wrote:

> plz poit me to a tutorial in the net about the basics of FPGA and design.
>
>   Julia


Article: 31416
Subject: How to handle/store partial product in Core generator ?
From: "A. I. Khan" <aikhan@chat.carleton.ca>
Date: 22 May 2001 23:21:55 GMT
Links: << >>  << T >>  << A >>
Hi:

I'm trying to implement DA FIR Filter using Xilinx Core Generator system
for Virtex E. I'm now looking for the way to handle/store partial
products (not the coefficients) in Core generator.

Any idea would be highly appreciated.......

Thankx,

Khan


Article: 31417
Subject: ANN Implementations (Suitable FPGA Platform)
From: Shawki Areibi <sareibi@uoguelph.ca>
Date: Tue, 22 May 2001 19:29:21 -0400
Links: << >>  << T >>  << A >>
hi, we basically are experimenting with mapping a Neural Network on an
FPGA
platform. We are currently using an XS40 board from XESS but it is too
small
(based on the X4005) I was wondering if any of you have experience with
the following platforms (advantages, disadvantages e.t.c)
1) Spyder Virtex X2E platfrom
2) Celoxica (RC1000)
3) Avnet  ADS-XLX-VE-DEV (Vertex -E)
4) Derication PF3100
5) Virtual Computer Corp HOT II or Virtual Workbench

Any comments or experience using any of these systems is appreciated
Shawki

--
Shawki Areibi
Assistant Professor
School of Engineering
University of Guelph
Guelph, Ont, Canada N1G 2W1
Tel: (519) 824-4120
Fax: (519) 836-0227



Article: 31418
Subject: Re: xilinx webpack problem
From: Gonzalo Arana <gonzaloa@sinectis.com.ar>
Date: Tue, 22 May 2001 20:35:09 -0300
Links: << >>  << T >>  << A >>
Kent,

   Thank you very much for your help.  Without it I wouln't be able to
continue.

Kent Orthner wrote:
> 
> Gonzalo Arana <gonzaloa@sinectis.com.ar> writes:
> > Hi there,
> >
> >   I'm a beginner in the FPGA world (also in the VHDL world).
> >   My first 'project' is just a counter written in vhdl.
> >   I wrote it as an entity.
> 
> I'll try to help you out a bit.  Please see my comments below.
> I hope they help.
> 
> -Kent
> 
> ----------------------
.....
>        when "1110" => nextcnt <= "1101";
> --       when "1111" => nextcnt <= "1110"; borrowout <= '0';
> 
> --** Use "1111" as your others case.  (I doubt know if this
> --** makes a difference, but it's better to be sure.)
> 
>        when others => nextcnt <= "1110"; borrowout <= '0';
>      end case;
>    end process getNextState;
> 

Just a convention (right?), but I'll do it this way (perhaps the VHDL
'compiler'
feels beter this way).

>    -- purpose: Realiza el cambio de estado
>    -- type   : combinational
> 
> --** This is not a combinational process.  You want the outputs
> --** to change on the rising edge of Clock, so this is sequential
> --**type.

UPS! Yes, this is a clear example of out-dated documentation (it once
was
combinational).

> 
>    -- inputs : clock
>    -- outputs: cnt
> --**   shiftState: process (clock, incntenable, borrowin, nextcnt)
> 
> --** The sensitivity list should only include signals that cause the
> --** outputs of yout process to change.  In your case, only clock.

Absolutely right!
 
> --** This *ALWAYS* drives zeros to your borrows signal:
>         borrows <= "000000";

That was my intention..... (obviously wrong).

> 
> --** You don't need clock1:
>         clock1 <= clock;

That's right.  It was a test (since in the .mpr file sayed something
about clock signal,
just added this -desperate move-).

> 
> --** These counters are trying to drive the borrows(4 downto 0) signal.
> --** But a few lines above, you're driving '0's all the time.  To prevent
> --** damage to the chip, the synthesis tool or Place-n-Route tool will
> --** remove something.

THAT's IT!!!!!!!!!!!!
THIS WAS MY PROBLEM!!!!!!!!!!!!
REMOVING THAT LINE REMOVED ALL MY HEADACKES!!!!!!!!!!

>         contador0: counter port map (cuatro_ceros, cero, clock, borrows(0), uno, uno);
.....
>         contador5: counter port map (cuatro_ceros, cero, clock, led, borrows(4), uno);

Just another question (if I may): why this code doesn't work?

  contador: for i in 0 to 5 generate
     cntr0: if (i = 0) generate
        counter_rightest: counter port map (cuatro_ceros, cero, clock,
borrows(i), uno, uno);
     cntr1to4: if (i > 0 and i < 5) generate
        counter_middle:   counter port map (cuatro_ceros, cero, clock,
borrows(i), borrows(i-1), uno);
     cntr5: if (i = 5) generate
        counter_leftest:  counter port map (cuatro_ceros, cero, clock,
led, borrows(i-1), uno);
  end generate;
end behavioral; -- I get here the message: BEHAVIROAL simbol read,
GENERATE expected..

As fas as I know (which turns to be really near -haha-) just one 'end
generate;' sentence is necesary (and another would be wrong).  Am I
right?
If I add another 'end generate;' sentence, WebPack gives me the same
message in the 'end behavioral;' line.
Hope I'm not abusing of your kidness (this must sound terrible in
english, sorry!).

Thank you very much again for your useful help and tips.

Gonzalo

Article: 31419
Subject: Re: Counter problem
From: Ray Andraka <ray@andraka.com>
Date: Wed, 23 May 2001 01:45:39 GMT
Links: << >>  << T >>  << A >>
in the pre synthesis VHDL, zero is going to get assigned at either edge of the
clock and at either edge of the reset.  It doesn't get updated when state
changes state, but on the next clock edge. This is surely not the behavior you
wanted.

Synthesis matches code to templates.  The first part of your code will correctly
infer the state machine bits, but that last part does not really fit into a
standard template.  I think Synplicity will add state to the sensitivity list
and post a warning saying that the sensitivity list is incomplete.  That will
makes the logic for zero into a combinatorial decode of state.  Other
synthesizers may do something else. In any event, this produces a mismatch
between your pre synthesis simulation and what you get out of the synthesizer.

This is different than the merging signals.  That refers to how the logic is
packed in the CLBs.

Martin wrote:
> 
> Hi,
> 
> Yes, after reset all signals have the proper values in post-P&R simulation. The problem begins when the reset goes unactive and the counter starts to count.
> 
> The Xilinx map report says it merged some signals. Maybe that caused that problem ?
> 
> Regards, Martin

-- 
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com

Article: 31420
Subject: Aldec, Synplify (was: free simulator)
From: "Jeff Cunningham" <jcc@sover.net>
Date: Tue, 22 May 2001 22:15:03 -0400
Links: << >>  << T >>  << A >>
> > "Ray Andraka" <ray@andraka.com> wrote in message
news:3B09098F.73C778D8@andraka.com...
> > > plus it comes with a fisrt class HDL editor, tutorials and probably
the best
> > > on-line help in the industry.  If you are learning VHDL, Aldec would
be THE tool
> > > to get.

I am an experienced ModelSim VHDL user, but am looking for a cheaper
solution for a possible new job move. What am I likely to miss in going from
ModelSim to Active HDL? I know ModelSim likes to tout a close adherence to
standards. I guess ModelSim is more popular as a sign-off simulator for
ASICs. But for doing FPGAs is there really anything lost in going to Active
HDL? I see the Xilinx design manager has built in back-end simulation
support for both tools, so I guess there is no difference there.

I am a Synplify user and have seen on Synplicity's web site that they have
some sort of partner agreement with Aldec, but they don't go into much
detail. Can anyone comment on what this is all about - do you get a price
break when you buy them both? Is Aldec more tightly coupled with, say, HDL
Analyst than ModelSim PE is?

While we're on the subject, can anyone comment on the necessity of HDL
Analyst when using Synplicity? I have it now, but because of my style of
working, I basically never use it for optimizing my code, i.e. I don't
generally try to get that extra ns or two of performance. But what I do find
it very useful for is tracking down bugs in Synplify's mapper that seem to
arise every few months. I've always sort of resented that I have to have a
tool that costs as much as Synplify just for tracking down bugs in Synplify.
On the other hand, if I don't have it, it can be ultra tedious to sort
through the netlist to prove to Synplicity that their mapper has a bug. Are
there many people out there who use Synplify but not HDL Analyst?

Thanks for all your great advice!

Jeff





Article: 31421
Subject: Re: fast divider
From: Peter Alfke <palfke@earthlink.net>
Date: Wed, 23 May 2001 03:38:43 GMT
Links: << >>  << T >>  << A >>


glen herrmannsfeldt wrote:

> How fast, and how much hardware can you supply to it?
>
> There is always a tradeoff.
>
> Are both dividend and divisor 32 bits?
> (Traditionally, the dividend is twice as long as the divisor.)
>

And is the divisor realy a variable, or is it fairly stable and
1/x can be pre-computed, so that the problem becomes one of
multiplication ?
As an aside: Virtex-II now has many 18 x 18 combinatorial
multipliers that can help speed up the division, if you go for
the one-bit-per -clock successsive approximation method...

Peter Alfke, Xilinx Applications



Article: 31422
Subject: replace_fpga problem
From: "Michael w-y Lai" <eelwy@ee.ust.hk>
Date: Wed, 23 May 2001 13:42:36 +0800
Links: << >>  << T >>  << A >>
Why there still have some IOB exists in the design after I done
replace_fpga? how to solve it? Thank you




Article: 31423
Subject: LCD/CRT video controller and whole MMI in FPGA
From: "Zdenka Safarzik" <zdenka.safarzik@inet.hr>
Date: Wed, 23 May 2001 08:49:04 +0200
Links: << >>  << T >>  << A >>
One efficient LCD/CRT video controller FPGA implementation can be found on:
http://www.logicbricks.com

 The whole MMI (Man Machine Interface) system is implemented in Xilinx
XC2S100 (100Kgates -$20) device. The video controller, keyboard controller,
touch panel controller, SSFDC (SmartMedia silicon disk) controller, two
UARTs (one IrDA capable), SDRAM and FLASH controller and CPU (MIPS or 8051)
interface fits in $20 FPGA device.
The video controller alone, "consumes" less than 40% of FPGA real estate.

Zdenka Safarzik
zdenka.safarzik@inet.hr





Article: 31424
Subject: Block Select RAM+ Memory and NCSim
From: "Miha Dolenc" <mihad@opencores.org>
Date: Wed, 23 May 2001 09:41:20 +0200
Links: << >>  << T >>  << A >>
Hello everyone!

I'm a member of OPENCORES group and we are working on FREE IP PCI bridge
core.

I have a problem. I use NCSim and I can't seem to get primitives from XILINX
Spartan and Virtex working in it. We are trying to use Block SelectRAM+
cells for FIFO implementation.
I've compiled unisim and simprim libraries with NCVlog and got one warning
(log file doesn't show the reason) for each primitive in the library. When I
simulate FIFO design, all outputs are always HighZ, regardles of enable,
reset or any other signal. Does anyone know what to do?

Thanx!

Regards,
    Miha Dolenc

P.S.
    If anyone wants to help us out with actual core design please contat me
or visit our webpage
http://www.opencores.org/cores/pci/





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