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Messages from 31425

Article: 31425
Subject: SPARTANII prototype boards + microcontroller available
From: Richard Meester <rme@quest-innovations.com>
Date: Wed, 23 May 2001 10:01:00 +0200
Links: << >>  << T >>  << A >>
Hello all,

The spartan II prototype boards are in stock again. We have decided to
release the Sourcecode for the onboard microcontroller for free to the
buyers of the spartanII board and also the board configuration software
that enables the users to set the clock speed etc.. This enables them to
use 12 i/o lines that can be connected to the microcontroller. Secondly
we lowered the price of the Q-bic kit. The software includes FPGA
programming algorithms and I2C eeprom functionality. It is possible to
hook up the FPGA to the I2C.

Take a look at www.quest-innovations.com

Richard.

--
Quest Innovations
tel: +31 (0) 227 604046
http://www.quest-innovations.com



Article: 31426
Subject: Re: Counter problem
From: Stephane <sjulhes@free.fr>
Date: Wed, 23 May 2001 08:34:57 GMT
Links: << >>  << T >>  << A >>
It seems that the zero signal initialization is missing on reset ?
Zero is undefined until state reaches 0 value.

Stephane.

Martin a écrit :

> Hi,
>
> Does anybody know what can be wrong with that code ?
>
> --- Code starts here ---
>
> entity DownCounter is
> generic( PresetValue: integer := 1023 );
> port(   Reset:  in std_logic;           Clk:    in std_logic;           Zero:   out std_logic           );
> end DownCounter;
>
> architecture Behaviour of DownCounter is
> begin
> Controller: process( Reset, Clk )
>         variable state: integer range 0 to PresetValue;
> begin
>         if( Reset = '1' ) then
>                 state := PresetValue;
>         elsif( Clk'event and Clk = '0' ) then
>                 if( state = 0 ) then
>                 state := PresetValue;
>         else
>                 state := state - 1;
>         end if;
>         end if;
>
>         if( state = 0 ) then
>                 Zero <= '1';
>         else
>                 Zero <= '0';
>         end if;
> end process Controller;
> end Behaviour;
>
> --- End of code  ----
>
> I use the Synplify 6.1.3 to synthesis and simulation after that operation is OK. The problem is in simulation after the Place&Route for Xilinx Spartan2 150k + Service Pack 7, which gives all 'X' signals. What can be wrong ?
>
> Regards,
> Martin


Article: 31427
Subject: RS422 - RS485 conversion
From: "Stefaan Vanheesbeke" <stefaan.vanheesbeke@planetinternet.be>
Date: Wed, 23 May 2001 11:30:17 +0200
Links: << >>  << T >>  << A >>
Someone has some code for a conversion from 422 to 485? (point to point
input, multidrop output)

Thanks




Article: 31428
Subject: Re: Counter problem
From: Martin <martin.t@yours.com>
Date: Wed, 23 May 2001 03:33:53 -0700
Links: << >>  << T >>  << A >>
Hi

Thanx for help ! The problem was in the test bench.

Regards,

Martin

Article: 31429
Subject: Re: RLocs on Inferred registers??
From: hamish@cloud.net.au
Date: Wed, 23 May 2001 11:23:21 GMT
Links: << >>  << T >>  << A >>
n# <n@n.com> wrote:
> problem (only small chips!). What I have found tends to happen with the
> Xilinx P&R tools, is that bussed registers get bunched up (when not RLoced
> or on the output of an adder etc), so, for example, if trying to add a level
> of pipeling to an already registered adder output which feeds input of
> another adder, we end up with a jiggered placement; instead of getting a
> nice adder 'stick' followed by a register 'stick' and then the other adder
> 'stick', the two adder sticks remain, but the middle register gets bunched
> up, (strangely, usually above and to the left) - not sure I have explained
> this as clearly as I could...!. Also, adding RLocs to large designs

Depending on how you name your signals, that might just be MAP
being 'helpful.' I posted a bit about this recently (register ordering in
map).

> considerably reduces P&R time in my experience . The bunching situation is
> particularly bad when using SRL16 primitive, which I have had to completely
> rloc down to get sensible PAR times and scores/repeatbility. 

In my experience you would not want the output of an SRL16(E) to drive
any logic directly; put a real FF on the end of the register instead.
Much better clock to out. Some early speed files had really badly
incorrect clock to out on the SRL16E too. :-(

> The UCF solution is also not good IMHO as I believe that it would need to be
> modified after synthisys each time (the names have been changed to persicute
> the innocent?)

Hmm; the names of your registers shouldn't change in synthesis. The names
of intermediate signals might though. (G_*, N_*, and un_* in Synplify
typically.)

> I guess I am asking for synthis with some ammount of placement, or an
> 'inteligent' P&R that doesn't start from a random seed, but rather takes a
> look at the data flow - I know, I know, take a number and get in line. I

Sounds good to me too.

Actually, I'd like an easy way to tell PAR to route block X to spec, 
then block Y, then the rest, or something like that. I've found a few
really messy ways to do it (eg guide files, or lots of LOCs from
past successful routes, or even the modular flow), but nothing clean.

Hamish
-- 
Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>

Article: 31430
Subject: block diagrams
From: "Vivian" <vivian.bessler@ucd.ie>
Date: Wed, 23 May 2001 15:05:38 +0100
Links: << >>  << T >>  << A >>
Does anyone know of a tool to draw block diagrams from verilog code.
Currently I synthesis the code in express, view the schematic and print it
out from there.  This is a lengthy process and the diagrams do not come out
very well on A3 pages (I have to stick several A3 pages together).

Thanks,
Viv



Article: 31431
Subject: FPGA Setup/Configuration Documentation
From: "Dave Feustel" <dfeustel@mindspring.com>
Date: Wed, 23 May 2001 12:33:32 -0500
Links: << >>  << T >>  << A >>
I'm interested in learning more about how
FPGAs are initialized during configuration.
Is there publically available documentation on
the way downloaded bit streams set up Atmel
and Xilinx FPGAs during configuration (Particularly
the Atmel FPSLIC)?

Do any of the open source EDA tools support
configuration of these FPGAs?

Thanks,

Dave Feustel
Fort Wayne, Indiana
1-219-483-1857



Article: 31432
Subject: Re: fast divider
From: eteam <eteam@aracnet.com>
Date: Wed, 23 May 2001 12:51:12 -0700
Links: << >>  << T >>  << A >>
There also some compact radix-4 divide algorithms that use
add/subtract/accumulate rather than multiply in the
"inner loop".  I designed one at Bipolar Integrated Technology in
the mid-80s, based largely on work published by a Greg Taylor.

I'm unfamiliar with the V-II multiplier block performance, but
using add/sub/acc usually results in a very fast iteration cycle.

-- Bob Elkind, eteam@aracnet.com

You might turn up some references with some web searching...

Peter Alfke wrote:
> 
> glen herrmannsfeldt wrote:
> 
> > How fast, and how much hardware can you supply to it?
> >
> > There is always a tradeoff.
> >
> > Are both dividend and divisor 32 bits?
> > (Traditionally, the dividend is twice as long as the divisor.)
> >
> 
> And is the divisor realy a variable, or is it fairly stable and
> 1/x can be pre-computed, so that the problem becomes one of
> multiplication ?
> As an aside: Virtex-II now has many 18 x 18 combinatorial
> multipliers that can help speed up the division, if you go for
> the one-bit-per -clock successsive approximation method...
> 
> Peter Alfke, Xilinx Applications

Article: 31433
Subject: Re: Can anyone comment on the difference between modelsim PE and XE
From: Mike Treseler <mike.treseler@flukenetworks.com>
Date: Wed, 23 May 2001 14:44:03 -0700
Links: << >>  << T >>  << A >>
Jeff Cunningham wrote:
> 
> I'm a user of ModelSim PE/VHDL. For financial reasons beyond my control I am
> being asked to consider switching to modelsim XE. I recall seeing somewhere
> that XE is literally just a slowed down version of PE (something like 3x or
> 5x). Can anyone familiar with both products confirm this? Is the only
> difference how fast they run? Do you still get all the windows, the ability
> to set breakpoints, etc? It is not limited in the size of the source code or
> anything like that is it? Thanks in advance.

For small altera devices, you can get free modelsim 5.4e with E+max
WebPack. Xylinx has the same deal for their devices using
modelsim XE with WebPack. All the usual windows work.

      -Mike Treseler

Article: 31434
Subject: C Source for BOOZER (BOOlean ZEro-one Reduction) Program
From: "Dave Feustel" <dfeustel@mindspring.com>
Date: Wed, 23 May 2001 16:59:58 -0500
Links: << >>  << T >>  << A >>
I'm looking for C source for the BOOZER Program originally
developed by Dr. William Fletcher. Fletcher's book (An Engineering
Approach to Digital Design) has an appendix containing an ALGOL
60 source listing, but I'd like to save myself some trouble of translation
and get a version written in C, if such a version exists. Does anyone know
where a C version of BOOZER is to be found?

Thanks,

Dave Feustel





Article: 31435
Subject: frequency ramp
From: "vi" <vi_ismyname@hotmail.com>
Date: Wed, 23 May 2001 17:13:13 -0700
Links: << >>  << T >>  << A >>
Anybody knows of the best way to implement a frequency ramp in a schematic
format(ie. logic)?

Thanks



Article: 31436
Subject: Re: frequency ramp
From: John Fields <jfields@austininstruments.com>
Date: Wed, 23 May 2001 19:40:40 -0500
Links: << >>  << T >>  << A >>
vi wrote:
> 
> Anybody knows of the best way to implement a frequency ramp in a schematic
> format(ie. logic)?
> 
> Thanks


---

Yeah, sure...

Restabulate the vinducicator.

---
To email, please add "nospam" to the end of the subject text.

John Fields,                   Austin Instruments, Inc.
El Presidente                  Austin, Republic of Texas
"I speak for my company"       http://www.austininstruments.com

Article: 31437
Subject: Re: FPGA consultant needed
From: "Austin Franklin" <austin@dar54kroom.com>
Date: Wed, 23 May 2001 23:36:05 -0400
Links: << >>  << T >>  << A >>
> What they search in here is someone who will be paid to
> pretend this is a real invention.

I take it you haven't seen the "wall of patents" at Xilinx?  Xilinx has many
patents, that IMO, should not have ever been issued in the first place...but
when you can re-word an "and" gate (non-specific example to make a point) to
sound like something new and innovative, and you have "good" (read that
anyway you want) lawyers, you can get a patent for just about anything that
we all consider common knowledge.

Intel is one of the kings of this...  Problem is, the patent examiners for
this type of technology aren't really the top of the field...why would you
expect them to be, when they can be making 2x the money plus stock options
as a professional engineer?

Now, if you're forte is fishing lures, working at the Patent Office is going
to pay you a HELL of a lot more than almost anything else you can do dealing
with fishing lures, and you would be doing something you like...




Article: 31438
Subject: Re: FPGA consultant needed
From: "Kevin Neilson" <kevin_neilson@yahoo.com>
Date: Thu, 24 May 2001 04:52:17 GMT
Links: << >>  << T >>  << A >>
The funny thing about a lawsuit won by Xilinx recently against Altera (which
I think has since been overturned) was that it was decided by a jury of
which only one person had any post-high-school education.  I doubt that even
that one person had any knowledge of electronics.  This seems to be a flaw
in the whole patent system.  How can citizens, most with no knowledge even
of what a transistor is, be expected to decide a case in which the esoteric
details are only well-understood by people with years of education and
experience in the field?  Even really intelligent technical people in
non-FPGA fields, like my brother the software engineer, don't grasp the
concept of reconfigurable chips.

The legal strategy seems to be mostly about spreading confusion amongst the
jury.  I gather the trial was something like this:  "Look at the Xilinx.  It
has lookup tables.  Look at the Altera.  What do we see?  Lookup tables!
A-ha!"

"Joe Gentile, III" <tabeast@ex-pressnet.com> wrote in message
news:tgam6fl5mg0bf5@corp.supernews.com...
> Technical Assistance Bureau, Inc
> 11469 Olive Boulevard, Suite 108  St. Louis, MO 63141
> Division of Resource Development
> Toll Free Voice:888-547-5124   Toll Free Fax: 888-738-4539          URL:
> http://www.tabexperts.com       email: joegentile@tabexperts.com
>
> MEMORANDUM FROM JOSEPH GENTILE
>
> RE: Altera v. Xilinx
>
>  We are a professional services corporation providing consulting services
to
> lawyers and insurance companies when technical expertise is required to
> resolve matters in litigation.
>
>  We have a client/lawyer in San Francisco who represents Altera in a
patent
> infringement case against Xilink, who needs someone with a background in
> programmable logic array chip design (architecture not fabrication)
relating
> to the inclusion of RAM memory. to consult and hopefully serve as an
expert
> witness someday on behalf of Altera.
>




Article: 31439
Subject: Re: xilinx webpack problem
From: Kent Orthner <korthner@hotmail.nospam.com>
Date: 24 May 2001 13:55:46 +0900
Links: << >>  << T >>  << A >>
Gonzalo Arana <gonzaloa@sinectis.com.ar> writes:

> Kent,
>    Thank you very much for your help.  Without it I wouln't be able to
> continue.

No problem.

> Just a convention (right?), but I'll do it this way (perhaps the VHDL
> 'compiler' feels beter this way).

I believe it's just a convention, but I've never seen it done any other 
way.  (With the exception of strings)

> Just another question (if I may): why this code doesn't work?
> 
>   contador: for i in 0 to 5 generate
>      cntr0: if (i = 0) generate
>         counter_rightest: counter port map (cuatro_ceros, cero, clock,
>         borrows(i), uno, uno);
>         cntr1to4: if (i > 0 and i < 5) generate
>           counter_middle:   counter port map (cuatro_ceros, cero, clock,
>           borrows(i), borrows(i-1), uno);
>           cntr5: if (i = 5) generate
>             counter_leftest:  counter port map (cuatro_ceros, cero, clock,
>                  led, borrows(i-1), uno);
>       end generate;
> end behavioral; 

What you're asking it to do doesn't make sense.  Your 'contador' 
statement looks fine.  Then, you only execute the lines after cntr0 if i 
is zero.  That means that the cntr1to4 line is only executed if i is 0.  
Which means that it is never 1 < i < 5.

Also, you do need an end generate for each generate statement.  You do 
not need to label your generate statments (label:), but ifyou do, you need
an end label.

I think what you are trying to do is this:

...
begin
  contador: for i in 0 to 5 generate

     cntr0: if (i = 0) generate
        counter_rightest: counter port map (cuatro_ceros, cero, clock,
             borrows(i), uno, uno);
     end generate cntr0;

     cntr1to4: if (i > 0 and i < 5) generate
        counter_middle:   counter port map (cuatro_ceros, cero, clock,
             borrows(i), borrows(i-1), uno);
     end generate cntr1to4;


     cntr5: if (i = 5) generate
        counter_leftest:  counter port map (cuatro_ceros, cero, clock,
             led, borrows(i-1), uno);
     end generate cntr5;

  end generate contador;  -- You need the end label.
end behavioral; 


... and what some people might find even more elegant:


...

  --** I changed the size of this vector:
  signal borrows : std_logic_vector(6 downto 0);  
begin

  borrows(0) <= '1';  --** Input to Counter #1
  led <= borrows(6);  --** Output from Counter #6

  contador: for i in 0 to 5 generate

     counter:   counter port map (cuatro_ceros, cero, clock,
             borrows(i+1), borrows(i), uno);

  end generate contador;  -- You need the end label.

end behavioral; 

-- I get here the message: BEHAVIROAL simbol read,
> GENERATE expected..

Because you wrote end behavioral, and it was still waiting for end generate.

> 
> As fas as I know (which turns to be really near -haha-) just one 'end
> generate;' sentence is necesary (and another would be wrong).  Am I
> right?

Nope.  You need an end generate for EVERY generate.  So in your 
case you needed 4.

> If I add another 'end generate;' sentence, WebPack gives me the same
> message in the 'end behavioral;' line.

That's becase if you added one, you had two.  You needed 4!

> Hope I'm not abusing of your kidness (this must sound terrible in
> english, sorry!).
> Thank you very much again for your useful help and tips.

No problem at all.  Hope it helps.

-kent

Article: 31440
Subject: Re: frequency ramp
From: Paul Burke <paul@scazon.com>
Date: Thu, 24 May 2001 08:03:49 +0000
Links: << >>  << T >>  << A >>
vi wrote:
> 
> Anybody knows of the best way to implement a frequency ramp in a schematic
> format(ie. logic)?
> 
> Thanks

Don't know if it's best but here's a few ways:

(1) Oscillator -> binary rate multipliers-> output

A counter clocked at the frequency ramp rate, counts up or down. Counter
output to BRMs.

(2) Counter->DAC->VCO

(3) Divide-by-N counter. Another counter ramps N. Non- linear frequency
ramp.

(4) Analog ramp circuit -> VCO (not logic).

(5) Microcontroller generates frequency. Software controls ramping.

Could go on a bit... what's it for?

Paul Burke

Article: 31441
Subject: Altera APEX internal signal coupling ?
From: il_templare@hotmail.com (g. giachella)
Date: 24 May 2001 01:54:14 -0700
Links: << >>  << T >>  << A >>
I'd like to know if anyone experienced this strange behaviour.
 
I have placed my design on an APEX 20KE1000 - 2X and here are the
resource used:
 
1) 60 % of LEs
 
2) no PLL used
 
3) no DEV_CLRn currently used (the design internal reset has a fanout
of 5000)
 
4) 8/8 global resources (clocks) used
 
Simulation after placement is ok and I have tested 2 different
versions.Let's call then Version_A and Version_B. They are sligthly
different.
After programming the device, Version_A shows an I/O IO_A that, when
asserted, oscillates at a frequency CLK_A. This frequency
(an internal clock) has no relation with the logic driving IO_A.
A completely different board using Version_A shows the same problem.
 
After programming the device, Version_B shows an output OUT_B
oscillating at a frequency CLK_B. This frequency
(again an internal clock) has no relation with the logic driving
OUT_B. Here IO_A does not show any oscillation.
 
We have checked the APEX power and ground pins  - analog (PLL) and
digital - and everything seems to be connected in
the right way. 
 
Any suggestion ?

Article: 31442
Subject: PCI core PROGRESS
From: "Tadej" <tadej@opencores.org>
Date: Thu, 24 May 2001 16:32:08 +0200
Links: << >>  << T >>  << A >>
Hi to all !

Status for CPI core:
FIFO module will be verified soon (by Miha), what will be somehow an
interface (or a major part of an interface) between PCI master/target and
WISHBONE slave/master.
An address decoder module (with address translation) will be finished soon
(by Tilen).
Miha would also like to do the WISHBONE slave module, when he will finish
the FIFO and I started with the WISHBONE master module.

So, if there is anybody interested to contribute to the PCI core (PCI
interface or a part of it, maybe verification, etc.), feel free to post your
message and to subscribe to PCI mailing list on OpenCores web page:
http://www.opencores.org/cores/pci/
Whatever you contribute, will be used and all the guys that help in
development, specification or verification will appear as co-authors on
OpenCores webpage, if they want.

Regards, Tadej.



Article: 31443
Subject: Need allegro footprint for Intel's IXP1200 ?
From: Nikhil Kumar Mittal <gt6671d@prism.gatech.edu>
Date: Thu, 24 May 2001 11:59:06 -0400
Links: << >>  << T >>  << A >>
Hello,
DO anybody have Allegro footprint for Intel's IXP1200 network processor
chip ? We are doing a design using this chip but we do not have the
physical part footprint for this chip. Also if anybody has a Concept
symbol then it would be great. Unfortunately we are not able to get
access to these from Intel (!!!).
Thanks,


Article: 31444
Subject: Re: frequency ramp
From: Ray Andraka <ray@andraka.com>
Date: Thu, 24 May 2001 17:04:00 GMT
Links: << >>  << T >>  << A >>
I'd use a DDS whose increment value is incremented at the desired rate.  It is
basically two accumulators:

inc_value<= inc_value+sweep_rate;
dds_acc<= dds_acc + inc_value;
square_wave_out<= dds_acc(dds_acc'left);

The frequency of the square output is  inc_value*fclk/2^k  where k is the number
of bits in the dds_accumulator.  the inc_value accumulator basically integrates
the rate to get a linear frequency sweep.  The dds_accumulator represents the
fractional phase angle of a rotating phasor, so the msb is a square wave.  If
you want, you can use the top N bits to drive a conversion from phase angle to
arbitrary waveshape.


Paul Burke wrote:
> 
> vi wrote:
> >
> > Anybody knows of the best way to implement a frequency ramp in a schematic
> > format(ie. logic)?
> >
> > Thanks
> 
> Don't know if it's best but here's a few ways:
> 
> (1) Oscillator -> binary rate multipliers-> output
> 
> A counter clocked at the frequency ramp rate, counts up or down. Counter
> output to BRMs.
> 
> (2) Counter->DAC->VCO
> 
> (3) Divide-by-N counter. Another counter ramps N. Non- linear frequency
> ramp.
> 
> (4) Analog ramp circuit -> VCO (not logic).
> 
> (5) Microcontroller generates frequency. Software controls ramping.
> 
> Could go on a bit... what's it for?
> 
> Paul Burke

-- 
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com

Article: 31445
Subject: Re: frequency ramp
From: RP Henry <richard.p.henry@saic.com>
Date: Thu, 24 May 2001 10:21:17 -0700
Links: << >>  << T >>  << A >>
vi wrote:
> 
> Anybody knows of the best way to implement a frequency ramp in a schematic
> format(ie. logic)?
> 
> Thanks

What do you mean by ramp?  Linear, log, exponential, etc?

Article: 31446
Subject: Re: frequency ramp
From: Jim_Thompson <Jim-T@analog_innovations.com>
Date: Thu, 24 May 2001 10:29:12 -0700
Links: << >>  << T >>  << A >>
On Thu, 24 May 2001 10:21:17 -0700, RP Henry
<richard.p.henry@saic.com> wrote:

|vi wrote:
|> 
|> Anybody knows of the best way to implement a frequency ramp in a schematic
|> format(ie. logic)?
|> 
|> Thanks
|
|What do you mean by ramp?  Linear, log, exponential, etc?

On my website, Subcircuits section, is a function generator that
*might* be of use to you, if you're using PSpice or certain other
Spice's.

(If replying by E-mail please observe obscure method of anti-spam.)

                                        ...Jim Thompson
-- 
|  James E.Thompson, P.E.                           |    mens     |
|  Analog Innovations, Inc.                         |     et      |
|  Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    |
|  Phoenix, Arizona            Voice:(480)460-2350  |             |
|  Jim-T@analog_innovations.com  Fax:(480)460-2142  |  Brass Rat  |
|       http://www.analog-innovations.com           |    1962     |

             For proper E-mail replies SWAP "-" and "_".

Article: 31447
Subject: Re: frequency ramp
From: "vi" <vi_ismyname@hotmail.com>
Date: Thu, 24 May 2001 10:47:26 -0700
Links: << >>  << T >>  << A >>
It is for a stepper motor control via fpga.  I use Xilinx.
Rather it ramp linear, log, or exponential is not too important at this
time.   I will test it ramping up and down.



Article: 31448
Subject: Re: Vhdl coding style for fpga
From: "Tom Verbeure" <tverbeure@globespan.net>
Date: Thu, 24 May 2001 17:07:18 -0400
Links: << >>  << T >>  << A >>

Some (including myself) prefer the single process one, others the two
process. I think there is that obscure book (design reuse manual ?) that
advocates the two process style...
It is a matter of personal preference that has been discussed here in the
past. Don't expect a definitive answer because there isn't one. AFAIK a
capable synthesis tool should produce the same result.


Tom




Article: 31449
Subject: Vhdl coding style for fpga
From: Jamil Khatib <khatib@ieee.org>
Date: Thu, 24 May 2001 23:08:10 +0200
Links: << >>  << T >>  << A >>
As far as I know it is recommended to write state machines using two
processes one registered (synchronous) and one for the combination
logic.
In this method I have to assign always the states in the combinational
process even if the state should not change or latch will be inferred.
after synthesis logic will be used to assign the FF value at each clock.

In the single process I do not have to assign value to the state ff only
when it should change. This produces after synthesis FF with Clock
enable already existing on the FF will be used which reduces the logic.

So which coding style is better for FPGAs??

================
-- 2 processes
process(clk)
begin
p_state <=  n_state;

end process;

process(input,pstate)
begin

case state
when '0' =>
if input  ='1' then
    state <= '1';
else
  state <= '0';
end if;
when '1' =>
.......
end process;

=============
-- Single process
process(clk)
begin
case state
    when '0' =>
    if input  ='1' then
        state <= '1';
    end if;
when '1' =>
    .......
end process;
=============

Regards
Jamil




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