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Messages from 31450

Article: 31450
Subject: spartan xl rise/fall time ?
From: eteam <eteam@aracnet.com>
Date: Thu, 24 May 2001 17:29:46 -0700
Links: << >>  << T >>  << A >>
The spartan xl data sheet doesn't have a min or max on the risetime or falltime of outputs.

Anyone have this information handy, for limited slew rate mode ?

Thanks, in advance...

Bob Elkind

Article: 31451
Subject: Re: frequency ramp
From: Jim Granville <jim.granville@designtools.co.nz>
Date: Fri, 25 May 2001 13:01:54 +1200
Links: << >>  << T >>  << A >>
vi wrote:
> 
> It is for a stepper motor control via fpga.  I use Xilinx.
> Rather it ramp linear, log, or exponential is not too important at this
> time.   I will test it ramping up and down.

 What Step-Clock range do you need ?

 We did a Stepper design recently, fitted into a Atmel ATF1504ASL CPLD,
( so fpga may be an overkill.. ) 
that had a very wide Step-clock range,( 1Hz-200KHz), 
with < 0.5% define at any speed, and controlled from a rotary knob, 
with a sister uC option for speed/profile operations.

-jg

-- 
======= 80x51 Tools & IP Specialists  =========
= http://www.DesignTools.co.nz

Article: 31452
Subject: Re: FPGA
From: "Martin Schoeberl" <martin.schoeberl@chello.at>
Date: Fri, 25 May 2001 08:29:43 GMT
Links: << >>  << T >>  << A >>
> it is plenty for a beginner. I don't know if Altera has a free tool suite.
> Several years ago I used the "Lattice"  tool suite, which was free back
then.

Altera has free tools (with Versions of Leonardo and Synopsys for VHDL and
Verilog)
I'm working with Leonardo and max-plus baseline and it's fine for me.

http://www.altera.com/products/software/free/fre-emax_baseline.html
http://www.altera.com/products/software/free/fre-download_0.html

Martin
--
Whant to see the evolution of a Java processor?

         http://www.jopdesign.com




Article: 31453
Subject: Re: Need A little prog?
From: "Martin Schoeberl" <martin.schoeberl@chello.at>
Date: Fri, 25 May 2001 08:37:25 GMT
Links: << >>  << T >>  << A >>
Take a look to my design of a Java Processor (with uart :-) for FPGAs

         http://www.jopdesign.com

Martin

"Frederic Darre" <darre@irit.fr> schrieb im Newsbeitrag
news:9eaocm$nbs$1@news.cict.fr...
> To communicate with the FPGA, i have a program coded in java, but i want
to
> write a program inside the FPGA for communication.
>
> "frederik" <ffrederiksen@hotmail.com> a écrit dans le message news:
> 9eam01$laa$1@news.net.uni-c.dk...
> > Why not use the HyperTerminal program that comes with Windows?
> >
> >
> >
> >
>
>



Article: 31454
Subject: JTAG source
From: Richard Meester <rme@quest-innovations.com>
Date: Fri, 25 May 2001 12:10:41 +0200
Links: << >>  << T >>  << A >>
Hello all,

Is there any source code available which describes the JTAG interface?

Richard

--
Quest Innovations
tel: +31 (0) 227 604046
http://www.quest-innovations.com



Article: 31455
Subject: Re: JTAG source
From: "Dave Feustel" <dfeustel@mindspring.com>
Date: Fri, 25 May 2001 06:13:16 -0500
Links: << >>  << T >>  << A >>
IEEE has a couple of documents which describe the JTag interface.
It's my impression that each manufacturer adds proprietary commands
to the basic set defined by the IEEE 1149.1 standard and getting info
on those proprietary commands may be difficult.

"Richard Meester" <rme@quest-innovations.com> wrote in message news:3B0E2FA1.B2E4D37F@quest-innovations.com...
> Hello all,
>
> Is there any source code available which describes the JTAG interface?
>
> Richard
>
> --
> Quest Innovations
> tel: +31 (0) 227 604046
> http://www.quest-innovations.com
>
>



Article: 31456
Subject: who needs clk180
From: "Meelis Kuris" <matiku@hot.ee>
Date: Fri, 25 May 2001 15:20:37 +0300
Links: << >>  << T >>  << A >>
Hi,

In Virtex-II, DCM has outputs clk180, clk2x180 and clkfx180.
Why should anybody need them if it's possible just to use falling
edge of clock? The same applies to clk270, I can
just use falling edge of clk90 instead of it. And this way only 1 clock
buffer is needed.

Just curious,

Meelis



Article: 31457
Subject: Re: spartan xl rise/fall time ?
From: Austin Lesea <austin.lesea@xilinx.com>
Date: Fri, 25 May 2001 07:57:10 -0700
Links: << >>  << T >>  << A >>
Bob,

Use the IBIS files with an IBIS simulator (I use HyperLynx by Innoveda).  This is THE ONLY WAY
to answer questions like the one you pose.  You must simulate it with the load you have (the
pcb trace of Zx ohms impedance Y inches long, into Device X1, etc).

With a 10K ohm resistor, and no pcb, and no device load, I get 117 ps for the FAST attribute,
and 663 ps for the LSOW attribute at the fast/strong IBIS corner.

The fast/strong IBIS corner is the fastest silicon, at the coldest ambient, at the highest
Vcc.  It has nothing to do with the IOB attribute of "FAST" or "SLOW"

Austin

eteam wrote:

> The spartan xl data sheet doesn't have a min or max on the risetime or falltime of outputs.
>
> Anyone have this information handy, for limited slew rate mode ?
>
> Thanks, in advance...
>
> Bob Elkind


Article: 31458
Subject: Re: spartan xl rise/fall time ?
From: Bob Perlman <bob@cambriandesign.com>
Date: Fri, 25 May 2001 15:41:59 GMT
Links: << >>  << T >>  << A >>
On Fri, 25 May 2001 07:57:10 -0700, Austin Lesea
<austin.lesea@xilinx.com> wrote:

>Bob,
>
>Use the IBIS files with an IBIS simulator (I use HyperLynx by Innoveda).  This is THE ONLY WAY
>to answer questions like the one you pose.  You must simulate it with the load you have (the
>pcb trace of Zx ohms impedance Y inches long, into Device X1, etc).
>
>With a 10K ohm resistor, and no pcb, and no device load, I get 117 ps for the FAST attribute,
>and 663 ps for the LSOW attribute at the fast/strong IBIS corner.

What's the package?  Has anyone actually seen a 117ps-risetime edge
escape from any of the currently-available Spartan XL packages?

Bob Perlman


Article: 31459
Subject: Jobs ASIC / FPGA / VLSI designers needed - Canada
From: "PROCOM" <derekw@procom.ca>
Date: Fri, 25 May 2001 13:29:12 -0400
Links: << >>  << T >>  << A >>
Our client is the leading provider of highly integrated silicon solutions
that enable broadband digital transmission of voice, video, and data. Using
proprietary technologies and advanced design methodologies, the company
designs, develops and supplies integrated circuits for a number of the most
significant broadband communications markets, including the markets for
cable set-top boxes, cable modems, high-speed local, metropolitan and wide
area networks, home networking, Voice over Internet Protocol (VoIP),
residential broadband gateways, direct broadcast satellite and terrestrial
digital broadcast, optical networking, digital subscriber lines (xDSL) and
wireless communications.

They are currently seeking ASIC Designers with the following...

Required Skills and Experiences:

BSEE or equivalent; MSEE preferred, plus 5+ years' of VLSI hardware design
experience.
Position requires working knowledge of Verilog and Synopsys.
Experience with back-end CAE, layout tools, 3D, video, and DSP is a plus.


Responsibilities:

Responsibilities include: definitions of the molecules specifications based
on the system specification; RTL development and debugging, test bench
development; design validation as part of an overall system, system
integration; synthesis of the RTL at a certain clock speed; Implementation
of the test strategy, scan insertion, ATPG test vectors generation.


PROCOM: Established in 1978, Professional Computer Consultants Group Ltd.
(Procom) is a national leader in the provision of Computer personnel on a
contract
and full-time basis. Our clients are comprised of the largest national and
international corporations that utilize technical resources extensively
across a wide range of disciplines. In the Financial Post (March 1999)
Procom was ranked as the 6th largest professional Services Company in
Canada. In November of 1999, Procom was named a Regional finalist in Canada'
s 50 Best Managed Private companies. Our track record is proven with more
than 180 consultants servicing Ottawa's high tech community and more than
1600 Procom consultants currently on assignment throughout. North America.
For further information on this and other opportunities please visit our web
site at www.procom.ca.

Interested candidates are invited to forward their resumes or questions in
confidence to:



Derek Weber
PROCOM

300 March Rd Suite 600
Kanata, Ontario
K2K-2E2
613-270-9339 x231
613-270-9449 (FAX)

derekw@procom.ca
www.procom.ca





Article: 31460
Subject: Re: FPGA
From: "Luk Michel St.Onge" <lstonge@ieee.org>
Date: Fri, 25 May 2001 14:59:53 -0400
Links: << >>  << T >>  << A >>
> plz poit me to a tutorial in the net about the basics of FPGA and design.

This is a pretty broad request, but if you are using (or end up using) the
Xilinx Foundation  Series Software (say the student edition with development
board), this site may be of help to you:

Design of Digital Control Devices Using XS40TM FPGA Board,
http://www.csit-sun.pub.ro/research/fpga/fpga_design/

And if you use VHDL this is another fairly good site:

VHDL Online Manual (with VHDL and FSM tutorials, and soon to have a specific
section on FPGA's),
http://www.vhdl-online.de/~vhdl/

Hope this is of at least SOME help.  Good luck,

Luk



Article: 31461
Subject: Re: JTAG source
From: cyber_spook <pjc@cyberspook.freeserve.co.uk>
Date: Fri, 25 May 2001 21:55:10 +0100
Links: << >>  << T >>  << A >>
Try the documents scetion of the Alter web site

cyber_spook_man


Richard Meester wrote:

> Hello all,
>
> Is there any source code available which describes the JTAG interface?
>
> Richard
>
> --
> Quest Innovations
> tel: +31 (0) 227 604046
> http://www.quest-innovations.com


Article: 31462
Subject: xilinx webpack warning !!
From: "Speedy Zero Two" <david@manorsway.freeserve.co.uk>
Date: Fri, 25 May 2001 22:58:37 +0100
Links: << >>  << T >>  << A >>
Hello,

I have a large design which when targeting a 300 series devices gives
several warning, (like below).
As this is an internal node how do I find out what to change to correct it.

Cheers
Dave


WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net MUX_OBUF is
sourced
   by a combinatorial pin. This is not good design practice. Use the CE pin
to
   control the loading of data into the flip-flop.



Article: 31463
Subject: Re: Xilinx Coolrunner 100% routable - but the tools aren't
From: z80@ds2.com (Peter)
Date: Fri, 25 May 2001 23:02:19 +0100
Links: << >>  << T >>  << A >>
Haven't Xilinx dropped the Coolrunner line - after buying it from
Philips?????

Peter.
--
Return address is invalid to help stop junk mail.
E-mail replies to zX80@digiYserve.com but remove the X and the Y.
Please do NOT copy usenet posts to email - it is NOT necessary.

Article: 31464
Subject: Re: Xilinx Coolrunner 100% routable - but the tools aren't
From: Peter Alfke <peter.alfke@xilinx.com>
Date: Fri, 25 May 2001 16:06:06 -0700
Links: << >>  << T >>  << A >>
CoolRunner is very much alive and well, as part of Xilinx.

Peter Alfke
=======================
Peter wrote:

> Haven't Xilinx dropped the Coolrunner line - after buying it from
> Philips?????
>
> Peter.
> --
> Return address is invalid to help stop junk mail.
> E-mail replies to zX80@digiYserve.com but remove the X and the Y.
> Please do NOT copy usenet posts to email - it is NOT necessary.


Article: 31465
Subject: Re: Xilinx Coolrunner 100% routable - but the tools aren't
From: Peter Alfke <peter.alfke@xilinx.com>
Date: Fri, 25 May 2001 16:43:48 -0700
Links: << >>  << T >>  << A >>

--------------5640F8382D41D79351968B74
Content-Type: text/plain; charset=us-ascii; x-mac-type="54455854"; x-mac-creator="4D4F5353"
Content-Transfer-Encoding: 7bit

Seven month ago, Xilinx sent a note to CoolRunner customers that certain older
CoolRunner would be discintinued, since the original fab will no longer make the
devices. Here is the URL of that note

http://www.xilinx.com/partinfo/notify/pdn0007.htm

All the newer members of the CoolRunner family are very much alive, and so is
the orignal design team, still located in Albuquerque as happy Xilinx employees,
working on the next generation CoolRunner.

To paraphrase Mark Twain:
The rumors of CoolRunner's death are highly exaggerated.

If you need CPLDs, CoolRunner is the way to go!

Peter Alfke


>

--------------5640F8382D41D79351968B74
Content-Type: text/html; charset=us-ascii
Content-Transfer-Encoding: 7bit

<!doctype html public "-//w3c//dtd html 4.0 transitional//en">
<html>
Seven month ago, Xilinx sent a note to CoolRunner customers that certain
older CoolRunner would be discintinued, since the original fab will no
longer make the devices. Here is the URL of that note
<p><u><A HREF="http://www.xilinx.com/partinfo/notify/pdn0007.htm">http://www.xilinx.com/partinfo/notify/pdn0007.htm</A></u>
<p>All the newer members of the CoolRunner family are very much alive,
and so is the orignal design team, still located in Albuquerque as happy
Xilinx employees, working on the next generation CoolRunner.
<p>To paraphrase Mark Twain:
<br>The rumors of CoolRunner's death are highly exaggerated.
<p>If you need CPLDs, CoolRunner is the way to go!
<p>Peter Alfke
<br>&nbsp;
<blockquote TYPE=CITE>&nbsp;</blockquote>
</html>

--------------5640F8382D41D79351968B74--


Article: 31466
Subject: Re: xilinx webpack problem
From: Gonzalo Arana <gonzaloa@sinectis.com.ar>
Date: Sat, 26 May 2001 09:16:21 -0300
Links: << >>  << T >>  << A >>
> > Just another question (if I may): why this code doesn't work?
> >
> >   contador: for i in 0 to 5 generate
> >      cntr0: if (i = 0) generate
> >         counter_rightest: counter port map (cuatro_ceros, cero, clock,
> >         borrows(i), uno, uno);
> >         cntr1to4: if (i > 0 and i < 5) generate
> >           counter_middle:   counter port map (cuatro_ceros, cero, clock,
> >           borrows(i), borrows(i-1), uno);
> >           cntr5: if (i = 5) generate
> >             counter_leftest:  counter port map (cuatro_ceros, cero, clock,
> >                  led, borrows(i-1), uno);
> >       end generate;
> > end behavioral;
> 
> What you're asking it to do doesn't make sense.  Your 'contador'
> statement looks fine.  Then, you only execute the lines after cntr0 if i
> is zero.  That means that the cntr1to4 line is only executed if i is 0.
> Which means that it is never 1 < i < 5.
> 
> Also, you do need an end generate for each generate statement.  You do
> not need to label your generate statments (label:), but ifyou do, you need
> an end label.
> 
> I think what you are trying to do is this:
> 
> ...
> begin
>   contador: for i in 0 to 5 generate
> 
>      cntr0: if (i = 0) generate
>         counter_rightest: counter port map (cuatro_ceros, cero, clock,
>              borrows(i), uno, uno);
>      end generate cntr0;
> 
>      cntr1to4: if (i > 0 and i < 5) generate
>         counter_middle:   counter port map (cuatro_ceros, cero, clock,
>              borrows(i), borrows(i-1), uno);
>      end generate cntr1to4;
> 
>      cntr5: if (i = 5) generate
>         counter_leftest:  counter port map (cuatro_ceros, cero, clock,
>              led, borrows(i-1), uno);
>      end generate cntr5;
> 
>   end generate contador;  -- You need the end label.
> end behavioral;
> 
> ... and what some people might find even more elegant:
> 
> ...
> 
>   --** I changed the size of this vector:
>   signal borrows : std_logic_vector(6 downto 0);
> begin
> 
>   borrows(0) <= '1';  --** Input to Counter #1
>   led <= borrows(6);  --** Output from Counter #6
> 
>   contador: for i in 0 to 5 generate
> 
>      counter:   counter port map (cuatro_ceros, cero, clock,
>              borrows(i+1), borrows(i), uno);
> 
>   end generate contador;  -- You need the end label.
> 
> end behavioral;
> 
> -- I get here the message: BEHAVIROAL simbol read,
> > GENERATE expected..
> 
> Because you wrote end behavioral, and it was still waiting for end generate.
> 
> >
> > As fas as I know (which turns to be really near -haha-) just one 'end
> > generate;' sentence is necesary (and another would be wrong).  Am I
> > right?
> 
> Nope.  You need an end generate for EVERY generate.  So in your
> case you needed 4.
> 
> > If I add another 'end generate;' sentence, WebPack gives me the same
> > message in the 'end behavioral;' line.
> 
> That's becase if you added one, you had two.  You needed 4!
> 
> > Hope I'm not abusing of your kidness (this must sound terrible in
> > english, sorry!).
> > Thank you very much again for your useful help and tips.
> 
> No problem at all.  Hope it helps.
> 
> -kent

Enlightning (spelling ok?)
Thank you very much again,

Gonzalo

Article: 31467
Subject: Re: free simulator
From: "Dave Feustel" <dfeustel@mindspring.com>
Date: Sat, 26 May 2001 12:39:08 -0500
Links: << >>  << T >>  << A >>
I had tried this a couple of times but I can't seem to get there from 'here'.
(I get dns/server error msg)

"Ray Andraka" <ray@andraka.com> wrote in message news:3B09A644.6F8725C6@andraka.com...
> http://www.aldec.com
>
> Dave Feustel wrote:
> >
> > What is the URL for Aldec?
> >




Article: 31468
Subject: The FAQ is Live and so is the Archive
From: Philip Freidin <philip@fliptronics.com>
Date: Sat, 26 May 2001 11:35:25 -0700
Links: << >>  << T >>  << A >>

The Archive and FAQ for comp.arch.fpga is up and running,
and now has beautiful threading and indexes thanks to the
tireless efforts of Jan Gray, and the pack-rat hoarding of old
articles by yours truly, and Markus Wannemacher.

The Google search engine has been added, and works,
although the pointers are still off by a little due to the delay
between the site data base being stabilized and the last time
the Google search engine/crawler indexed the site. This should
resolve itself in the near future.

Most importantly, the first donated FAQ page has been received
and published. You can see it in all its glory at:

     http://www.fpga-faq.com/FAQ_Pages/0014_Xilinx_vs_Altera.htm

THANKS Martin Thompson !!!

I am sure this will inspire most of you to contribute your own donation to
this site.

Here's how:

1) Send me some email letting me know you are going to write a page
    on your favorite topic. If it collides with someone elses pending work
   I will let you know. If you dont have a favorite topic of your own, go
   to the archive, find an interesting thread, and edit it into an interesting
   FAQ page (remember to acknowledge the original authors).

2) Go to the site and download the template page at:

            http://www.fpga-faq.com/FAQ_Pages/FAQ_Entry_template.htm

  (select the above link in your browser, download it to your machine,
  edit it till it has good content, send it to me. See Martin's FAQ page 0014
  as an excelent example of what can be done!)

3) Using your favorite editor, write an FAQ page. For example, VI, emacs,
    edlin, ultraedit, netscape composer, ....... see, lots of choices

4) send it to me for publication.

NOTE that the archive is itself an excelent source of material, and you
may of course use links to the archive in your FAQ pages. Unless something
horrible happens, the archive, and it article pages and article numbers will
remain static, so for instance, 

    http://www.fpga-faq.com/archives/02450.html#2450

should always select the same article, even as new articles are added to
the archive.

The articles are linked with a line looks like:

       Links: << >>  << T >>  << A >> 

Is this obvious in its intent or should there be some help to explain how
to use it?

Search, Read, and Enjoy

(on a more personal note, I missed the last episode of
    3rd Rock from the Sun . If anyone has this recorded, and could lend
it to me, I would be most grateful ! )

Philip Freidin

===================
Philip Freidin
philip@fliptronics.com
Host for WWW.FPGA-FAQ.COM

Article: 31469
Subject: Xilinx XC4010E Problem
From: Henning Trispel <h_trispel@comundo.de>
Date: Sat, 26 May 2001 20:44:23 +0200
Links: << >>  << T >>  << A >>
Hello,

I had to do some changes in an earlier design using a XC4010E-4 device.
The design is a fully synchronous design using a single 8 MHz clock, all
transitions are sampled on rising clock edge. The design controls a CPU
access to a FIFO (hosted on a MVME IP-bus). 

In my simulations - functional as well as timing - the design works as
required. However, in real world, the FPGA outputs are mostly correct,
but partly false. Even bits, which are defined as constant low, are
sometimes high. This phenomenon is different for each compilation / PROM
version, but within that version 100% reproducable. There is no obvious
timing problem, since I measured the setup/holds with fast scope.

My only clue right now is that my configuration PROM - a XC1701 device -
does not contain what it should. (I use the 1Mbits, since I have still
plenty of these, while I have only three 256k PROMs left). Workflow:
Compilation -> Creation of a MCS86 prom file -> reading the design using
my HiLo-Programmer (as Intel-Hex, unused bytes set to 0) -> burn

When I view the programming data loaded into the programmer, the data
seem correct (I checked the first dozen bytes - but not all). I am using
the 3.1i Xilinx foundation software. (BTW can anybody tell me why the
heck the timing for a >3 year old FPGA is "prelimanary" in the FND3.1i?)

Right now I can't believe that the simulated timing is so much off the
real behaviour. And a 8 MHz synchronous design should be that big of a
deal anyway. (Usage is 80% of the CLBs, the design contains mainly three
one-hot-state state machines).

Any hints or help is highly welcome. 

Thank you,

Henning Trispel

Article: 31470
Subject: Internal tri states
From: Jamil Khatib <khatib@ieee.org>
Date: Sat, 26 May 2001 23:03:52 +0200
Links: << >>  << T >>  << A >>
Is there any drawbacks for using internal tristate buffers to implement
busses? or should I keep using muxs?

Thanks
Jamil


Article: 31471
Subject: Re: Xilinx XC4010E Problem
From: Peter Alfke <palfke@earthlink.net>
Date: Sun, 27 May 2001 01:57:06 GMT
Links: << >>  << T >>  << A >>
Here is one wild guess, triggered by your words "one-hot state machines"

You might have a problem at the end of configuration, at start-up. I have
often described this as a complicated step, analoguous to a baby being
born, changing from one oxygen-supply system to another. It takes a
doctor's defty clap so synchronize things...
In your case, you have CCLK doing the configuring, then your ( I assume
totally unrelated ) user clock takes over, and inow the global reset that
kept everything quiet during configuration gets released. But that release
is not instantaneous. It is a signal travelling all over the chip, and it
may take 30 ns to do so. In the meantime your clock is clocking all over
the chip. Things could get messed up.

The best cure is to give the state machine bits their own extra,
longer-lasting reset that is synchronously controlled by your user clock.
Just use a 2-bit shift register for that, so you stretch global reset, and
it ends in a proper synchronous fashion.

As I said, just a wild guess, but it has worked before...

Alles Gute und viel Erfolg !
Peter Alfke, Xilinx Applications
=========================================
Henning Trispel wrote:

> Hello,
>
> I had to do some changes in an earlier design using a XC4010E-4 device.
> The design is a fully synchronous design using a single 8 MHz clock, all
> transitions are sampled on rising clock edge. The design controls a CPU
> access to a FIFO (hosted on a MVME IP-bus).
>
> In my simulations - functional as well as timing - the design works as
> required. However, in real world, the FPGA outputs are mostly correct,
> but partly false. Even bits, which are defined as constant low, are
> sometimes high. This phenomenon is different for each compilation / PROM
> version, but within that version 100% reproducable. There is no obvious
> timing problem, since I measured the setup/holds with fast scope.
>
> My only clue right now is that my configuration PROM - a XC1701 device -
> does not contain what it should. (I use the 1Mbits, since I have still
> plenty of these, while I have only three 256k PROMs left). Workflow:
> Compilation -> Creation of a MCS86 prom file -> reading the design using
> my HiLo-Programmer (as Intel-Hex, unused bytes set to 0) -> burn
>
> When I view the programming data loaded into the programmer, the data
> seem correct (I checked the first dozen bytes - but not all). I am using
> the 3.1i Xilinx foundation software. (BTW can anybody tell me why the
> heck the timing for a >3 year old FPGA is "prelimanary" in the FND3.1i?)
>
> Right now I can't believe that the simulated timing is so much off the
> real behaviour. And a 8 MHz synchronous design should be that big of a
> deal anyway. (Usage is 80% of the CLBs, the design contains mainly three
> one-hot-state state machines).
>
> Any hints or help is highly welcome.
>
> Thank you,
>
> Henning Trispel


Article: 31472
Subject: Re: Internal tri states
From: Peter Alfke <palfke@earthlink.net>
Date: Sun, 27 May 2001 02:06:38 GMT
Links: << >>  << T >>  << A >>
Internal 3-states are great, but:

If you use the longline with resistive pull-up, (DTL-fashion, wired AND)
it is very safe, but slow.
If you switch between active drivers, you are responsible for making sure
that only one driver is on at any one time, otherwise you get contention.
The drivers are deliberately designed to be faster in turn-off than in
turn-on, so if you think you have a seemless change, there actually is a
small idle time between the two drivers being active. Good! Short
contentions are not destrucive, but generate a lot of noise, and
unnecassary power consumption.
On very large chips, the longlines represent a lot of capacitance, that's
why Virtex implements 3-state buffering differently.

Peter Alfke
==================================
Jamil Khatib wrote:

> Is there any drawbacks for using internal tristate buffers to implement
> busses? or should I keep using muxs?
>
> Thanks
> Jamil


Article: 31473
Subject: JPEG cores
From: "James Brennan" <mailjamesnow@yahoo.com.au>
Date: Sun, 27 May 2001 15:22:52 +1000
Links: << >>  << T >>  << A >>
A bit of a general request: I'm looking for some free VHDL source of a JPEG
encoder and/or decoder. Does anyone know of some available VHDL source in
this regard? It doesn't have to implement *everything* in the JPEG standard,
just the basic functionality.

Thanks,

James.



Article: 31474
Subject: Re: Xilinx XC4010E Problem
From: Peter Alfke <palfke@earthlink.net>
Date: Sun, 27 May 2001 06:02:47 GMT
Links: << >>  << T >>  << A >>
Henning,
I think I have a simpler solution that does not require any redesign.
My previous suggestion is appropriate for very high clock rates, 100 MHz and
more.
(Most of our activity these days is with 100 to 500 MHz clocks...)
For a  slow clock, you only need to synchronize the start-up to your clock,
the "user clock", and you do that by invoking the UCLK_NOSYNC option, as
descibed in the XC4000 data sheet, page 6-53, figure 47. The same figure is
also shown in some XAPP notes on configuration.  I wrote that stuff, so get
back to me if there are questions...

Again, this is a wild guess...

Gruß
Peter Alfke, Xilinx Applications

(Xilinx is mainly shut down for the whole of next week, but this is my home
e-mail address , and I'll be there )

Peter Alfke wrote:

> Here is one wild guess, triggered by your words "one-hot state machines"
>
> You might have a problem at the end of configuration, at start-up. I have
> often described this as a complicated step, analoguous to a baby being
> born, changing from one oxygen-supply system to another. It takes a
> doctor's defty clap so synchronize things...
> In your case, you have CCLK doing the configuring, then your ( I assume
> totally unrelated ) user clock takes over, and inow the global reset that
> kept everything quiet during configuration gets released. But that release
> is not instantaneous. It is a signal travelling all over the chip, and it
> may take 30 ns to do so. In the meantime your clock is clocking all over
> the chip. Things could get messed up.
>
> The best cure is to give the state machine bits their own extra,
> longer-lasting reset that is synchronously controlled by your user clock.
> Just use a 2-bit shift register for that, so you stretch global reset, and
> it ends in a proper synchronous fashion.
>
> As I said, just a wild guess, but it has worked before...
>
> Alles Gute und viel Erfolg !
> Peter Alfke, Xilinx Applications
> =========================================
> Henning Trispel wrote:
>
> > Hello,
> >
> > I had to do some changes in an earlier design using a XC4010E-4 device.
> > The design is a fully synchronous design using a single 8 MHz clock, all
> > transitions are sampled on rising clock edge. The design controls a CPU
> > access to a FIFO (hosted on a MVME IP-bus).
> >
> > In my simulations - functional as well as timing - the design works as
> > required. However, in real world, the FPGA outputs are mostly correct,
> > but partly false. Even bits, which are defined as constant low, are
> > sometimes high. This phenomenon is different for each compilation / PROM
> > version, but within that version 100% reproducable. There is no obvious
> > timing problem, since I measured the setup/holds with fast scope.
> >
> > My only clue right now is that my configuration PROM - a XC1701 device -
> > does not contain what it should. (I use the 1Mbits, since I have still
> > plenty of these, while I have only three 256k PROMs left). Workflow:
> > Compilation -> Creation of a MCS86 prom file -> reading the design using
> > my HiLo-Programmer (as Intel-Hex, unused bytes set to 0) -> burn
> >
> > When I view the programming data loaded into the programmer, the data
> > seem correct (I checked the first dozen bytes - but not all). I am using
> > the 3.1i Xilinx foundation software. (BTW can anybody tell me why the
> > heck the timing for a >3 year old FPGA is "prelimanary" in the FND3.1i?)
> >
> > Right now I can't believe that the simulated timing is so much off the
> > real behaviour. And a 8 MHz synchronous design should be that big of a
> > deal anyway. (Usage is 80% of the CLBs, the design contains mainly three
> > one-hot-state state machines).
> >
> > Any hints or help is highly welcome.
> >
> > Thank you,
> >
> > Henning Trispel




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