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Messages from 31575

Article: 31575
Subject: RLOC'in Virtex-II FDCs???
From: muzaffer@dspia.com
Date: Wed, 30 May 2001 17:26:32 +0100
Links: << >>  << T >>  << A >>
hi,
has anyone done any work on virtex-ii FDC RLOCs ? I think the same
issue applies to Virtex too. How do you control the location of an FDC
in a slice? There are two FDCs per slice and I can't seem to get lsb
of a register to be assigned lower than the second bit. If I RLOC a
number of bits, the floorplan gets (u1, u0), (u3, u2) etc. Any ideas
how to get (u0, u1), (u2, u3) ? (all in ascending order.)

Muzaffer



Article: 31576
Subject: Re: Fragen zu PCI und FPGA
From: T-Online <Mario.Heike.Niklas@t-online.de>
Date: Wed, 30 May 2001 19:53:08 +0200
Links: << >>  << T >>  << A >>
Danke für die Tipps.
Problem ist mehr das VHDL-Design um über den PCI-Bus (und damit über 9052) das
Auslesen des Speichers vorzubereiten.

Mario


Kevin Neilson schrieb:

> Alles klar.  Am einfachsten is ein dual-port SRAM zu benutzen.  An dieser
> Weise darf die FPGA die Daten an einer Seite (Port) das dual-port SRAM
> liefern.  Die andere Seite (Port) des SRAMs waere direkt mit 9052
> angeschlossen.  Es ist also nicht noetig, ein kompliziert Anschluss zwischen
> FPGA und 9052 machen.  Diese dual-port SRAM darf ausserlich sein, oder
> besser, wenn sie nicht so viel SRAM brauchen, durfen Sie z.B. Xilinx
> blockRAM benutzen.
>
> -Kevin
>
> "T-Online" <Mario.Heike.Niklas@t-online.de> wrote in message
> news:3B1490F8.8E645D42@t-online.de...
> > Danke für ihr Interesse !
> > An dem FPGA ist ein Lasersensorkopf angeschlossen der daten liefert. Diese
> > Daten werden über das FPGA in das SRAM geschrieben. Dort möchte ich diese
> Daten
> > mit den beschriebenen Bausteinen auslesen. Dabei geht es nicht um die
> Software
> > die den PCI-Bus ansteuert, sondern nur um das FPGA-Design.
> >
> > Mario
> >
> > Kevin Neilson schrieb:
> >
> > > Mario,
> > > Etwas ist nicht klar.  Warum brauchen sie ein FPGA?  Der 9052 hat
> Lokal-Bus
> > > fuer Lokal-Speicher.  Koennen Sie nicht direkt die SRAM mit dem 9052
> > > anbinden?  Das waere einfacher.  Man braucht viellecht noch eine
> Processor,
> > > der 9052 zu programmieren.
> > > -Kevin
> > >
> > > "T-Online" <Mario.Heike.Niklas@t-online.de> wrote in message
> > > news:3B109F88.356B08B7@t-online.de...
> > > > Wer hat Erfahrung mit der Anbindung eines FPGA auf einem PCI - Board
> an
> > > > den PCI - Bus. Dazu benutze ich den PLX Baustein PCI 9052. Ich möchte
> > > > einen SRAM, das mit dem FPGA verbunden ist über den PCI -Bus auslesen.
> > > > Wer hat Tipps oder auch Beispielprogramme in VHDL die dieses
> > > > bewerkstelligen. Worauf muss ich beim programmieren des FPGA achten.
> > > >
> > > > Danke
> > > >
> > > > Mario Giffel
> > > >
> > > >
> >
> >


Article: 31577
Subject: Foundation 3.3i memory useage
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Wed, 30 May 2001 20:06:59 +0100
Links: << >>  << T >>  << A >>

I've just started playing with the F3.3i eval kit & have found it, +SP8,
to be much faster & to produce better results than 2.1i *BUT* PAR memory
useage has gone up by ~50% for exactly the same design! I don't know if
there's a warning anywhere about this but I would suggest this warning
label on the CD sleeve:

Before Installation: Go buy more memory, and we mean *LOTS* more. If
your PC's motherboard doesn't support large amounts of DRAM then go buy
a new  motherboard.

Note to Xilinx [#437 in the series ``please give us Linux'']: This sort
of thing would not be too bad running under Linux which has reasonably
efficient swapping but NT's performance plummets like a brick through a
greenhouse roof as soon as it starts to swap. Don't know if Win2K is any
better in the respect.




Article: 31578
Subject: Re: Help: RAM clear in one clock cycle
From: eteam <eteam@aracnet.com>
Date: Wed, 30 May 2001 12:14:05 -0700
Links: << >>  << T >>  << A >>
Plan B:

The famous "dirty" cache tag trick... keep a single-bit scoreboard
of each ram address that marks each address as "written" (aka "dirty) or not.
While accessing the ram, access the scoreboard.  If a read access, and the
scoreboard shows the address as unwritten, then return a '0' for the read data.
If a write access, then set the scoreboard bit associated with the address,
marking the address as "dirty".

Of course, this means that the scoreboard must be cleared in a single cycle.

Here's plan C:

This is very similar to plan B (the scoreboard thing) except:
Instead of using a single-bit "dirty" tag, use an N-bit "dirty" tag.
Add an N-bit counter, this will be your secret decoder key.  Every time you
need to "clear" the RAM buffer, increment the key count.  For every read access,
compare the tag array content with the current key value. If they don't match,
then the corresponding RAM buffer is "unwritten", and a read access should
return a 0 data value.  (note: while you're returning a '0' value, you might also
want to write a '0' into the location being read, and update the tag to the
current key value)  If the tag key matches the current key, the ram address is
"dirty" and may be read normally.  If the ram buffer access is a write, then
store the current key in the corresponding tag store location.

Basically this is the same as plan B with an added N-bit comparison to validate
a ram address read.

If you're guaranteed to access *every* ram location at least once between
"clear" operations, then the key need be only a 1-bit value.  Life should be this
simple!  If not, then preventing key matches to stale tag keys must be added
to the logic (see below).

In order to guarantee that the current key value doesn't wrap around to match
a "stale" key in the tag, you have to provide a "background" mechanism to
clear the ram (or the tag array) in less time than a "key wrap" can occur.

In spare cycles, go through the tag store and clear each ram location to '0'
*if* its corresponding tag value doesn't already match the current key value.
This gives you (N-1) * M cycles in which to clear the ram array, where N is the
number of possible valid keys and M is the number of cycles between "ram clear"
commands.
 

Here's plan D:

This works if the time between "clears" is at least N cycles, where N is the
word depth of the ram buffer.

Maintain two copies of the ram buffer, with a state bit enabling one copy or
the other.  While buffer A is enabled and being accessed normally, buffer B
is being cleared.  When the "CLEAR RAM" command is invoked, simply toggle the
state bit which selects buffer A vs. buffer B.

There are lots of variations on this theme, addressing all sorts of nuances.
A survey of mainframe cache coherency and write-back schemes is in order.
This should be in the ancient history section of the computer science library :=)

Good luck, and may the force be with you!

Bob Elkind, the e-team, consulting FPGA/ASIC design
eteam@aracnet.com


Ray Andraka wrote:
> 
> I hope it is a small block.  You'll have to implement the RAM as an array of
> flip-flops to get the single cycle clear.  The block RAMs and CLB RAMs do not
> have a clear input, so they cannot be cleared in a single cycle.  If the access
> is in a known pattern however, you can fake it by gating the read data until the
> RAM has been re-written.
> 
> Huang wrote:
> >
> > Hi all,
> >
> > I just got a design document from system architect, and found something
> > unusual: A BLOCK of RAM is cleared in one clock cycle.
> >
> > Can anyone tell me how to implement RAM in FPGA that can be cleared in this
> > way?
> >
> > Thanks
> 
> --
> -Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930     Fax 401/884-7950
> email ray@andraka.com
> http://www.andraka.com

Article: 31579
Subject: Re: Help: RAM clear in one clock cycle
From: John_H <johnhandwork@mail.com>
Date: Wed, 30 May 2001 22:27:21 GMT
Links: << >>  << T >>  << A >>
The most effecient way to clear a block of RAM:  find an FPGA that offers that
functionality... I haven't seen one.

The next best thing appropriate for small RAMs:  implement the RAMs as
registers.  Some synthesizers let you infer RAMs.  If the architecture allows
RAMs that don't have a single cycle clear but one is specified in the code, the
result should be an array of registers.

Big RAMs?  Popular FPGAs?  Get new specs.

Synplicity's synthesizer performs pretty well for proper RAM inference in my
Xilinx designs as of late.

- John


Huang wrote:

> Hi all,
>
> I just got a design document from system architect, and found something
> unusual: A BLOCK of RAM is cleared in one clock cycle.
>
> Can anyone tell me how to implement RAM in FPGA that can be cleared in this
> way?
>
> Thanks


Article: 31580
Subject: Help on Xilinx 6200
From: Kuan Zhou <zhouk@rpi.edu>
Date: Wed, 30 May 2001 18:32:20 -0400
Links: << >>  << T >>  << A >>
Hi,
   I am a guy who is looking at the performance of 
the Xilinx 6200 chips.
   When I download the compiled bit streams into 
Xilinx 6200 chip,Is there any tool or file for me to
easily tell how the circirts are mapped  in the 
Xilinx 6200 chip?I want to know the functions
of each CLB in the chip during the application.
   Is there any data sheet describing that?


sincerely
-------------
Kuan Zhou




Article: 31581
Subject: Barrel shifter in Xilinx Virtex-E
From: Jean-Paul Smeets <jpsmeets@xs4all.nl>
Date: Thu, 31 May 2001 00:45:37 +0200
Links: << >>  << T >>  << A >>
Hi,

I have just finished a CPU in which the shift/logical ALU is the
critical path.

The shift ALU is 16 bits wide and implements SLL, SRL, SRA, ROL and
ROR over 0..15 positions.

Usign the following equivalences:
a ROR b= = a ROL (16 - b)
a SLL b == (a ROL b) AND (X"FFFF" SLL b)
a SRL b == (a ROL (16 - b))  AND (X"FFFF" SRL b)
ar == (others => a(15)
a SRA b == ((a ROL (16 - b))  AND (X"FFFF" SRL b)) OR (ar AND (X"FFFF"
SRL b))

Note: X"FFFF" SLL b is generated by 16x16 ROM

The basic architecture is 
stage 1:ROL 0,4,8,12
stage 2: ROL 0,1,2,3
stage 3A: AND with mask (SLL and SRL)
stage 3B: AND with mask OR with replicated MSB (SRA)

In a Virtex-E this requires about 15ns, which is too slow.

Any ideas for speeding this up?



J.P. Smeets
business:
Ellips
Woenselsestr 352A
5623 EG Eindhoven
tel: +31-40-2456540
fax: +31-40-2467183
email: jeanpaul@ellips.nl
home:
Loondermolen 23
5612 MH Eindhoven
tel: +31-40-2465105
email: jpsmeets@xs4all.nl

Article: 31582
Subject: Re: Is anybody using FPGAs for scientific computing?
From: "Tim" <tim@rockylogic.com.spamtrap>
Date: Wed, 30 May 2001 23:55:42 +0100
Links: << >>  << T >>  << A >>
Look at SRC computers, the latest in the Cray lineage.

A problem may be that they are pretty secretive over results.

Also, check the archives for thsi group.

Roberto R. Osorio wrote in message <3B14EAD0.1CBDF5E8@imec.be>...
>This is just a question.
>
>Is anybody using FPGAs to execute scientific programs?
>Is it possible to find small cores in the programs that can
>be mapped onto a FPGA and obtain good speed-up?
>Which is the main problem, computing or IO bandwidth?
>
>If you are doing that, which are the results? Which kind
>of programs are you focused in: optimization, genetics,
>matrix computation, simulation, weather forecast...?
>






Article: 31583
Subject: IEEE VHDL library support in HDL compilers
From: Kris Nichols <knichols@uoguelph.ca>
Date: Wed, 30 May 2001 23:14:51 GMT
Links: << >>  << T >>  << A >>
Hey,
    I have a few concerns with regards to support for the IEEE VHDL
libraries in HDL compilers.  I'm currently using Synopsys FPGA Express
v3.3 (that comes with Xilinx Foundation 2.1i), and have found that this
compiler does not support the 'math_real' IEEE library for real (i.e.
floating point) numbers, or the divide "/" function from the
'numeric_std' IEEE library.  I was wondering if anyone knows if current
versions of Synopsys FPGA Compiler II or Synopsys FPGA Express have
support for these libraries?  Does the Xilinx XST Compiler support these
libraries?  What other professional HDL compilers are offered, which
provide this kind of support?  If these libraries aren't yet supported
in any compilers, why is this the case?  Thanks for your time.

Kris Nichols
School of Engineering
University of Guelph
Guelph, Ontario
Canada


Article: 31584
Subject: Re: [Q]setup-time violation
From: Paul Campbell <paul@verifarm.com>
Date: Wed, 30 May 2001 23:20:35 +0000
Links: << >>  << T >>  << A >>
Ben wrote:

> Hi,
> 
> I use two independent clocks and an asynchronous fifo from synopsys
> DesignWare in my design.
> This means there is frequent data transfer between the clock domains.
> During the simulation, a fliflop which gets signal from another flipflop
> of different clock domain generated setup time violation error.
> The flipflop must be some kind of synchronizer for internal control of
> fifo. I think this kind of error is ubiquitous for 2-clock design or any
> design that has synchronizer for asynchronus signal in it, and believe
> that there is some technique which will prevent or bypass timing error
> during simulation. 

yup you're right - it's common to use a special cell for these sorts of 
synchronizers - one that is more metastability resistant - its verilog 
model is usually without setup/hold checks and a long clk->Q. The synopsys 
version of the cell also usually has a long clk->Q and you need to set a 
false path to its input (make sure its input is only driven directly from a 
single flop in the other domain - no combinatorial logic that can make the 
chance of metastability higher)

        Paul 

Article: 31585
Subject: fct logic and xc4000xl inputs
From: "Chuck Woodring" <woodringfam@earthlink.net>
Date: Thu, 31 May 2001 01:00:14 GMT
Links: << >>  << T >>  << A >>
I am building a FPDP interface in a XC4000xl chip, but the FPDP spec calls
out specific FCT logic for the interface.  The 20 MHz TTL strobe calls for a
FCT806A clock driver from IDT and the DVALID and SYNC signals use a FCT15962
?? 16 bit register chip.

    I was hoping to bring the FPDP strobe and control signals directly into
the FPGA.  Is this unrealistic?  I have terminated the strobe as called for
220 to VCC and 330 to gnd.  My card is only a Receiver or Receiver master
but I am sending back the SUSPEND and NRDY signals.

I have a XESS proto card with the interface programmed in but when I look at
the signal they look pretty distorted.  The strobe actually looks ok but the
DATA VALID is shakey at best.  I am unsure if it is the protocard grounding
or the fact that I haven't used the chips called for in the spec?

Any help/thoughts appreciated.

Thanks

Chuck



Article: 31586
Subject: Re: Fun with DLLs.
From: Kent Orthner <korthner@hotmail.nospam.com>
Date: 31 May 2001 10:09:42 +0900
Links: << >>  << T >>  << A >>


> Allan Herriman wrote:
> > Hi Kent,
> >
> > Is that "nominally 52MHz" clock really 51.840MHz?  If it's being used
> > for SONET/SDH timing, there are all sorts of restrictions regarding the
> > rate of change of frequency, and the size of phase hits, etc.
> >
> > Implementing SONET/SDH clock switching is non-trivial.

Nope.  The 52 MHz clock really is 52.000 +/- 100ppm.  The main project I'm 
working on right now is a SONET framer, and I agree that the SONET/SDH clock 
requirements are a headache!

-Kent

Article: 31587
Subject: Re: Help: RAM clear in one clock cycle
From: "Huang" <xyhuang@sc.mcel.mot.com>
Date: Thu, 31 May 2001 09:35:07 +0800
Links: << >>  << T >>  << A >>
Thank you all for your replies.

The architecture design was done in behavior C, so the system architect can
clear blocks of RAM in one cycle.
I knew it's not reasonable to clear a LARGE block ram( >200K) in one cycle,
but my system architect seems didn't think so, he told me that on-chip RAM
block has a special CLEAR pin!

The purpose for me to ask question in newsgroup is to affirm my idea. Now it
does.

In my daily work, I saw too many stupid design by those Ph.Ds w/o practical
engineering experience! What can I do? Those guys don't like negative
feedback.

I hope this story will not happen to others.

Huang <xyhuang@sc.mcel.mot.com> wrote in message
news:9f2bce$2kv$1@newshost.mot.com...
> Hi all,
>
> I just got a design document from system architect, and found something
> unusual: A BLOCK of RAM is cleared in one clock cycle.
>
> Can anyone tell me how to implement RAM in FPGA that can be cleared in
this
> way?
>
> Thanks
>
>
>
>



Article: 31588
Subject: PAD to PAD Timing Constraints. (Xilinx)
From: Kent Orthner <korthner@hotmail.nospam.com>
Date: 31 May 2001 10:54:53 +0900
Links: << >>  << T >>  << A >>
Hi, guys.

Does anyone know of a way to specify a timing constraint on 
a path from an input pad, maybe thrught a CLB, maybe not, to
an output pad?  ie. a simple propogation delay?

All of the timing constraints I can find seem to be referenced to 
a clock.

Note:  Using Xilinx Spartan-II, ISE 3.3i SP8.

Thanks in advance.
-Kent

Article: 31589
Subject: Re: Fun with DLLs.
From: Allan Herriman <allan_herriman.hates.spam@agilent.com>
Date: Thu, 31 May 2001 12:34:35 +1000
Links: << >>  << T >>  << A >>
Austin Lesea wrote:
> 
> Allan,
> 
> I second that.
> 
> I worked for a company that build BITS clocks for SONET, and the switchover was
> not a pretty spec.  You could move less than X ns in y ms, which led to PLL's
> with poles at > 0.1 Hz.  This led to really bad short term stability problems
> from the PLL having such a terrible and slow response time.
> 
> If I had it to do over again, I would use a synthesizer running at 300 MHz to
> synthesize the 51.84 MHz (a digital locked loop with the A or B 51.85 as a
> reference input to be tracked), and then digitally slew the DDFS synthesizer
> from one frequency to the other.  I would then remove the synthesis jitter with
> a PLL following.

Hi Austin,

Since you need an analog PLL following the digital frequency
synthesiser, you can digitally synthesise a much lower frequency, and
multiply up in the PLL.  This is much easier to do, and saves power
without compromising performance (if designed properly, of course).
I believe that's the way the commercial ASICs work.  E.g. that Semtech
chip I mentioned used a 12.8MHz reference osc.  I designed one once that
used 20.0MHz as the reference clock for the NCO.
The trick is to choose the reference frequency such that the jitter you
get from sampling the various other frequencies doesn't alias close to
DC (where it can't be filtered out by the DPLL).

Regards,
Allan.

Article: 31590
Subject: Re: FPGA consultant needed
From: "Austin Franklin" <austin@dar54kroom.com>
Date: Wed, 30 May 2001 22:40:48 -0400
Links: << >>  << T >>  << A >>
> > > The legal strategy seems to be mostly about spreading confusion
amongst
> > the
> > > jury.  I gather the trial was something like this:  "Look at the
Xilinx.
> > It
> > > has lookup tables.  Look at the Altera.  What do we see?  Lookup
tables!
> > > A-ha!"
> >
> > That is, of course, completely ridiculous.  The "strategy" is to explain
> > things to the jury in such a way that they understand it, and can reach
a
> > fair decision.  I take it you have no first hand knowledge of how cases
> like
> > this work, or I don't believe you'd be saying this.
> >
> >
> So you are saying that lawyers attempt to present juries unbiased
> statistical facts so that they can come to a just, fair, conclusion.  I
had
> the notion they used subterfuge and emotion to win at all costs.  I must
be
> very naive about the legal system.

I can only guess you watch too much TV, and have not been actually involved
in any patent related court cases.









Article: 31591
Subject: Xilinx on Linux Howto Updated
From: bjrosen@polybus.com (B. Joshua Rosen)
Date: 30 May 2001 19:42:05 -0700
Links: << >>  << T >>  << A >>
The Xilinx on Linux HowTo page has been updated. 

http://www.polybus.com/xilinx_on_linux.html

Article: 31592
Subject: Re: Help: RAM clear in one clock cycle
From: Ray Andraka <ray@andraka.com>
Date: Thu, 31 May 2001 03:34:29 GMT
Links: << >>  << T >>  << A >>
Don't feel bad.  It happens more than you might think, although I don't think
I've had a systems guy pull the 'clear the whole memory in a clock' stunt on me
yet.  Most often algorithms that are supposedly targeted to hardware that are
done in double precision floating point.

Huang wrote:
> 
> Thank you all for your replies.
> 
> The architecture design was done in behavior C, so the system architect can
> clear blocks of RAM in one cycle.
> I knew it's not reasonable to clear a LARGE block ram( >200K) in one cycle,
> but my system architect seems didn't think so, he told me that on-chip RAM
> block has a special CLEAR pin!
> 
> The purpose for me to ask question in newsgroup is to affirm my idea. Now it
> does.
> 
> In my daily work, I saw too many stupid design by those Ph.Ds w/o practical
> engineering experience! What can I do? Those guys don't like negative
> feedback.
> 
> I hope this story will not happen to others.
> 
> Huang <xyhuang@sc.mcel.mot.com> wrote in message
> news:9f2bce$2kv$1@newshost.mot.com...
> > Hi all,
> >
> > I just got a design document from system architect, and found something
> > unusual: A BLOCK of RAM is cleared in one clock cycle.
> >
> > Can anyone tell me how to implement RAM in FPGA that can be cleared in
> this
> > way?
> >
> > Thanks
> >
> >
> >
> >

-- 
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com

Article: 31593
Subject: Re: RLOC'in Virtex-II FDCs???
From: Ray Andraka <ray@andraka.com>
Date: Thu, 31 May 2001 03:48:34 GMT
Links: << >>  << T >>  << A >>
Yes,  you need to add BEL attributes.  Unfortunately, the syntax is very
clunky.  I liked the extensions on the RLOCs that they used for the 4K much more
(and even those were not that great).

	
for the luts:
attribute BEL of U1:label is "F";
attribute BEL of U2:label is "G";

for the xorcy's:
attribute BEL of U3:label is "XORF";
attribute BEL of U4:label is "XORG";

and for the ff's:
attribute BEL of U5:label is "FFX";
attribute BEL of U6:label is "FFY";

Note that even without the RLOCs, putting them in the correct way with the
floorplanner, then iterating the design and reopening the floorplanner, you'll
find that they get turned upside-down.  This is a flaw that I've complained to
xilinx about on and off for over two years.  The BELs will prevent it, but they
are a PITA to use.

The only place it is a real problem is when you have RLOC'd carry chains because
it scrambles the carry chains, which then causes the placer to complain.  



muzaffer@dspia.com wrote:
> 
> hi,
> has anyone done any work on virtex-ii FDC RLOCs ? I think the same
> issue applies to Virtex too. How do you control the location of an FDC
> in a slice? There are two FDCs per slice and I can't seem to get lsb
> of a register to be assigned lower than the second bit. If I RLOC a
> number of bits, the floorplan gets (u1, u0), (u3, u2) etc. Any ideas
> how to get (u0, u1), (u2, u3) ? (all in ascending order.)
> 
> Muzaffer

-- 
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com

Article: 31594
Subject: [Q]setup-time violation
From: "Ben" <ejhong@future.co.kr>
Date: Thu, 31 May 2001 05:46:39 GMT
Links: << >>  << T >>  << A >>
Hi,

I use two independent clocks and an asynchronous fifo from synopsys
DesignWare in my design.
This means there is frequent data transfer between the clock domains.
During the simulation, a fliflop which gets signal from another flipflop of
different clock domain generated setup time violation error.
The flipflop must be some kind of synchronizer for internal control of fifo.
I think this kind of error is ubiquitous for 2-clock design or any design
that has synchronizer for asynchronus signal in it, and believe that there
is some technique which will prevent or bypass timing error during
simulation.
Please help me out of this problem.

Thanks,

Ben



Article: 31595
Subject: Re: [Q]setup-time violation
From: Kent Orthner <korthner@hotmail.nospam.com>
Date: 31 May 2001 15:11:26 +0900
Links: << >>  << T >>  << A >>
Hi, Ben.

Peter Alfke from Xilinx has covered this topic in a number 
of App notes.  I suggest that you take a look at the following:

http://www.xilinx.com/xapp/xapp051.pdf
http://www.xilinx.com/xapp/xapp175.pdf

You may wlaso want to look at the following for some metastbility theory.

http://www.ednmag.com/ednmag/reg/1994/062394/13df2.htm

-Kent


Article: 31596
Subject: PowerPC?
From: "Anthony Ellis" <xxxa.ellis@logicworks.co.za>
Date: Thu, 31 May 2001 08:14:47 +0200
Links: << >>  << T >>  << A >>
Anyone know where I can get a VHDL  bus interface model (functional only)
for a PowerPC 603E. I need such for use in a test bench.
Thanks Anthony




Article: 31597
Subject: EPC2: no output signals
From: Chatillon.tecdis@st.com (Alessandro Patalani)
Date: Thu, 31 May 2001 07:08:07 +0000 (UTC)
Links: << >>  << T >>  << A >>
I have a problem with the configuration of a 4 Altera Flex 10K20 Board
being programmed by means of  an EPC2 connected  to a BitBlaster cable.
To build the board I have followed the scheme on the Altera Application
Note 116, pag. 55, fig 29, but this seems not to work. We tried to
program the EPC2 using Max+Plus II Programmer trasferring a .pof file
(built on the 4 .sof files) specifically targeted to EPC2TC32. We are
not able to observe any output signal from the EPC2. The error message
displayed by the Programmer is "Unrecognizable devide". We are using 5V
for the Vpp and Vcc, having tied both Vppsel and Vccsel pins to GND like

the Application Note suggested.
Have anyone had the same problem? Can anyone help me to understand where

is the problem?

Thank you in advance.

Alessandro



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Article: 31598
Subject: Re: IEEE VHDL library support in HDL compilers
From: Renaud Pacalet <pacalet@enst.fr>
Date: Thu, 31 May 2001 09:10:51 +0200
Links: << >>  << T >>  << A >>
Kris Nichols a écrit :
> 
> Hey,
>     I have a few concerns with regards to support for the IEEE VHDL
> libraries in HDL compilers.

Hi Kris,

First of all "compiler" is an ambiguous word. For most software
people and for some hardware it's a tool that converts a source
code (C, C++, Java, VHDL, Verilog, etc) in a binary object code
that is in turn converted in executable form by a linker. So it
leads to simulation. For some hardware guys it means synthesizer:
a tool that interprets the source code and tries to build a logic
gates network that implements the same behavior. There are a lot
of differences between synthesizers and true compilers but one
that is meaningful to you is that compilers usually accept the
whole syntax of while synthesizers can only handle a small subset.

> I'm currently using Synopsys FPGA Express
> v3.3 (that comes with Xilinx Foundation 2.1i),

That is, a synthesizer, not a compiler.

> and have found that this
> compiler does not support the 'math_real' IEEE library for real (i.e.
> floating point) numbers, or the divide "/" function from the
> 'numeric_std' IEEE library.

Because real stuff is not synthesizable logic synthesizers. Same
with dividers. The reason being that a FPU or a divider are too
large modules with too many different possible hardware
architectures. If you code your real operations at a too high
level of abstraction (S := A * B; S, A and B beeing floats) you
don't give enough informations about the hardware architecture you
want. So, if you really need floating point in your hardware
either use an already designed FPU or design your own (and then
you'll have to deal with sign, exponent and mantissa, left and
right shifts, infinity, not a number, zero+, zero-, etc).

> I was wondering if anyone knows if current
> versions of Synopsys FPGA Compiler II or Synopsys FPGA Express have
> support for these libraries?  Does the Xilinx XST Compiler support these
> libraries?  What other professional HDL compilers are offered, which
> provide this kind of support?  If these libraries aren't yet supported
> in any compilers, why is this the case?  Thanks for your time.

Every true compiler supports reals and dividers (and pointers, files,
etc). Their names are Leapfrog, Ncsim, Modelsim, VSS, etc. Not FPGA
Compiler, MAX+II, Quartus, dc_shell, ac_shell, etc. The frequent
confusion (even in this group) comes from post-synthesis simulation
capabilities of some synthesizers. MAX+II, for instance, lets you
define waveform stimulus, simulate your design and analyze the
resulting waveforms. But first of all it synthesizes your source
code because it's not a true compiler-linker-simulator, it's what we
call a gate-level simulator, all it can "simulate" is a network of
gates, a netlist. So it cannot simulate reals and dividers while
Ncsim from Cadence can. Hope it helps.

Regards,
-- 
Renaud Pacalet, ENST / COMELEC, 46 rue Barrault 75634 Paris Cedex 13
Tel. : 01 45 81 78 08 | Fax : 01 45 80 40 36 | Mel : pacalet@enst.fr

Article: 31599
Subject: Re: PAD to PAD Timing Constraints. (Xilinx)
From: "fred" <x@y.z>
Date: Thu, 31 May 2001 08:46:43 +0100
Links: << >>  << T >>  << A >>
If you use Project Manager and have created a project, there will be a
<myproject>.ucf constarints file in the project directory which is an
editable template with examples. Theres also a template blank in the
<Xilinx> tree. The defn you want is:

# ------------------
# FROM:TO TIME-SPECs
# ------------------
TIMESPEC TSP2P  = FROM : PADS  : TO : PADS  : 125 ns;
#
this is global, for all pads. If you want to act on specific pads, group
them together with a timegroup:

TIMEGRP my_constrained_pads = PADS(mypad1 : mypad2 : more_pads) ;

and use

TIMESPEC TSmypads  = FROM : my_constrained_pads : TO : my_constrained_pads :
125 ns;


Fred








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