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Messages from 31775

Article: 31775
Subject: Re: Help in FIFO design
From: "Austin Franklin" <austin@dar54kroom.com>
Date: Tue, 5 Jun 2001 17:54:29 -0400
Links: << >>  << T >>  << A >>
> I think I have a watertight design that uses Gray (that's the correct
> spelling)

As a note, Gray codes are named after the Frank Gray who patented their use
for shaft encoders in 1953

> Peter Alfke ( designed the industry's first FIFO, the Fairchild 3341, in
1971. )

No one else EVER used/implemented a FIFO before that???

As another note, FIFO is a standard inventory accounting term and has been
for a very long time...




Article: 31776
Subject: CMOS Analog Director of IC Design -Seattle
From: Anjanette Gautier <agautier@scientific.com>
Date: Tue, 05 Jun 2001 21:58:42 GMT
Links: << >>  << T >>  << A >>
We are desperately looking for the best ANALOG IC ENGINEERS!!!

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Basic requirements:
* 10 years of successfully developing product to market in the hardware 
industry
* ASIC/ Mixed signal development
* BSEE required. MS EE or higher preferred
* Ability to work effectively with product management, system, CAD, and 
foundry partners
* Proven track record of sucessfully leading and mentor junior analog 
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questions and resolving IC design issues. 

This company needs you today. How does full relocation costs sound to 
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recruiting specialists would be more than happy to tailor a comprehensive 
job search to your specific needs and abilities.   We currently have job 
openings available with hardware clients across the country who are looking 
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Associate
Scientific Placement, Inc
512-331-0302
512-331-1828 fax
agautier@scientific.com

Article: 31777
Subject: Re: FPU IEEE-754 calculation
From: "Peter L. Montgomery" <Peter-Lawrence.Montgomery@cwi.nl>
Date: Tue, 5 Jun 2001 22:12:25 GMT
Links: << >>  << T >>  << A >>
In article <3B1C0F7C.93A14865@ieee.org> khatib@ieee.org writes:
>I am trying to implement a floating point arithmetic adder subtractor
>based on IEEE-754 standard
>I am comparing the results from my code with the Softfloat library
>results
>
>I have problems with some operations such as
>0x807FFFFC  +  0x3A000001  the softfloat produces 0x3A000000  but my
>code produces 0x3A000001
>This problem occurs whenever the difference between the exponents is too
>large
>
>Can anyone point me to the possible source of error?
>Note: I am using round to nearest zero rounding (chupping)

    I believe the leftmost bit is the sign bit, so 0x807FFFFC is
negative but 0x3A000001 is positive.  Their unrounded
sum is (barely) less than 0x3A000001.  Since you are rounding towards zero,
the sum should round down, to 0x3A000000.
You may need to retain a guard bit (or is it called a sticky bit?)
when the negative operand becomes all zeros after shifting.
[But don't generate this guard bit for a -0 operand.]
    

 
-- 
The 21st century is starting after 20 centuries complete,
but we say someone is age 21 after 21 years (plus fetus-hood) complete.
        Peter-Lawrence.Montgomery@cwi.nl    Home: San Rafael, California
        Microsoft Research and CWI

Article: 31778
Subject: Re: one state machine
From: "Austin Franklin" <austin@dar54kroom.com>
Date: Tue, 5 Jun 2001 18:31:45 -0400
Links: << >>  << T >>  << A >>

> It should take you less than 15 minutes to write the three logic
equations, then
> leave it to the synthesis tool to optimize it down to  a single level of
logic.

I've yet TO find anything that 1) takes 15 minutes to do, and 2) does what I
want it to, in synthesis.  Now, if you said draw it in ViewDraw, I could do
it in three minutes, and I know it would do what I want it to ;-)




Article: 31779
Subject: Re: Help in FIFO design
From: Peter Alfke <peter.alfke@xilinx.com>
Date: Tue, 05 Jun 2001 15:33:57 -0700
Links: << >>  << T >>  << A >>

The real origin goes back to a 1963 Danish ultra-fast paper-tape reader from a
company called Gier. It read 1000 characters per second, and "virtually" stopped
on a character by using a magnetic core buffer between the optical read cell and
the output. In Sweden, I had designed an interface to this reader. A few years
later, the memory of that design came back and spawned the idea of a
semiconductor FIFO.
That's why I wrote "the industry's" meaning the semiconductor industry's.
FIFO is a centuries-old accounting term, but nobody had offered an IC memory
device of that type before the Fairchild 3341 in 1971.  It had taken me 2 years
of kicking the company, because Marketing had never seen a request for a FIFO.
For several years, Fairchild had a monopoly, and at times it was their only
profitable (n-channel) MOS device.
Times change...

Peter Alfke
=======================================
Austin Franklin wrote

>
> > Peter Alfke ( designed the industry's first FIFO, the Fairchild 3341, in
> 1971. )
>
> No one else EVER used/implemented a FIFO before that???
>
> As another note, FIFO is a standard inventory accounting term and has been
> for a very long time...


Article: 31780
Subject: Re: Help in FIFO design
From: "Austin Franklin" <austin@dar54kroom.com>
Date: Tue, 5 Jun 2001 19:09:13 -0400
Links: << >>  << T >>  << A >>
Have you  been hanging out with Rocky again?  (personal joke)

Are you sure IBM (or any of the dozens of computer manufacturers from the
50's etc.) didn't have any FIFOs at all, in any of their hardware?  Now, if
you said it was the first "standard" MOS product, that I could believe.  I
believe FIFOs had been around for decades (in the computer industry) before
1971.


"Peter Alfke" <peter.alfke@xilinx.com> wrote in message
news:3B1D5E55.31A4CF73@xilinx.com...
>
> The real origin goes back to a 1963 Danish ultra-fast paper-tape reader
from a
> company called Gier. It read 1000 characters per second, and "virtually"
stopped
> on a character by using a magnetic core buffer between the optical read
cell and
> the output. In Sweden, I had designed an interface to this reader. A few
years
> later, the memory of that design came back and spawned the idea of a
> semiconductor FIFO.
> That's why I wrote "the industry's" meaning the semiconductor industry's.
> FIFO is a centuries-old accounting term, but nobody had offered an IC
memory
> device of that type before the Fairchild 3341 in 1971.  It had taken me 2
years
> of kicking the company, because Marketing had never seen a request for a
FIFO.
> For several years, Fairchild had a monopoly, and at times it was their
only
> profitable (n-channel) MOS device.
> Times change...
>
> Peter Alfke
> =======================================
> Austin Franklin wrote
>
> >
> > > Peter Alfke ( designed the industry's first FIFO, the Fairchild 3341,
in
> > 1971. )
> >
> > No one else EVER used/implemented a FIFO before that???
> >
> > As another note, FIFO is a standard inventory accounting term and has
been
> > for a very long time...
>



Article: 31781
Subject: Re: one state machine
From: "Austin Franklin" <austin@dar54kroom.com>
Date: Tue, 5 Jun 2001 19:16:42 -0400
Links: << >>  << T >>  << A >>

> Interesting.
> So there are cases where the schematic is simpler than theVHDL.
> ...
> Peter Alfke
> ========================

Cases?  Schematic is most ALWAYS simpler than any HDL (if done properly and
with the right tools)...but you really don't want get me going on that, now
do you?  If you do, I'll be HAPPY to chime in ;-)




Article: 31782
Subject: Re: one state machine
From: "Austin Franklin" <austin@dar54kroom.com>
Date: Tue, 5 Jun 2001 19:19:18 -0400
Links: << >>  << T >>  << A >>

> Synth tools are no different from any others and only give their best
results after
> spending time learning how to use them

Oh yes they are!  What about the problem when the synthesis tool vendor (or
a different tool) CHANGES the tools to do something different the next bug
relese?  There is NO standard or documented construct dissemination, and
that causes a LOT of problems!




Article: 31783
Subject: Re: one state machine
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Wed, 06 Jun 2001 01:15:49 +0100
Links: << >>  << T >>  << A >>


Austin Franklin wrote:

> > It should take you less than 15 minutes to write the three logic
> equations, then
> > leave it to the synthesis tool to optimize it down to  a single level of
> logic.
>
> I've yet TO find anything that 1) takes 15 minutes to do, and 2) does what I
> want it to, in synthesis.  Now, if you said draw it in ViewDraw, I could do
> it in three minutes, and I know it would do what I want it to ;-)

Just timed it. From a standing start to completed synth of a Verilog module
implementing the original poster's sequence in 8 min(*). Result, using
"syn_preserve" on the register, = 3 LUTs, 3FFs, 1 level.

Maybe you are thinking of VHDL (couldn't resist)

*  One minute of which was wasted in reinstalling the dongle into my home
machine and restarting the license daemon.



Article: 31784
Subject: Re: Help in FIFO design
From: Peter Alfke <peter.alfke@xilinx.com>
Date: Tue, 05 Jun 2001 17:26:11 -0700
Links: << >>  << T >>  << A >>
Austin, let' not mix up hardware and software.
I am sure that the computer industry used FIFOs and LIFO stacks in software, but
there were no semiconductor memories around before 1969.
It started then with some puny 64-bit memories, and the ILLIAC used the first
large arrays of (puny) bipolar memories, but otherwise it was a mag-core world.
Intel was founded in the summer of 1969, (I joined Fairchild the day Bob Noyce
left, no correlation! ) and their first product was an n-channel MOS memory and
(I think ) also a bipolar memory. All way below 1024 bits.

Peter Alfke

Austin Franklin wrote:

> Have you  been hanging out with Rocky again?  (personal joke)
>
> Are you sure IBM (or any of the dozens of computer manufacturers from the
> 50's etc.) didn't have any FIFOs at all, in any of their hardware?  Now, if
> you said it was the first "standard" MOS product, that I could believe.  I
> believe FIFOs had been around for decades (in the computer industry) before
> 1971.
>
> "Peter Alfke" <peter.alfke@xilinx.com> wrote in message
> news:3B1D5E55.31A4CF73@xilinx.com...
> >
> > The real origin goes back to a 1963 Danish ultra-fast paper-tape reader
> from a
> > company called Gier. It read 1000 characters per second, and "virtually"
> stopped
> > on a character by using a magnetic core buffer between the optical read
> cell and
> > the output. In Sweden, I had designed an interface to this reader. A few
> years
> > later, the memory of that design came back and spawned the idea of a
> > semiconductor FIFO.
> > That's why I wrote "the industry's" meaning the semiconductor industry's.
> > FIFO is a centuries-old accounting term, but nobody had offered an IC
> memory
> > device of that type before the Fairchild 3341 in 1971.  It had taken me 2
> years
> > of kicking the company, because Marketing had never seen a request for a
> FIFO.
> > For several years, Fairchild had a monopoly, and at times it was their
> only
> > profitable (n-channel) MOS device.
> > Times change...
> >
> > Peter Alfke
> > =======================================
> > Austin Franklin wrote
> >
> > >
> > > > Peter Alfke ( designed the industry's first FIFO, the Fairchild 3341,
> in
> > > 1971. )
> > >
> > > No one else EVER used/implemented a FIFO before that???
> > >
> > > As another note, FIFO is a standard inventory accounting term and has
> been
> > > for a very long time...
> >


Article: 31785
Subject: Re: Help in FIFO design
From: Eric Smith <eric-no-spam-for-me@brouhaha.com>
Date: 05 Jun 2001 18:20:32 -0700
Links: << >>  << T >>  << A >>
"Peter Alfke" <peter.alfke@xilinx.com> wrote:
> That's why I wrote "the industry's" meaning the semiconductor
> industry's.  FIFO is a centuries-old accounting term, but nobody had
> offered an IC memory device of that type before the Fairchild 3341 in
> 1971.

"Austin Franklin" <austin@dar54kroom.com> followed up with:
> Are you sure IBM (or any of the dozens of computer manufacturers from the
> 50's etc.) didn't have any FIFOs at all, in any of their hardware?

Despite IBM being a semiconductor manufacturer (and thus arguably part
of the semiconductor industry), any FIFO buffers they made in the 1950s
and 1960s certainly weren't "semiconductor industry" products.

> Now, if you said it was the first "standard" MOS product, that I could
> believe.  I believe FIFOs had been around for decades (in the computer
> industry) before 1971.

Well, since they were so commonplace, I'm sure you'll have no trouble
citing a specific reference to a semiconductor-industry FIFO made before
1971.  :-)

Article: 31786
Subject: Re: Virtex LUT4 problems in FPGA Express
From: Kent Orthner <korthner@hotmail.nospam.com>
Date: 06 Jun 2001 10:50:30 +0900
Links: << >>  << T >>  << A >>

> Kent Orthner <korthner@hotmail.nospam.com> writes:
> > I seem to remember somewhere that to specify the initial contents of a 
> > RAM or LUT, you need to use an attribute, that the synthesizer will 
> > not grab it from the generic.  Sorry I forgot to mention this before.

Michael Dales <michael@dcs.gla.ac.uk> writes:
> Ah. As an aside, is this a general rule of thumb? Passing info to
> simulation is done using generics and synthesis using attributes? 

As far as I can tell, with synthesys tools, there are no rules of thumb.
But the INIT generic would be an excellent place to specefy the INITial 
contents of the RAM for synthesis, no?

> For the key I actually use a series of LUT1s - this may be inefficient
> in terms of area, but my idea depends on my ability to locate a
> replace the the key simply. It is also a requirement of my project
> that I don't use RAM blocks (I'm trying to predict the performance of
> a processor that had Virtex fabric attached to it - but having large
> amounts of state in a processor is a bad idea, so I assume that RAM
> blocks wouldn't be allowed).
> 
> Probably more info than you wanted to know ;) 

I am interested in understanding why you figure using RAM would be bad ...
seems like the easiest/most logical solution, no?

-Kent

Article: 31787
Subject: Re: Help in FIFO design
From: "Austin Franklin" <austin@dar54kroom.com>
Date: Tue, 5 Jun 2001 23:32:40 -0400
Links: << >>  << T >>  << A >>
> Well, since they were so commonplace, I'm sure you'll have no trouble
> citing a specific reference to a semiconductor-industry FIFO made before
> 1971.  :-)

It actually should be relatively easy.  Most every computer made from the
late 50's on up was made from semiconductors....  The DEC PDP-1 was out in
1960, and was entirely solid state.  Transistors are semiconductors, as I'm
sure you know ;-)

Anyway, why would it have to be implemented in semiconductors to be a FIFO?
Peter's initial statement didn't state what "industry" he was referring to,
I assumed computer industry.  I really believe computers had FIFOs before
1971...  I have no problem believing that he (Peter) implemented the first
commercially available integrated circuit FIFO.  That wasn't what was at
"issue".




Article: 31788
Subject: Re: Help in FIFO design
From: "Austin Franklin" <austin@dar54kroom.com>
Date: Tue, 5 Jun 2001 23:35:26 -0400
Links: << >>  << T >>  << A >>
> Austin, let' not mix up hardware and software.

I'm not.

> I am sure that the computer industry used FIFOs and LIFO stacks in
software, but
> there were no semiconductor memories around before 1969.

It doesn't have to be what you are thinking of as a regular "memory" to be a
FIFO.  Either in the CPU, or in a peripheral, I'm reasonably sure someone
used a FIFO of some sort prior to 1971.  Cripes, one register, with a "full"
and "empty" flag is a FIFO!





Article: 31789
Subject: Re: Help in FIFO design
From: Austin Lesea <austin.lesea@xilinx.com>
Date: Tue, 05 Jun 2001 21:00:12 -0700
Links: << >>  << T >>  << A >>
Ahhhh, old computers,

The GR-15 tube computer with rotating disk memory (each instruction had the
address of the next one, so if you shuffled the card deck it ran faster due to
"catching" the next instruction more frequently due to rotational latency),

the PDP-1, the PDP-5 made out of flip chip modules of discrete transistor NAND,
NORS, FF's,

the IBM 1604 and 1800 with their hybrid modules and their 8 state bus,

the PDP-8's,

the Meta 4 with its paper dot capacitor ROM for microprogramming,

the HP 2100's with DTL (wow!), the Nova from Data General (the soul of a new
machine!),

and the venerable PDP-11 had no semiconductor FIFO's as far as I can remember.

As Peter noted, to interface to these computers, one needed tons of random
logic, memories (core, whatever), and the first time I implemented a "fifo" was
in 1971.  It was made from a new Intel bipolar memory IC (256 X 8!) and a bunch
of control logic for a ..... yes! Paper Tape Reader.

Later in 1974 I used a Fairchild FIFO (thanks Peter) for a novel terminal
concentrator with an Intel 8080 so that The first Berkeley UNIX PDP-11/70 could
access clusters of 32 - 9600 baud ADM3A terminals.  Packets were created from
keystrokes on all of the terminals once every 16 ms, and sent to the FIFO on
the 11/70 bus.  The 11/70 woke up every 16 ms to process all packets that had
arrived.  This removed all interrupt overhead for each and every terminal and
allowed Berkeely UNIX to serve ~128 users time share real time (as opposed to
twelve if you used individual RS232 interface cards with TX and RX interrupts
for each character).

It isn't that we didn't know or want a FIFO as I recall, it was just too tricky
to make one out of discretes (really requires matched tracking timing paths, or
more logic than we had a stomach for to do it right).

Austin

Austin Franklin wrote:

> > Well, since they were so commonplace, I'm sure you'll have no trouble
> > citing a specific reference to a semiconductor-industry FIFO made before
> > 1971.  :-)
>
> It actually should be relatively easy.  Most every computer made from the
> late 50's on up was made from semiconductors....  The DEC PDP-1 was out in
> 1960, and was entirely solid state.  Transistors are semiconductors, as I'm
> sure you know ;-)
>
> Anyway, why would it have to be implemented in semiconductors to be a FIFO?
> Peter's initial statement didn't state what "industry" he was referring to,
> I assumed computer industry.  I really believe computers had FIFOs before
> 1971...  I have no problem believing that he (Peter) implemented the first
> commercially available integrated circuit FIFO.  That wasn't what was at
> "issue".


Article: 31790
Subject: Re: Help in FIFO design
From: Eric Smith <eric-no-spam-for-me@brouhaha.com>
Date: 05 Jun 2001 21:17:35 -0700
Links: << >>  << T >>  << A >>
"Austin Franklin" <austin@dar54kroom.com> writes:
> It actually should be relatively easy.  Most every computer made from the
> late 50's on up was made from semiconductors....  The DEC PDP-1 was out in
> 1960, and was entirely solid state.  Transistors are semiconductors, as I'm
> sure you know ;-)

The PDP-1 doesn't contain any FIFOs.  If you can cite a FIFO available
as a purchasable semiconductor-based product (even using discrete
transistors) that was available before 1971, a lot of us will be
interested.  For that matter, any sort of electronic FIFO, or even
electromechanical.  As long as it's digital and the input and output
rates can be independently varied.  A delay line doesn't qualify.

AFAIK, no one sold FIFOs as a product until Peter's product.

Even most early computer peripherals that used buffer memory used it in
a dual ported direct-access arrangement rather than a FIFO, e.g., the
core buffer options on some early IBM card readers.

> Peter's initial statement didn't state what "industry" he was referring to,
> I assumed computer industry.  I really believe computers had FIFOs before
> 1971...  I have no problem believing that he (Peter) implemented the first
> commercially available integrated circuit FIFO.  That wasn't what was at
> "issue".

And yet after he clarified that he meant "semiconductor industry", you
continued to try to refute his claim.

Article: 31791
Subject: Re: one state machine
From: Lasse Langwadt Christensen <langwadt@ieee.org>
Date: Tue, 05 Jun 2001 22:05:54 -0700
Links: << >>  << T >>  << A >>
Allan Herriman wrote:
> 
> Hi Brian,
> 
> Brian_Sullivan wrote:
> > This gives 3 LC in an APEX20KE device through Synplify.  I do not have
> > accesss to Xilinx tools, so I cannot comment on that.  Let me know if
> > this helps.
> 
> This code also gives 3 LUTs and 3FF in a Virtex-E, using Synplify (what
> do you mean, you don't have the Xilinx tools :)
> 
snip

FE says 2LUTs and 3FF in a Virtex-E  

-Lasse
-- Lasse Langwadt Christensen, 
-- PHX,AZ


Article: 31792
Subject: Re: Pentium 4 or AMD ?
From: Rick Collins <spamgoeshere4@yahoo.com>
Date: Wed, 06 Jun 2001 02:21:51 -0400
Links: << >>  << T >>  << A >>
I would not disagree with what you say about the cost of RDRAM, but this
is the first time I have heard claims that it is not as fast as it is
supposed to be. Why do you say this? Or are you really referring to its
use with the P4?


Eric wrote:
> 
> I would go with AMD Athlon 1333 with DDR memory.
> 
> P4 reaches 1.7Gigs but to achieve this, the pipeline
> is much too long, a typical case of marketing tactics
> interfering badly with real word performance.
> 
> Also, P4 only works with infamous RDRAM (RIMM)
> that underperforms and costs too much (especially since
> large Xilinx devices PAR requires anywhere between 256M
> and 1Gig RAM). Main technical problem with RDRAM
> is the very long latency time, compared to SDRAM / DDR
> that is not compensated by the higher theoretical peak
> bandwidth.
> 
> If you want to get the most of your system, use DDR
> from major brands (Micron) that's specified with a CAS
> latency of 2 or 2.5.
> 
> Here is a good memory module vendor :
> http://www.corsairmicro.com/main/products.htm
> 
> Some multimedia benchmarks show P4 performing better
> than AMD Athlon, because those applications use the P4
> proprietary SSE2 extended instructions. AFAIK, PAR does
> not use them, so these benchmarks can safely be ignored.
> 
> You can find lots of benchmarks here as long as you forget
> about the gaming/overclocking stuff :
> 
> Intel P4 1.7Gigs
> http://www6.tomshardware.com/cpu/01q2/010423/index.html
> 
> AMD Athlon 1333 / DDR
> http://www6.tomshardware.com/cpu/01q1/010322/index.html
> 
> ----------
> 
> One thing I always wondered is the reason why the PAR
> software can't use FPGA based hardware accelerators.
> Maybe the PAR algorithms are not a good fit for FPGA
> processing, or market for such devices would be too small ?
> 
> ----------
> 
> Eric.
> 
> -----------------------------------------------------
> 
> Domagoj wrote:
> 
> > Hi!
> >
> >  Has anybody done any comparison of
> > Pentium 4 vs. AMD architectures for PAR and
> > simulation ? What about RIMM/DRAM/DDR ?
> >
> > thx
> >
> > Regards,
> >      Domagoj Babic
> >    domagoj(et)rasip.fer.hr


-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 31793
Subject: Re: one state machine
From: Rick Collins <spamgoeshere4@yahoo.com>
Date: Wed, 06 Jun 2001 02:41:44 -0400
Links: << >>  << T >>  << A >>
Austin Franklin wrote:
> 
> > It should take you less than 15 minutes to write the three logic
> equations, then
> > leave it to the synthesis tool to optimize it down to  a single level of
> logic.
> 
> I've yet TO find anything that 1) takes 15 minutes to do, and 2) does what I
> want it to, in synthesis.  Now, if you said draw it in ViewDraw, I could do
> it in three minutes, and I know it would do what I want it to ;-)

I understand why you have such a dislike of HDLs. My first exposure to
VHDL was less than pleasant. But I have returned to HDLs on a project
using Verilog and I am having a much better go of it. 

Some of the problems I had stemmed from the strong typing in VHDL,
combined with the poor documentation of the conversion libraries. There
is always a way to make it work, but it is not always obvious how to do
it. 

Many of the problems I had were just a matter of learning what to expect
from an HDL. After you get some experience with a compilier, you learn
what kind of design it produces from what type of code. Now I very
seldom have a problem getting what I want even in very highly optimized
design. The only exception is when I need to use a unique architectural
feature. Other than instantiation, this can be difficult to coax. But
often there is no good reason not to use instantiation. 

So jump in and get to know HDLs. You may even like it once you learn the
flow.

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 31794
Subject: Mapping a Library
From: Kyriakos Vlachos <kvlachos@lucent.com>
Date: Wed, 06 Jun 2001 09:29:21 +0200
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.
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Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit


Does anybody know how to map a library to a host directory?
I did mapped a library but I do not know how to map it a host directory.

This was an error emerged from Synopsys while the simulation of my design was
OK.


Thanks
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begin:vcard 
n:Vlachos;Kyriakos
tel;fax:+31 35 687 5954
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--------------EAEA7AFEF50B25BEDFAB8582--


Article: 31795
Subject: Re: one state machine
From: allan_herriman.hates.spam@agilent.com (Allan Herriman)
Date: Wed, 06 Jun 2001 07:34:50 GMT
Links: << >>  << T >>  << A >>
On Tue, 05 Jun 2001 22:05:54 -0700, Lasse Langwadt Christensen
<langwadt@ieee.org> wrote:

>Allan Herriman wrote:
>> 
>> Hi Brian,
>> 
>> Brian_Sullivan wrote:
>> > This gives 3 LC in an APEX20KE device through Synplify.  I do not have
>> > accesss to Xilinx tools, so I cannot comment on that.  Let me know if
>> > this helps.
>> 
>> This code also gives 3 LUTs and 3FF in a Virtex-E, using Synplify (what
>> do you mean, you don't have the Xilinx tools :)
>> 
>snip
>
>FE says 2LUTs and 3FF in a Virtex-E  

Hi Lasse,
   One of the LUTs was an inverter, so it would vanish once it hit the
back end tools.

IIRC, Virtex-E has inverters built in to the flip flops.  Why doesn't
the picture in the databook show them?

Regards,
Allan.

Article: 31796
Subject: What am I doing wrong?
From: ruitenbe@cs.utwente.nl
Date: 6 Jun 2001 07:38:26 GMT
Links: << >>  << T >>  << A >>
Hi, I want to implement a state machine which runs through state SA2
50 times, but I can't get it to work correctly.

Here's what I have:
SUBDESIGN final
(
waveout: OUTPUT;
d0, d1, d2 : INPUT;
strobe : INPUT;
clock : INPUT; 
)
VARIABLE
buf[2..0] : DFF;
buff[5..0] : DFF;
SA: machine with states(sa0, sa1, sa2);	
count[6..0]: DFFE;
pulstel[6..0]: DFF;
pulscnt[5..0]: DFF;
zendloop[5..0]: DFF;
nieuw[6..0]: DFF;
BEGIN
zendloop[].clk = global (clock);
buff[].clk = clock;
buf[].clk = clock;
pulstel[].clk = clock;
pulscnt[].clk = clock;
nieuw[].clk = clock;
count[].clk = clock;
count[].d=count[].q+1;
sa.clk = clock;
buf[2].d = d2;
buf[1].d = d1;
buf[0].d = d0;
CASE SA IS
	WHEN sa0 =>
	zendloop[].d=0;				%reset voor loop in sa2%
	pulstel[].d=0;
	pulscnt[].d=0;
		IF !strobe THEN
			count[].ENA = gnd;
		END IF;
			IF strobe THEN
				count[].ENA = vcc;
				SA = sa1;
			END IF;
	WHEN sa1 =>
		IF strobe THEN
			IF !buf[0] & !buf[1] & !buf[2] THEN % 105%
				buff[].d = 53;
				nieuw[].d = 105; 
				waveout = Vcc;
				SA = sa2;
			END IF;
			IF !buf[0] & !buf[1] & buf[2] THEN %103%
				buff[].d = 52;
				nieuw[].d = 103;
				waveout = Vcc;
				sa = sa2;
			END IF;
			IF !buf[0] & buf[1] & !buf[2] THEN %102%
				buff[].d = 51;
				nieuw[].d = 102;
				waveout = Vcc;
				SA = sa2;
			END IF;
			IF !buf[0] & buf[1] & buf[2] THEN %101%
				buff[].d = 50;
				nieuw[].d = 101;
				waveout = Vcc;
				SA = sa2;
			END IF;
			IF buf[0] & !buf[1] & !buf[2] THEN %100%
				buff[].d = 49;
				nieuw[].d = 100;
				waveout = Vcc;
				SA = sa2;
			END IF;
			IF buf[0] & !buf[1] & buf[2] THEN %99%
				buff[].d = 48;
				nieuw[].d = 99;
				waveout = Vcc;
				SA = sa2;
			END IF;
			IF buf[0] & buf[1] & !buf[2] THEN %98%
				buff[].d = 47;
				nieuw[].d = 98;
				waveout = Vcc;
				SA = sa2;
			END IF;
			IF buf[0] & buf[1] & buf[2] THEN %97%
				buff[].d = 46;
				nieuw[].d = 97;
				waveout = Vcc;
				SA = sa2;
			END IF;
		END IF;
	WHEN sa2 =>
			if pulscnt[].q == buff[].q then waveout=gnd;
				SA = sa1;
			elsif zendloop[].q == 50 then
				SA = sa0;
			else zendloop[].d = zendloop[].q+1;
				pulscnt[].d = pulscnt[].q+1;
			end if;
	END CASE;
END;


The problem is that it gets through the various states very well, but
waveout seems to be stuck to ground in SA2.
But it shouldn't be stuck at ground, it should change to Vcc when 50
ticks of the clock have passed

What am I doing wrong? Any ideas would be greatly appreciated.

-- 
Sander Ruitenbeek
tel: +31622518788 e-mail: ruitenbe@cs.utwente.nl


Article: 31797
Subject: problem: bahavior simulation of xilinx's coregen cores
From: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
Date: Wed, 06 Jun 2001 10:08:36 +0200
Links: << >>  << T >>  << A >>
Hi,

I encountered a little problem in the bahavioral simulation a xilinx
core that have been generated with the core generator. 

All outputs of the core instances are in the unknown state ('U'). Timing
simulation works fine !

I am using the xilinx coregen with IP update #3 from xilinx foundation
software service pack #6. I installed all updated and precompiled
simulation libraries (including the xilinx core lib) for modelsim 5.3d
XE (as it comes with the WebPack CD).

I copied all sections from the .vho file to the right locations
(configuration etc.). When I start modelsim out of the webpack
enviroment to do a functional simulation, I got a warning that my core
component (async fifo V3.0) is not bound - This warning can be ignored !
When I start my testbench, all outputs of my core (I also tested a
simple counter core) stay unknown.

What could be the reson for this behavior ? I noticed an other problem
that could have somthing to do with the above: In one of my other
projects I am using a "hand instancetiated" BUFG and IBUF. These
components are not working in functional simulation. Why ? How can I use
and where can I find models for these components ?

Matthias
-- 
-------------------------------------------------
\ Matthias Fuchs                                 \
 \ esd electronic system design Gmbh              \
  \ Vahrenwalder Straße 205                        \
   \ D-30165 Hannover                               \
    \ email: matthias.fuchs@esd-electronics.com      \
     \ phone: +49-511-37298-0                         \
      \ fax:   +49-511-37298-68                        \
       --------------------------------------------------

Article: 31798
Subject: Re: FPU IEEE-754 calculation
From: Terje Mathisen <terje.mathisen@hda.hydro.com>
Date: Wed, 06 Jun 2001 10:47:09 +0200
Links: << >>  << T >>  << A >>
"Peter L. Montgomery" wrote:
>     I believe the leftmost bit is the sign bit, so 0x807FFFFC is
> negative but 0x3A000001 is positive.  Their unrounded
> sum is (barely) less than 0x3A000001.  Since you are rounding towards zero,
> the sum should round down, to 0x3A000000.
> You may need to retain a guard bit (or is it called a sticky bit?)
> when the negative operand becomes all zeros after shifting.

I believe 'sticky bit' is correct: What it should do is to remember the
fact that at least one bit to the right of the current position was set.

When I implemented a 128-bit fp lib, I finally understood why the IEEE
specs talk about both guard and sticky bit: Having both is enough to
guarantee correct rounding in all modes.

You must have two because the initial FADD/FSUB operation can lead to a
change in the final exponent, which requires one more bit in the
resulting mantissa.

Terje

-- 
- <Terje.Mathisen@hda.hydro.com>
Using self-discipline, see http://www.eiffel.com/discipline
"almost all programming can be viewed as an exercise in caching"

Article: 31799
Subject: Re: one state machine
From: allan_herriman.hates.spam@agilent.com (Allan Herriman)
Date: Wed, 06 Jun 2001 08:53:45 GMT
Links: << >>  << T >>  << A >>
On Wed, 06 Jun 2001 07:34:50 GMT,
allan_herriman.hates.spam@agilent.com (Allan Herriman) wrote:

>On Tue, 05 Jun 2001 22:05:54 -0700, Lasse Langwadt Christensen
><langwadt@ieee.org> wrote:
>
>>Allan Herriman wrote:
>>> 
>>> Hi Brian,
>>> 
>>> Brian_Sullivan wrote:
>>> > This gives 3 LC in an APEX20KE device through Synplify.  I do not have
>>> > accesss to Xilinx tools, so I cannot comment on that.  Let me know if
>>> > this helps.
>>> 
>>> This code also gives 3 LUTs and 3FF in a Virtex-E, using Synplify (what
>>> do you mean, you don't have the Xilinx tools :)
>>> 
>>snip
>>
>>FE says 2LUTs and 3FF in a Virtex-E  
>
>Hi Lasse,
>   One of the LUTs was an inverter, so it would vanish once it hit the
>back end tools.
>
>IIRC, Virtex-E has inverters built in to the flip flops.  Why doesn't
>the picture in the databook show them?

I can answer my own question.  There's an optional inverter on the BX
and BY inputs.  This isn't shown in the Virtex-E data book, but it
*is* shown in the Virtex2 data book.

Regards,
Allan.



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