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Messages from 32050

Article: 32050
Subject: Re: Gray Code Guard bits (was Re: Help in FIFO design)
From: Peter Alfke <palfke@earthlink.net>
Date: Tue, 12 Jun 2001 05:20:16 GMT
Links: << >>  << T >>  << A >>
I think we all understand now that the lengthened Gray counter works ( sorry
for my original doubts ), but I still claim that "my" way of using a Gray
counter of normal length is simpler, since I can differentiate between Full and
Empty with just a latch set or reset by looking at the two sets of two "MSBs"
of the Gray counters.
VHDL description is almost ready, app note following that.
I think we can do >200 MHz asynchronous clocks in Virtex-II, limited by the
BlockRAM clock-to-out delay. Maybe we can do 300 MHz in small, 16-deep FIFOs in
distributed LUT-RAM. Any takers?

Peter Alfke, Xilinx Applications
=================================
John_H wrote:

> Don,
>
> I'm disappointed you didn't give iglam the benefit of the doubt in his short
>
> response.
>
> Look at your example of why the count sequence "won't work" and take an xor
> of the two msbits instead of ignoring the msbit.  Suddenly there's no data
> scramble.
>
> Converting both ways between binary and Gray and using 4 bit comparators is
> more resource intensive than the xor of the Gray counter's two msbits and
> the
> comparator xor.
>
> Of course using all the lsbs unmodified would scramble your data.  Iglam
> incorrectly mentioned the msb was ignored but I don't see that as reason to
> dismiss the idea out of hand.
>
> Gray is powerful, but you can't ignore the fact that it's different from
> what we're "used to."
>
> > Bzzzzzt. This won't work.
> >
> > Consider a 4-word fifo using a 3-bit gray-code counter.  The
> > count sequence is:
> >    000
> >    001
> >    011
> >    010
> >    110
> >    111
> >    101
> >    100


Article: 32051
Subject: Re: Triscend A5: can it reconfigure itself?
From: C_van_Loos@Excite.com (Cor van Loos)
Date: 11 Jun 2001 23:35:57 -0700
Links: << >>  << T >>  << A >>
"Steve Beaver" <sbeaver@columbus.rr.com> wrote in message news:<xI6V6.51481$V5.1979837@typhoon.columbus.rr.com>...
> At a recent seminar I attended on the Triscend chip, they said it could.
> 
> Steve

Try contacting Triscend for details on this matter. They gave us a lot
of technical support when evaluating a E5-device.

Cor

Article: 32052
Subject: High Speed Sampling Oscilloscope in an FPGA
From: "Rune Baeverrud" <fpga@iname.com>
Date: Tue, 12 Jun 2001 12:00:06 +0100
Links: << >>  << T >>  << A >>
Hello, and thanks to everyone for sharing your insight in this group!

I'm trying to figure out the basics for how you would/could implement a high
speed digital oscilloscope with an FPGA, with an analoge bandwidth of at
least a few GHz, and a sampling rate of a few hundred MHz. I'm in particular
looking for "undersampling" techniques, where you can build eye diagrams of
GHz analog waveforms using moderate sampling rates.

In this context i've been thinking hard about the trigger mechanism. Just
comparing digital sample values for determining trigger conditions would not
work, because of the low granularity. (2 GHz analog waveform with 256 points
resolution per period would yield a sample rate of 512GHz - which is
obviously out of the question. Also - jitter introduced by this measuring
method would be very bad). So - my conclusion so far is that the trigger
mechanism has to be based on a good old analog comparator.

Then comes the next part - which seems to be very tricky. In order to align
the digital samples correctly in time - you would need to accurately know
the time difference between the trigger point and the next sample point,
and/or between the trigger point and the previous sample point. These time
intervals could be in the ps range, and it seems to me that any clocked
digital circuitry would be inadequate for this kind of time measurement. If
you know both time intervals, I have an idea that the the accurateness of
these time intervals may not be so important, since you could use the ratio
of the two to align the trigger point compared to the sample points.

Does anyone have any idea of how this is done by the big guys like Tektronix
and LeCroy? And - do you know of any standard chips that could simplify this
kind of application?

Rune Baeverrud



Article: 32053
Subject: Re: Force tristate enable register into IOB
From: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
Date: Tue, 12 Jun 2001 13:35:21 +0200
Links: << >>  << T >>  << A >>
Tobias Stumber wrote:
> Use:
>   attribute IOB: string;
>   attribute IOB of ge_mem_oe_reg : signal is "true";
> This makes XST to replicate the FFs again after (!) having merged them into
> one in the final optimization phase.
> Works great !
> 
> Tobias
Hi,

I tried to attach the IOB attribute but it did not work ! Even if I
instanciate FlipFlop components(FD) by hand, they are optimized away and
a single flop drives 16 tristate signals. I also tried the max_fanout
attribute:

attribute max_fanout : integer;
attribute max_fanout of ge_mem_tri_reg : signal is 1;

.. same result !

What is wrong ?

Matthias
-- 
-------------------------------------------------
\ Matthias Fuchs                                 \
 \ esd electronic system design Gmbh              \
  \ Vahrenwalder Straße 205                        \
   \ D-30165 Hannover                               \
    \ email: matthias.fuchs@esd-electronics.com      \
     \ phone: +49-511-37298-0                         \
      \ fax:   +49-511-37298-68                        \
       --------------------------------------------------

Article: 32054
Subject: Re: Gray Code Guard bits (was Re: Help in FIFO design)
From: krw@btv.ibm.com (Keith R. Williams)
Date: Tue, 12 Jun 2001 12:31:32 GMT
Links: << >>  << T >>  << A >>
On Tue, 12 Jun 2001 05:20:16 GMT, Peter Alfke <palfke@earthlink.net>
wrote:

>I think we all understand now that the lengthened Gray counter works ( sorry
>for my original doubts ), but I still claim that "my" way of using a Gray
>counter of normal length is simpler, since I can differentiate between Full and
>Empty with just a latch set or reset by looking at the two sets of two "MSBs"
>of the Gray counters.
>VHDL description is almost ready, app note following that.
>I think we can do >200 MHz asynchronous clocks in Virtex-II, limited by the
>BlockRAM clock-to-out delay. Maybe we can do 300 MHz in small, 16-deep FIFOs in
>distributed LUT-RAM. Any takers?

Sure.  I'll take one ;-), though I'm stuck in Virtex/Virtex-E for now.
...waiting for the app note.

----
  Keith


Article: 32055
Subject: USB for a new FPGA based product, which transciever ?
From: Laurent Gauch <laurent.gauch@amontec.com>
Date: Tue, 12 Jun 2001 15:08:54 +0200
Links: << >>  << T >>  << A >>
Dear all,

For a new product, I want to have an USB 2.0 connection to my FPGA.
I am searching a transciever or transciever/controler chip.
Do you now the best way to build an USB 2.0 interface, thinking 'Time To 
Market'?

In the case where I use a transciever and an integrated Serial Interface 
Engine do you know where can I find a SIE core for FPGA, or where can I 
find some doc about it.

Laurent Gauch
for Amontec


Article: 32056
Subject: Re: Pin locking in Maxplus2
From: Russell Shaw <rjshaw@iprimus.com.au>
Date: Wed, 13 Jun 2001 00:26:04 +1000
Links: << >>  << T >>  << A >>
It was 10.01 (with a patch). I got a reply about another patch from
altera to fix it, so am about to try it.

eteam wrote:
> 
> What version SW are you using?  The currrent release, 10.0, is
> pretty solid with Quartus fitter enabled or disabled.  Previous versions
> did have a problem with the Quartus fitter (which could be disabled).
> 
> Version 10.0 has been around for about 6 months or more.
> 
> -- bob elkind, the e-team -- fpga design, consulting
> 
> Russell Shaw wrote:
> >
> > Using the Quartus fitter in maxplus2 (for acex1k), it crashes at
> > 28% when doing a simple 32x8 lpm fifo function and not much else
> > (pc has 256MB ram). By setting the option not to use quartus, the
> > compilation completes without error. Have you found the same bugginess?
> >
> > bob elkind wrote:
> > >
> > > The Max7K family, in my experience, tends to be more finicky about
> > > being filled to >80% utilisation with pinouts pre-defined.  The 6K and the
> > > Acex 1K families (my current favourites) are much more forgiving in this
> > > regard (and of course, they also have many more pins :=) ).
> > >
> > > You may wish to consider replacing your Max7Ks device with a
> > > Flex6Ka (3.3V) or Acex1K (3.3V/2.5V) with an EPC2 (in-system
> > > programmable config EEROM).  You probably won't be very far
> > > removed in cost, and you will be light-years ahead in usable gates,
> > > power consumption, AC performance, and pinot flexibility.
> > >
> > > -- Bob Elkind, the e-team (fpga/asic design, consulting, etc.)
> > >

--
   ___                                           ___
  /  /\                                         /  /\
 /  /__\                                       /  /\/\
/__/   / Russell Shaw, B.Eng, M.Eng(Research) /__/\/\/
\  \  /  Victoria, Australia, Down-Under      \  \/\/
 \__\/                                         \__\/

Article: 32057
Subject: Re: High Speed Sampling Oscilloscope in an FPGA
From: John_H <johnhandwork@mail.com>
Date: Tue, 12 Jun 2001 15:42:55 GMT
Links: << >>  << T >>  << A >>
If you're looking for a true eye diagram, you've got a very stable underlying
clock for your signal.  If you want random pulse detection, there's little you
can do.  Please note that even if you see "Tektronix" somewhere in the message
header, I haven't messed with oscilloscopes - I work with printers.  My
background includes communications test equipment and clock impairment
generation.

If you have a 100MHz clock that you can get from your system under test which is
the basis for your eye diagram, the oversampling technique can work using an
analog PLL to that system clock of, say, 99.0099 MHz (more specifically
100*100/101 MHz), you'll have edges from this slaved clock that are 100pS
further from the reference clock each sample.  Keep a modulo 100 counter running
on your locked clock and you'll know how many 100pS samples you're away from
your bit edge (or some random point in your bit period).  The system can be
easily scaled to how ever many points you want.

If you desire true randomness associated with a trigger, life is more
difficult.  To measure the trigger point precisely *and* have decent sample
rates, I'd recommend quadrature sampling of a stable reference clock.  This gets
complex and expensive.  You need two sinusoidal waveforms - a sine and a cosine
- generated from your reference.  If you sample both waveforms at the same time
with your trigger, you get values of sin(x) and cos(x) where x is the phase at
the moment of sample.  You need to extract the phase from these digitized analog
values - complex but achievable in FPGAs (a CORDIC processor, for instance -
I've seen one on hammercores.com).  You can deal with the repetitive signal in
the PLL format I described and take the difference from your trigger (
atan(sin(x)/cos(x)) ) and your data sample to figure out the needed offset.

The system can get complicated.  If you have - or can extract - timing from your
sampled data you will get the least expensive approach and display any high
frequency jitter which is a part of your original signal;  this is part of what
I needed my eye diagrams to tell me.  If timing isn't available, the trigger
gets weird.

Notice that on some very-high-bandwidth scopes, some of the trigger rates are
<100kHz.  This is partly because of the time measurement technique used for the
trigger.  The quadrature sampling I mentioned allows faster time extraction than
some other methods.

Good luck!


Rune Baeverrud wrote:

> Hello, and thanks to everyone for sharing your insight in this group!
>
> I'm trying to figure out the basics for how you would/could implement a high
> speed digital oscilloscope with an FPGA, with an analoge bandwidth of at
> least a few GHz, and a sampling rate of a few hundred MHz. I'm in particular
> looking for "undersampling" techniques, where you can build eye diagrams of
> GHz analog waveforms using moderate sampling rates.
>
> In this context i've been thinking hard about the trigger mechanism. Just
> comparing digital sample values for determining trigger conditions would not
> work, because of the low granularity. (2 GHz analog waveform with 256 points
> resolution per period would yield a sample rate of 512GHz - which is
> obviously out of the question. Also - jitter introduced by this measuring
> method would be very bad). So - my conclusion so far is that the trigger
> mechanism has to be based on a good old analog comparator.
>
> Then comes the next part - which seems to be very tricky. In order to align
> the digital samples correctly in time - you would need to accurately know
> the time difference between the trigger point and the next sample point,
> and/or between the trigger point and the previous sample point. These time
> intervals could be in the ps range, and it seems to me that any clocked
> digital circuitry would be inadequate for this kind of time measurement. If
> you know both time intervals, I have an idea that the the accurateness of
> these time intervals may not be so important, since you could use the ratio
> of the two to align the trigger point compared to the sample points.
>
> Does anyone have any idea of how this is done by the big guys like Tektronix
> and LeCroy? And - do you know of any standard chips that could simplify this
> kind of application?
>
> Rune Baeverrud


Article: 32058
Subject: Re: Doing Ethernet in a Virtex ?
From: Muzaffer Kal <muzaffer@dspia.com>
Date: Tue, 12 Jun 2001 15:48:48 GMT
Links: << >>  << T >>  << A >>
On Mon, 11 Jun 2001 23:50:29 +0100, Rick Filipkiewicz
<rick@algor.co.uk> wrote:

>
>I'm trying to work out whether its possible to do Ethernet in an FPGA.
>Not just the MAC layer and then out on MII to an external PHY but
>connect directly to the TP transformer. Does anybody know if any of the
>Virtex2 differential IO standards would work either directly or with a
>minimal amount of level shifting ?
>
do you mean 10bt, 100btx or 1000bt (or something else :-) ? 10bt is
non-trivial but doable in an FPGA (have done it already). You need
some external components to drive and a comparator to receive. It is
difficult to be fully 802.3 compliant without a full AFE though.
100btx is very difficult even without the AFE issue (you need a 6 bit
250 (or 125) MHz ADC for a DSP implementation). It is possible with a
large and fast virtex-2 if you can put the AFE together (ADC+VGA on
the input. MLT3 driver on the output)

Muzaffer

FPGA DSP Consulting
http://www.dspia.com

Article: 32059
Subject: Re: Force tristate enable register into IOB
From: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
Date: Tue, 12 Jun 2001 18:09:32 +0200
Links: << >>  << T >>  << A >>
fred wrote:
> I use FPGA Express but have experienced similar problems.
> 
> My solution was to create a primitive entity that did work ie wrote code for
> a single IOB that worked, and then used a generate at a higher level to
> create multiple instances of that primative. With my synth tool (at the
> time) I even had to create a prim that had a TS (tristate) signal rather
> than an OE signal and invert it outside the primitive otherwise the tool
> would not infer the reg in the IOB - good huh. It was messy, but I have
> given up on trying to be too clever when having to hand-hold the tools.
> 
> With my toolset you also have top tell the synth tool _and_ the placement
> tool to set "use IOB regs = true" or "push regs into IOBs" or whatever
> equivalent to make this work.
> 
> Hope this helps, reply to group if you want code.
Could you post the hdl code of your "IOB-primitive" ? I still have
problems with tristate reg and io reg in the IOB !

Thanks very much
Matthias

-- 
-------------------------------------------------
\ Matthias Fuchs                                 \
 \ esd electronic system design Gmbh              \
  \ Vahrenwalder Straße 205                        \
   \ D-30165 Hannover                               \
    \ email: matthias.fuchs@esd-electronics.com      \
     \ phone: +49-511-37298-0                         \
      \ fax:   +49-511-37298-68                        \
       --------------------------------------------------

Article: 32060
Subject: Re: Doing Ethernet in a Virtex ?
From: Kolja Sulimma <kolja@sulimma.de>
Date: Tue, 12 Jun 2001 18:11:11 +0200
Links: << >>  << T >>  << A >>
> 10bt is
> non-trivial but doable in an FPGA (have done it already). You need
> some external components to drive and a comparator to receive.

Interesting. Do you have a schematic for a driver circuit?


> It is
> difficult to be fully 802.3 compliant without a full AFE though.

What is AFE?

> 100btx is very difficult even without the AFE issue (you need a 6 bit
> 250 (or 125) MHz ADC for a DSP implementation). It is possible with a
> large and fast virtex-2 if you can put the AFE together (ADC+VGA on
> the input. MLT3 driver on the output)

Kolja Sulimma


Article: 32061
Subject: Force routing on an Apex
From: "olivier" <oganry@hotmail.com>
Date: Tue, 12 Jun 2001 09:11:55 -0700
Links: << >>  << T >>  << A >>
Hi,

For some reasons, I need to be able to force the routing on a group of cells
in an Altera APEX400e.
I have to create two identical blocks of logic that have to have the same
routing. So far I could only lock the placement but the routing between the
blocks remains different (I would like to use only local routing). I checked
the ressource usage and it looks like that there are plenty of local routing
available in the area (within a MegaLab). Look to me that the router is
doing whatever he wants (even if I assign the local routing option), for one
cell he uses a "fast track fan out" routing type instead of a "local
routing"; whereas for the other identical block, same cell, he will use
"local routing".
Anybody knows how to constraint the router of QuartusII???

Thanks
Olivier



Article: 32062
(removed)


Article: 32063
(removed)


Article: 32064
Subject: Re: Virtex LUT4 problems in FPGA Express
From: Ray Andraka <ray@andraka.com>
Date: Tue, 12 Jun 2001 17:54:30 GMT
Links: << >>  << T >>  << A >>
This is good news.  can you also special case the SRL16's in the same way?  It
would be most helpful for designs that use the SRL16 as a reloadable LUT.  Same
for the CLB RAM and ROM and block RAMs.  

Ken McElvain wrote:
> 
> 
> Actually, if you instantiate a LUT4 with a INIT generic/parameter in Synplify
> it will work fine and produce a LUT in the output EDIF programed with
> your INIT generic.  If you are using verilog, you will need to include
> .../synplify/lib/xilinx/virtex.v and for VHDL you need to use the stmts.
> 
> library virtex;
> use virtex.components.all;
> 
> LUTS have been special cased.

-- 
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com

Article: 32065
Subject: Re: Virtex LUT4 problems in FPGA Express
From: Ray Andraka <ray@andraka.com>
Date: Tue, 12 Jun 2001 18:27:50 GMT
Links: << >>  << T >>  << A >>
This is good news.  can you also special case the SRL16's in the same way?  It
would be most helpful for designs that use the SRL16 as a reloadable LUT.  Same
for the CLB RAM and ROM and block RAMs.  

Ken McElvain wrote:
> 
> 
> Actually, if you instantiate a LUT4 with a INIT generic/parameter in Synplify
> it will work fine and produce a LUT in the output EDIF programed with
> your INIT generic.  If you are using verilog, you will need to include
> .../synplify/lib/xilinx/virtex.v and for VHDL you need to use the stmts.
> 
> library virtex;
> use virtex.components.all;
> 
> LUTS have been special cased.

-- 
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com

Article: 32066
Subject: Re: Pin locking in Maxplus2
From: bob elkind <eteam@aracnet.com>
Date: Tue, 12 Jun 2001 11:47:56 -0700
Links: << >>  << T >>  << A >>
Hmmm....  I had no probs with 10.0 (no patch).  I wonder if the patch
may be a problem.  Maybe someone else listening in on this thread might
have some data to help correlate our experiences.  Also, I was targeting
only 6K and Acex1K devices.

Hmmm....

-- Bob Elkind, -- fpga design, consulting

Russell Shaw wrote:

> It was 10.01 (with a patch). I got a reply about another patch from
> altera to fix it, so am about to try it.
>
> eteam wrote:
> >
> > What version SW are you using?  The currrent release, 10.0, is
> > pretty solid with Quartus fitter enabled or disabled.  Previous versions
> > did have a problem with the Quartus fitter (which could be disabled).
> >
> > Version 10.0 has been around for about 6 months or more.
> >
> > -- bob elkind, the e-team -- fpga design, consulting
>


Article: 32067
Subject: Re: USB for a new FPGA based product, which transciever ?
From: "Felix Bertram" <fbertram@gmx.net>
Date: Tue, 12 Jun 2001 21:30:37 +0200
Links: << >>  << T >>  << A >>
Laurent,

"Laurent Gauch" <laurent.gauch@amontec.com> schrieb im Newsbeitrag
news:3B261466.9080405@amontec.com...
> Dear all,
>
> For a new product, I want to have an USB 2.0 connection to my FPGA.

USB 2.0 is forward and backward compatible to USB 1.1. Therefore USB 2.0
contains everything that USB 1.1 does- plus the 480Mbps speed. Important
question here: Does your application require 480Mbps? If not, you can stick
to USB 1.1 solutions.

> I am searching a transciever or transciever/controler chip.
> Do you now the best way to build an USB 2.0 interface, thinking 'Time To
> Market'?

I would try to chose from available IP as testing and debugging a Serial
Interface Engine is a time-consuming task to do.

> In the case where I use a transciever and an integrated Serial Interface
> Engine do you know where can I find a SIE core for FPGA, or where can I
> find some doc about it.

There are application notes, product specifications and a complete
behavioral VHDL model of our "full speed" (12Mbps) USB Function Controller
on our web site- visit www.trenz-electronic.de

Designing a "high speed" (480Mbps) USB Function Controller is quite similar
to "full speed" (12Mbps) or "low speed" (1.5Mbps)- the following things come
to my mind:
* UTMI transceivers used for 480Mbps already contain the PLL, NRZI coding &
decoding and bitstuffing blocks. These transceivers provide 8 or 16bit
parallel data.
* new tokens NYET, PING and DATA2 require minor extensions to the
transaction layer

Hope this helps,
best regards

Felix Bertram
___
Dipl.-Ing. Felix Bertram
Trenz Electronic
Duenner Kirchweg 77
D - 32257 Buende
Tel.: +49 (0) 5223 4939755
Fax.: +49 (0) 5223 48945
Mailto:f.bertram@trenz-electronic.de
http://www.trenz-electronic.de





Article: 32068
Subject: Video Compression on an FPGA
From: jad@aedinc.net (Jason Daughenbaugh)
Date: 12 Jun 2001 12:52:53 -0700
Links: << >>  << T >>  << A >>
Hello all,

I am looking for any information on video compression/decompression 
on an FPGA.  I am interested in IP cores, papers on implementation,
etc.  I don't want algorithms that are too lossy - lossless or near
lossless are all I can consider.  JPEG-2000, JPEG-LS, or others.  Can
MPEG-4 or MPEG-7 be near-lossless?

We want to be able to process 24 bit RGB at 45Mpix/s or faster.  I
don't think that DSPs can do it, a massively parallel FPGA
architecture or an ASIC are probably the only choices.

I have looked at the ADV-JP2000 Codec.  It is a cool IC, but can only
do 10Mpix/s (with only one color component, slow with more?).  I would
also be interested in any similar chips (but faster) that might be
able to do this processing, and then I could glue it to an FPGA.

I have little experience with video CODECs, so I would appreciate any
advice on where to look.

Thanks!
Jason Daughenbaugh
http://www.aedinc.net

Article: 32069
Subject: Re: Triscend A5: can it reconfigure itself?
From: sknapp@triscend.com (Steven K. Knapp)
Date: 12 Jun 2001 13:34:37 -0700
Links: << >>  << T >>  << A >>
This is possible with the Triscend E5.  You can either have the E5
load different images out of the same Flash device or remotely update
the E5 via a serial port or some other communciations method.

There is an application note that describes how to perform remote
updates at the following link.  There is also an associated project
file with demonstration code.

"AN02: Implementing Secure Remote Updates using Triscend E5
Configurable System-on-Chip Devices"
http://www.triscend.com/products/TextTechLit.html#appnotes

Steven Knapp
Triscend Corporation


ariasm@inaoep.mx (Miguel Arias) wrote in message news:<ad5d52be.0106081408.63db47b7@posting.google.com>...
> Hello,
> 
> I am planning an application where I need a remote FPGA based
> architecture which I want to reconfigure using a microcontroller. The
> Triscend E5 CSoc (8051 + FPGA) specifications seem very interesting
> since all resides in a single chip but, is it possible to reconfigure
> the FPGA part of the chip using a program in the internal
> microcontroller?
> 
> Based on the specifications, reconfiguration goes through the JTAG
> input, which I could control using the PIOs of the E5, but for
> security reasons, I would prefer to find out an internal way to do
> this, is it possible?
> 
> Thanks for any comments with a copy to my email.
> 
> Miguel 
> FPGAs for Computer Vision
> INAOE - Mexico

Article: 32070
Subject: Virtex, Routing Error
From: "Hu Chen" <>
Date: Tue, 12 Jun 2001 13:47:43 -0700
Links: << >>  << T >>  << A >>
Virtex 800-hq240 -4;
bitgen -l -m -w -g ConfigRate:4 -g CclkPin:PULLUP -g TdoPin:PULLNONE -g M1Pin:PULLUP -g DonePin:PULLUP -g DriveDone:No -g StartUpClk:CCLK -g DONE_cycle:4 -g GTS_cycle:5 -g GSR_cycle:6 -g M0Pin:PULLUP -g M2Pin:PULLUP -g ProgPin:PULLUP -g TckPin:PULLUP -g TdiPin:PULLUP -g TmsPin:PULLUP -g DonePipe:No -g GWE_cycle:6 -g LCK_cycle:NoWait -g Security:NONE 

I got the following error and I have no idea at all.

ERROR:DesignRules:10 - Netcheck: The signal "GLOBAL_LOGIC0" is completely
   unrouted.

Thanks a lot.

Chen

Article: 32071
Subject: Re: Virtex, Routing Error
From: Vikram Pasham <Vikram.Pasham@xilinx.com>
Date: Tue, 12 Jun 2001 14:14:42 -0700
Links: << >>  << T >>  << A >>

Hu,

This is fixed in 3.1i service packs. Download SP8 from
http://support.xilinx.com/support/techsup/sw_updates/

-Vikram
Xilinx Applications

Hu Chen wrote:

> Virtex 800-hq240 -4;
> bitgen -l -m -w -g ConfigRate:4 -g CclkPin:PULLUP -g TdoPin:PULLNONE -g M1Pin:PULLUP -g DonePin:PULLUP -g DriveDone:No -g StartUpClk:CCLK -g DONE_cycle:4 -g GTS_cycle:5 -g GSR_cycle:6 -g M0Pin:PULLUP -g M2Pin:PULLUP -g ProgPin:PULLUP -g TckPin:PULLUP -g TdiPin:PULLUP -g TmsPin:PULLUP -g DonePipe:No -g GWE_cycle:6 -g LCK_cycle:NoWait -g Security:NONE
>
> I got the following error and I have no idea at all.
>
> ERROR:DesignRules:10 - Netcheck: The signal "GLOBAL_LOGIC0" is completely
>    unrouted.
>
> Thanks a lot.
>
> Chen


Article: 32072
Subject: Re: Virtex, Routing Error
From: Vikram Pasham <Vikram.Pasham@xilinx.com>
Date: Tue, 12 Jun 2001 14:14:52 -0700
Links: << >>  << T >>  << A >>

Hu,

This is fixed in 3.1i service packs. Download SP8 from
http://support.xilinx.com/support/techsup/sw_updates/

-Vikram
Xilinx Applications

Hu Chen wrote:

> Virtex 800-hq240 -4;
> bitgen -l -m -w -g ConfigRate:4 -g CclkPin:PULLUP -g TdoPin:PULLNONE -g M1Pin:PULLUP -g DonePin:PULLUP -g DriveDone:No -g StartUpClk:CCLK -g DONE_cycle:4 -g GTS_cycle:5 -g GSR_cycle:6 -g M0Pin:PULLUP -g M2Pin:PULLUP -g ProgPin:PULLUP -g TckPin:PULLUP -g TdiPin:PULLUP -g TmsPin:PULLUP -g DonePipe:No -g GWE_cycle:6 -g LCK_cycle:NoWait -g Security:NONE
>
> I got the following error and I have no idea at all.
>
> ERROR:DesignRules:10 - Netcheck: The signal "GLOBAL_LOGIC0" is completely
>    unrouted.
>
> Thanks a lot.
>
> Chen


Article: 32073
Subject: Re: Video Compression on an FPGA
From: Vikram Pasham <Vikram.Pasham@xilinx.com>
Date: Tue, 12 Jun 2001 14:57:08 -0700
Links: << >>  << T >>  << A >>
Jason,

By definition, JPEG and MPEG are lossy compression algorithms.  With both
these standards, its possible to control the percentage of lossy data.. In
JPEG software compressors, its possible to vary the "quality" settings to
vary compression ratios. FPGA are widely used in Video processing for
implementing JPEG codecs, DCT, IDCT, Color converters etc. and these IPs
are available in the market.

Refer Xilinx's Video and Image Processing website at
http://www.xilinx.com/ipcenter/vid_img_proc.htm

Hope this helps !!!

-Vikram
Xilinx Applications


Jason Daughenbaugh wrote:

> Hello all,
>
> I am looking for any information on video compression/decompression
> on an FPGA.  I am interested in IP cores, papers on implementation,
> etc.  I don't want algorithms that are too lossy - lossless or near
> lossless are all I can consider.  JPEG-2000, JPEG-LS, or others.  Can
> MPEG-4 or MPEG-7 be near-lossless?
>
> We want to be able to process 24 bit RGB at 45Mpix/s or faster.  I
> don't think that DSPs can do it, a massively parallel FPGA
> architecture or an ASIC are probably the only choices.
>
> I have looked at the ADV-JP2000 Codec.  It is a cool IC, but can only
> do 10Mpix/s (with only one color component, slow with more?).  I would
> also be interested in any similar chips (but faster) that might be
> able to do this processing, and then I could glue it to an FPGA.
>
> I have little experience with video CODECs, so I would appreciate any
> advice on where to look.
>
> Thanks!
> Jason Daughenbaugh
> http://www.aedinc.net


Article: 32074
Subject: Re: Virtex, Routing Error
From: Ray Andraka <ray@andraka.com>
Date: Tue, 12 Jun 2001 23:58:09 GMT
Links: << >>  << T >>  << A >>
what version of the tools are you using, and what service pack?  A while back
there was a problem with the router dealing with the logic zero and logic one
constants in the design.  This was resolved by xilinx over a year ago.  If you
are using an older version of the tools, then you should update to the latest
release, or at the very least check the answers database on the xilinx website
for the interim workaround solution that was posted before the next service pack
was released.  

Hu Chen wrote:
> 
> Virtex 800-hq240 -4;
> bitgen -l -m -w -g ConfigRate:4 -g CclkPin:PULLUP -g TdoPin:PULLNONE -g M1Pin:PULLUP -g DonePin:PULLUP -g DriveDone:No -g StartUpClk:CCLK -g DONE_cycle:4 -g GTS_cycle:5 -g GSR_cycle:6 -g M0Pin:PULLUP -g M2Pin:PULLUP -g ProgPin:PULLUP -g TckPin:PULLUP -g TdiPin:PULLUP -g TmsPin:PULLUP -g DonePipe:No -g GWE_cycle:6 -g LCK_cycle:NoWait -g Security:NONE
> 
> I got the following error and I have no idea at all.
> 
> ERROR:DesignRules:10 - Netcheck: The signal "GLOBAL_LOGIC0" is completely
>    unrouted.
> 
> Thanks a lot.
> 
> Chen

-- 
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com



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